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https://github.com/g-truc/glm.git
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glm-aarch64: Add neon's mat4 inverse
This commit is contained in:
Amaury Le Leyzour
parent
7eb810be81
commit
a2403634da
@ -103,17 +103,10 @@ namespace glm {
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auto MulRow = [&](int l) {
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float32x4_t const SrcA = m2[l].data;
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#if GLM_ARCH & GLM_ARCH_ARMV8_BIT
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float32x4_t r= vmulq_laneq_f32(m1[0].data, SrcA, 0);
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r = vaddq_f32(r, vmulq_laneq_f32(m1[1].data, SrcA, 1));
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r = vaddq_f32(r, vmulq_laneq_f32(m1[2].data, SrcA, 2));
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r = vaddq_f32(r, vmulq_laneq_f32(m1[3].data, SrcA, 3));
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#else
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float32x4_t r= vmulq_f32(m1[0].data, vdupq_n_f32(vgetq_lane_f32(SrcA, 0)));
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r = vaddq_f32(r, vmulq_f32(m1[1].data, vdupq_n_f32(vgetq_lane_f32(SrcA, 1))));
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r = vaddq_f32(r, vmulq_f32(m1[2].data, vdupq_n_f32(vgetq_lane_f32(SrcA, 2))));
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r = vaddq_f32(r, vmulq_f32(m1[3].data, vdupq_n_f32(vgetq_lane_f32(SrcA, 3))));
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#endif
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float32x4_t r = neon::mul_lane(m1[0].data, SrcA, 0);
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r = neon::madd_lane(r, m1[1].data, SrcA, 1);
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r = neon::madd_lane(r, m1[2].data, SrcA, 2);
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r = neon::madd_lane(r, m1[3].data, SrcA, 3);
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return r;
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};
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@ -127,5 +120,130 @@ namespace glm {
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return Result;
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}
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#endif // CXX11
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template<qualifier Q>
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struct detail::compute_inverse<4, 4, float, Q, true>
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{
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GLM_FUNC_QUALIFIER static mat<4, 4, float, Q> call(mat<4, 4, float, Q> const& m)
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{
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float32x4_t const& m0 = m[0].data;
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float32x4_t const& m1 = m[1].data;
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float32x4_t const& m2 = m[2].data;
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float32x4_t const& m3 = m[3].data;
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// m[2][2] * m[3][3] - m[3][2] * m[2][3];
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// m[2][2] * m[3][3] - m[3][2] * m[2][3];
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// m[1][2] * m[3][3] - m[3][2] * m[1][3];
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// m[1][2] * m[2][3] - m[2][2] * m[1][3];
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float32x4_t Fac0;
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{
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float32x4_t w0 = vcombine_f32(neon::dup_lane(m2, 2), neon::dup_lane(m1, 2));
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float32x4_t w1 = neon::copy_lane(neon::dupq_lane(m3, 3), 3, m2, 3);
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float32x4_t w2 = neon::copy_lane(neon::dupq_lane(m3, 2), 3, m2, 2);
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float32x4_t w3 = vcombine_f32(neon::dup_lane(m2, 3), neon::dup_lane(m1, 3));
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Fac0 = w0 * w1 - w2 * w3;
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}
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// m[2][1] * m[3][3] - m[3][1] * m[2][3];
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// m[2][1] * m[3][3] - m[3][1] * m[2][3];
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// m[1][1] * m[3][3] - m[3][1] * m[1][3];
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// m[1][1] * m[2][3] - m[2][1] * m[1][3];
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float32x4_t Fac1;
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{
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float32x4_t w0 = vcombine_f32(neon::dup_lane(m2, 1), neon::dup_lane(m1, 1));
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float32x4_t w1 = neon::copy_lane(neon::dupq_lane(m3, 3), 3, m2, 3);
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float32x4_t w2 = neon::copy_lane(neon::dupq_lane(m3, 1), 3, m2, 1);
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float32x4_t w3 = vcombine_f32(neon::dup_lane(m2, 3), neon::dup_lane(m1, 3));
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Fac1 = w0 * w1 - w2 * w3;
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}
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// m[2][1] * m[3][2] - m[3][1] * m[2][2];
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// m[2][1] * m[3][2] - m[3][1] * m[2][2];
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// m[1][1] * m[3][2] - m[3][1] * m[1][2];
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// m[1][1] * m[2][2] - m[2][1] * m[1][2];
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float32x4_t Fac2;
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{
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float32x4_t w0 = vcombine_f32(neon::dup_lane(m2, 1), neon::dup_lane(m1, 1));
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float32x4_t w1 = neon::copy_lane(neon::dupq_lane(m3, 2), 3, m2, 2);
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float32x4_t w2 = neon::copy_lane(neon::dupq_lane(m3, 1), 3, m2, 1);
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float32x4_t w3 = vcombine_f32(neon::dup_lane(m2, 2), neon::dup_lane(m1, 2));
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Fac2 = w0 * w1 - w2 * w3;
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}
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// m[2][0] * m[3][3] - m[3][0] * m[2][3];
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// m[2][0] * m[3][3] - m[3][0] * m[2][3];
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// m[1][0] * m[3][3] - m[3][0] * m[1][3];
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// m[1][0] * m[2][3] - m[2][0] * m[1][3];
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float32x4_t Fac3;
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{
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float32x4_t w0 = vcombine_f32(neon::dup_lane(m2, 0), neon::dup_lane(m1, 0));
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float32x4_t w1 = neon::copy_lane(neon::dupq_lane(m3, 3), 3, m2, 3);
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float32x4_t w2 = neon::copy_lane(neon::dupq_lane(m3, 0), 3, m2, 0);
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float32x4_t w3 = vcombine_f32(neon::dup_lane(m2, 3), neon::dup_lane(m1, 3));
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Fac3 = w0 * w1 - w2 * w3;
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}
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// m[2][0] * m[3][2] - m[3][0] * m[2][2];
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// m[2][0] * m[3][2] - m[3][0] * m[2][2];
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// m[1][0] * m[3][2] - m[3][0] * m[1][2];
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// m[1][0] * m[2][2] - m[2][0] * m[1][2];
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float32x4_t Fac4;
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{
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float32x4_t w0 = vcombine_f32(neon::dup_lane(m2, 0), neon::dup_lane(m1, 0));
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float32x4_t w1 = neon::copy_lane(neon::dupq_lane(m3, 2), 3, m2, 2);
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float32x4_t w2 = neon::copy_lane(neon::dupq_lane(m3, 0), 3, m2, 0);
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float32x4_t w3 = vcombine_f32(neon::dup_lane(m2, 2), neon::dup_lane(m1, 2));
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Fac4 = w0 * w1 - w2 * w3;
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}
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// m[2][0] * m[3][1] - m[3][0] * m[2][1];
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// m[2][0] * m[3][1] - m[3][0] * m[2][1];
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// m[1][0] * m[3][1] - m[3][0] * m[1][1];
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// m[1][0] * m[2][1] - m[2][0] * m[1][1];
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float32x4_t Fac5;
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{
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float32x4_t w0 = vcombine_f32(neon::dup_lane(m2, 0), neon::dup_lane(m1, 0));
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float32x4_t w1 = neon::copy_lane(neon::dupq_lane(m3, 1), 3, m2, 1);
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float32x4_t w2 = neon::copy_lane(neon::dupq_lane(m3, 0), 3, m2, 0);
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float32x4_t w3 = vcombine_f32(neon::dup_lane(m2, 1), neon::dup_lane(m1, 1));
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Fac5 = w0 * w1 - w2 * w3;
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}
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float32x4_t Vec0 = neon::copy_lane(neon::dupq_lane(m0, 0), 0, m1, 0); // (m[1][0], m[0][0], m[0][0], m[0][0]);
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float32x4_t Vec1 = neon::copy_lane(neon::dupq_lane(m0, 1), 0, m1, 1); // (m[1][1], m[0][1], m[0][1], m[0][1]);
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float32x4_t Vec2 = neon::copy_lane(neon::dupq_lane(m0, 2), 0, m1, 2); // (m[1][2], m[0][2], m[0][2], m[0][2]);
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float32x4_t Vec3 = neon::copy_lane(neon::dupq_lane(m0, 3), 0, m1, 3); // (m[1][3], m[0][3], m[0][3], m[0][3]);
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float32x4_t Inv0 = Vec1 * Fac0 - Vec2 * Fac1 + Vec3 * Fac2;
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float32x4_t Inv1 = Vec0 * Fac0 - Vec2 * Fac3 + Vec3 * Fac4;
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float32x4_t Inv2 = Vec0 * Fac1 - Vec1 * Fac3 + Vec3 * Fac5;
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float32x4_t Inv3 = Vec0 * Fac2 - Vec1 * Fac4 + Vec2 * Fac5;
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float32x4_t r0 = float32x4_t{-1, +1, -1, +1} * Inv0;
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float32x4_t r1 = float32x4_t{+1, -1, +1, -1} * Inv1;
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float32x4_t r2 = float32x4_t{-1, +1, -1, +1} * Inv2;
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float32x4_t r3 = float32x4_t{+1, -1, +1, -1} * Inv3;
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float32x4_t det = neon::mul_lane(r0, m0, 0);
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det = neon::madd_lane(det, r1, m0, 1);
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det = neon::madd_lane(det, r2, m0, 2);
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det = neon::madd_lane(det, r3, m0, 3);
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float32x4_t rdet = vdupq_n_f32(1 / vgetq_lane_f32(det, 0));
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mat<4, 4, float, Q> r;
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r[0].data = vmulq_f32(r0, rdet);
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r[1].data = vmulq_f32(r1, rdet);
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r[2].data = vmulq_f32(r2, rdet);
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r[3].data = vmulq_f32(r3, rdet);
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return r;
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}
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};
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}//namespace glm
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#endif
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155
glm/simd/neon.h
Normal file
155
glm/simd/neon.h
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@ -0,0 +1,155 @@
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/// @ref simd_neon
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/// @file glm/simd/neon.h
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#pragma once
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#if GLM_ARCH & GLM_ARCH_NEON_BIT
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#include <arm_neon.h>
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namespace glm {
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namespace neon {
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static float32x4_t dupq_lane(float32x4_t vsrc, int lane) {
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switch(lane) {
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#if GLM_ARCH & GLM_ARCH_ARMV8_BIT
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case 0: return vdupq_laneq_f32(vsrc, 0);
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case 1: return vdupq_laneq_f32(vsrc, 1);
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case 2: return vdupq_laneq_f32(vsrc, 2);
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case 3: return vdupq_laneq_f32(vsrc, 3);
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#else
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case 0: return vdupq_n_f32(vgetq_lane_f32(vsrc, 0));
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case 1: return vdupq_n_f32(vgetq_lane_f32(vsrc, 1));
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case 2: return vdupq_n_f32(vgetq_lane_f32(vsrc, 2));
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case 3: return vdupq_n_f32(vgetq_lane_f32(vsrc, 3));
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#endif
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}
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assert(!"Unreachable code executed!");
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return vdupq_n_f32(0.0f);
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}
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static float32x2_t dup_lane(float32x4_t vsrc, int lane) {
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switch(lane) {
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#if GLM_ARCH & GLM_ARCH_ARMV8_BIT
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case 0: return vdup_laneq_f32(vsrc, 0);
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case 1: return vdup_laneq_f32(vsrc, 1);
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case 2: return vdup_laneq_f32(vsrc, 2);
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case 3: return vdup_laneq_f32(vsrc, 3);
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#else
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case 0: return vdup_n_f32(vgetq_lane_f32(vsrc, 0));
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case 1: return vdup_n_f32(vgetq_lane_f32(vsrc, 1));
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case 2: return vdup_n_f32(vgetq_lane_f32(vsrc, 2));
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case 3: return vdup_n_f32(vgetq_lane_f32(vsrc, 3));
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#endif
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}
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assert(!"Unreachable code executed!");
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return vdup_n_f32(0.0f);
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}
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static float32x4_t copy_lane(float32x4_t vdst, int dlane, float32x4_t vsrc, int slane) {
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#if GLM_ARCH & GLM_ARCH_ARMV8_BIT
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switch(dlane) {
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case 0:
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switch(slane) {
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case 0: return vcopyq_laneq_f32(vdst, 0, vsrc, 0);
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case 1: return vcopyq_laneq_f32(vdst, 0, vsrc, 1);
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case 2: return vcopyq_laneq_f32(vdst, 0, vsrc, 2);
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case 3: return vcopyq_laneq_f32(vdst, 0, vsrc, 3);
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}
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assert(!"Unreachable code executed!");
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case 1:
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switch(slane) {
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case 0: return vcopyq_laneq_f32(vdst, 1, vsrc, 0);
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case 1: return vcopyq_laneq_f32(vdst, 1, vsrc, 1);
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case 2: return vcopyq_laneq_f32(vdst, 1, vsrc, 2);
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case 3: return vcopyq_laneq_f32(vdst, 1, vsrc, 3);
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}
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assert(!"Unreachable code executed!");
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case 2:
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switch(slane) {
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case 0: return vcopyq_laneq_f32(vdst, 2, vsrc, 0);
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case 1: return vcopyq_laneq_f32(vdst, 2, vsrc, 1);
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case 2: return vcopyq_laneq_f32(vdst, 2, vsrc, 2);
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case 3: return vcopyq_laneq_f32(vdst, 2, vsrc, 3);
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}
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assert(!"Unreachable code executed!");
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case 3:
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switch(slane) {
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case 0: return vcopyq_laneq_f32(vdst, 3, vsrc, 0);
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case 1: return vcopyq_laneq_f32(vdst, 3, vsrc, 1);
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case 2: return vcopyq_laneq_f32(vdst, 3, vsrc, 2);
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case 3: return vcopyq_laneq_f32(vdst, 3, vsrc, 3);
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}
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assert(!"Unreachable code executed!");
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}
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#else
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float l;
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switch(slane) {
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case 0: l = vgetq_lane_f32(vsrc, 0); break;
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case 1: l = vgetq_lane_f32(vsrc, 1); break;
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case 2: l = vgetq_lane_f32(vsrc, 2); break;
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case 3: l = vgetq_lane_f32(vsrc, 3); break;
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default:
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assert(!"Unreachable code executed!");
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}
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switch(dlane) {
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case 0: return vsetq_lane_f32(l, vdst, 0);
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case 1: return vsetq_lane_f32(l, vdst, 1);
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case 2: return vsetq_lane_f32(l, vdst, 2);
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case 3: return vsetq_lane_f32(l, vdst, 3);
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}
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#endif
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assert(!"Unreachable code executed!");
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return vdupq_n_f32(0.0f);
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}
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static float32x4_t mul_lane(float32x4_t v, float32x4_t vlane, int lane) {
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#if GLM_ARCH & GLM_ARCH_ARMV8_BIT
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switch(lane) {
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case 0: return vmulq_laneq_f32(v, vlane, 0); break;
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case 1: return vmulq_laneq_f32(v, vlane, 1); break;
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case 2: return vmulq_laneq_f32(v, vlane, 2); break;
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case 3: return vmulq_laneq_f32(v, vlane, 3); break;
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default:
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assert(!"Unreachable code executed!");
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}
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assert(!"Unreachable code executed!");
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return vdupq_n_f32(0.0f);
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#else
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return vmulq_f32(v, dupq_lane(vlane, lane));
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#endif
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}
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static float32x4_t madd_lane(float32x4_t acc, float32x4_t v, float32x4_t vlane, int lane) {
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#if GLM_ARCH & GLM_ARCH_ARMV8_BIT
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#ifdef GLM_CONFIG_FORCE_FMA
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# define FMADD_LANE(acc, x, y, L) do { asm volatile ("fmla %0.4s, %1.4s, %2.4s" : "+w"(acc) : "w"(x), "w"(dup_lane(y, L))); } while(0)
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#else
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# define FMADD_LANE(acc, x, y, L) do { acc = vmlaq_laneq_f32(acc, x, y, L); } while(0)
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#endif
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switch(lane) {
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case 0:
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FMADD_LANE(acc, v, vlane, 0);
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return acc;
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case 1:
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FMADD_LANE(acc, v, vlane, 1);
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return acc;
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case 2:
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FMADD_LANE(acc, v, vlane, 2);
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return acc;
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case 3:
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FMADD_LANE(acc, v, vlane, 3);
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return acc;
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default:
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assert(!"Unreachable code executed!");
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}
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assert(!"Unreachable code executed!");
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return vdupq_n_f32(0.0f);
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# undef FMADD_LANE
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#else
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return vaddq_f32(acc, vmulq_f32(v, dupq_lane(vlane, lane)));
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#endif
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}
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} //namespace neon
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} // namespace glm
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#endif // GLM_ARCH & GLM_ARCH_NEON_BIT
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@ -364,7 +364,7 @@
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#elif GLM_ARCH & GLM_ARCH_SSE2_BIT
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# include <emmintrin.h>
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#elif GLM_ARCH & GLM_ARCH_NEON_BIT
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# include <arm_neon.h>
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# include "neon.h"
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#endif//GLM_ARCH
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#if GLM_ARCH & GLM_ARCH_SSE2_BIT
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