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Fixed isnan for Intel compiler
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b1ecabdd28
commit
b012c80771
@ -40,6 +40,8 @@ elseif(NOT GLM_TEST_ENABLE_MS_EXTENSIONS)
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endif()
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endif()
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#set(GLM_SIMD_INSTRUCTION_SET "" CACHE STRING "Instruction set. Possible values are SSE1, SSE2")
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option(GLM_TEST_ENABLE_SIMD "Enable SIMD optimizations" OFF)
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if(GLM_TEST_ENABLE_SIMD)
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if(CMAKE_COMPILER_IS_GNUCXX)
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@ -809,8 +809,15 @@ namespace detail
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{
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GLM_STATIC_ASSERT(detail::type<genType>::is_float, "'isnan' only accept floating-point inputs");
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# if(GLM_COMPILER & GLM_COMPILER_VC)
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# if(GLM_COMPILER & (GLM_COMPILER_VC | GLM_COMPILER_INTEL))
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return _isnan(x) != 0;
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# elif(GLM_COMPILER & GLM_COMPILER_GCC)
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# if(GLM_PLATFORM & GLM_PLATFORM_ANDROID)
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return _isnan(x) != 0;
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# else
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return std::isnan(x);
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# endif
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/*
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# elif(GLM_COMPILER & GLM_COMPILER_GCC)
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# if(GLM_PLATFORM & GLM_PLATFORM_ANDROID)
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return _isnan(x) != 0;
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@ -818,7 +825,8 @@ namespace detail
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return std::isnan(x);
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# endif
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# elif(GLM_COMPILER & GLM_COMPILER_INTEL)
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return isnan(x) != 0;
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return _isnan(x) != 0;
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*/
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# else
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return std::isnan(x);
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# endif
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@ -364,14 +364,14 @@ int test_isnan()
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Error += true == glm::any(glm::isnan(glm::dvec3(0.0 / Zero_d))) ? 0 : 1;
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Error += true == glm::any(glm::isnan(glm::dvec4(0.0 / Zero_d))) ? 0 : 1;
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}
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/*
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{
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Error += true == glm::isnan(0.0f/Zero_f) ? 0 : 1;
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Error += true == glm::any(glm::isnan(glm::vec2(0.0f/Zero_f))) ? 0 : 1;
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Error += true == glm::any(glm::isnan(glm::vec3(0.0f/Zero_f))) ? 0 : 1;
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Error += true == glm::any(glm::isnan(glm::vec4(0.0f/Zero_f))) ? 0 : 1;
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}
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*/
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return Error;
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}
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