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Clean up SIMD Support subsection

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- Also use the \glmheader{} macro
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Jesse Talavera-Greenberg 2015-11-27 17:33:37 -05:00
parent bfbd8d8bcb
commit bfc4fa7b5d
1 changed files with 5 additions and 5 deletions
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@ -396,13 +396,13 @@ Later standards will override earlier ones, like so:
\subsection{SIMD Support} \subsection{SIMD Support}
GLM provides some SIMD (Single instruction, multiple data) optimizations based on compiler intrinsics. These optimizations will be automatically utilized based on the compiler arguments. For example with Visual C++, if a program is compiled with \verb|/arch:AVX|, GLM will use code paths relying on AVX instructions. GLM provides some SIMD (Single instruction, multiple data) optimizations based on compiler intrinsics, which will be automatically utilized based on compiler's arguments. For example, if a program is compiled in Visual C++ with \verb|/arch:AVX| set, certain GLM functionality will use AVX instructions.
Furthermore, GLM provides specialized vec4 and mat4 through two extensions, \verb|GLM_GTX_simd_vec4| and \verb|GLM_GTX_simd_mat4|. In addition, GLM provides specialized \verb|vec4|, \verb|quat|, and \verb|mat4| implementations through the \verb|GLM_GTX_simd_vec4|, \verb|GLM_GTX_simd_quat|, and \verb|GLM_GTX_simd_mat4| extensions.
A programmer can restrict or force instruction sets used by GLM using the following defines: \verb|GLM_FORCE_SSE2|, \verb|GLM_FORCE_SSE3|, \verb|GLM_FORCE_SSE4|, \verb|GLM_FORCE_AVX| or \verb|GLM_FORCE_AVX2|. A programmer can force GLM to use a particular set of intrinsics with the following defines: \verb|GLM_FORCE_SSE2|, \verb|GLM_FORCE_SSE3|, \verb|GLM_FORCE_SSE4|, \verb|GLM_FORCE_AVX| or \verb|GLM_FORCE_AVX2|.
A programmer can discard the use of intrinsics by defining \verb|GLM_FORCE_PURE| before any inclusion of \verb|<glm/glm.hpp>|. If \verb|GLM_FORCE_PURE| is defined, then including a SIMD extension will generate a compiler error. Intrinsics may also be disabled entirely by defining \verb|GLM_FORCE_PURE| before any inclusion of \glmheader{glm}. If \verb|GLM_FORCE_PURE| is defined, then including any SIMD extension will generate a compiler error.
\begin{cppcode} \begin{cppcode}
#define GLM_FORCE_PURE #define GLM_FORCE_PURE
@ -417,7 +417,7 @@ Useful as \verb|GLM_FORCE_PURE| is, I suggest you enforce this with compiler arg
#define GLM_FORCE_AVX2 #define GLM_FORCE_AVX2
#include <glm/glm.hpp> #include <glm/glm.hpp>
// Will only compile if the compiler supports AVX2 instrinsics. // Will only compile if AVX2 intrinsics are supported.
\end{cppcode} \end{cppcode}
\subsection{Force Inline} \subsection{Force Inline}