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Fixed SIMD support detection
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@ -700,73 +700,73 @@ namespace glm
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# endif
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// Report build target
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# if GLM_ARCH == GLM_ARCH_X86
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# if GLM_MODEL == GLM_MODEL_64
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# pragma message("GLM: x86 64 bits build target")
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# else
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# pragma message("GLM: x86 32 bits build target")
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# endif
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# elif GLM_ARCH == GLM_ARCH_AVX2
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# if GLM_ARCH & GLM_ARCH_AVX2_BIT
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# if GLM_MODEL == GLM_MODEL_64
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# pragma message("GLM: x86 64 bits with AVX2 instruction set build target")
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# else
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# pragma message("GLM: x86 32 bits with AVX2 instruction set build target")
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# endif
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# elif(GLM_ARCH == GLM_ARCH_AVX)
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# elif GLM_ARCH & GLM_ARCH_AVX_BIT
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# if GLM_MODEL == GLM_MODEL_64
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# pragma message("GLM: x86 64 bits with AVX instruction set build target")
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# else
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# pragma message("GLM: x86 32 bits with AVX instruction set build target")
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# endif
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# elif(GLM_ARCH == GLM_ARCH_SSE42)
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# elif GLM_ARCH & GLM_ARCH_SSE42_BIT
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# if GLM_MODEL == GLM_MODEL_64
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# pragma message("GLM: x86 64 bits with SSE4.2 instruction set build target")
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# else
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# pragma message("GLM: x86 32 bits with SSE4.2 instruction set build target")
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# endif
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# elif(GLM_ARCH == GLM_ARCH_SSE41)
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# elif GLM_ARCH & GLM_ARCH_SSE41_BIT
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# if GLM_MODEL == GLM_MODEL_64
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# pragma message("GLM: x86 64 bits with SSE4.1 instruction set build target")
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# else
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# pragma message("GLM: x86 32 bits with SSE4.1 instruction set build target")
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# endif
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# elif(GLM_ARCH == GLM_ARCH_SSSE3)
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# elif GLM_ARCH & GLM_ARCH_SSSE3_BIT
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# if GLM_MODEL == GLM_MODEL_64
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# pragma message("GLM: x86 64 bits with SSSE3 instruction set build target")
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# else
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# pragma message("GLM: x86 32 bits with SSSE3 instruction set build target")
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# endif
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# elif(GLM_ARCH == GLM_ARCH_SSE3)
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# elif GLM_ARCH & GLM_ARCH_SSE3_BIT
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# if GLM_MODEL == GLM_MODEL_64
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# pragma message("GLM: x86 64 bits with SSE3 instruction set build target")
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# else
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# pragma message("GLM: x86 32 bits with SSE3 instruction set build target")
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# endif
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# elif(GLM_ARCH == GLM_ARCH_SSE2)
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# elif GLM_ARCH & GLM_ARCH_SSE2_BIT
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# if GLM_MODEL == GLM_MODEL_64
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# pragma message("GLM: x86 64 bits with SSE2 instruction set build target")
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# else
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# pragma message("GLM: x86 32 bits with SSE2 instruction set build target")
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# endif
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# elif(GLM_ARCH == GLM_ARCH_ARM)
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# elif GLM_ARCH & GLM_ARCH_X86_BIT
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# if GLM_MODEL == GLM_MODEL_64
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# pragma message("GLM: ARM 64 bits build target")
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# pragma message("GLM: x86 64 bits build target")
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# else
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# pragma message("GLM: ARM 32 bits build target")
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# pragma message("GLM: x86 32 bits build target")
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# endif
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# elif(GLM_ARCH == GLM_ARCH_NEON)
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# elif GLM_ARCH & GLM_ARCH_NEON_BIT
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# if GLM_MODEL == GLM_MODEL_64
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# pragma message("GLM: ARM 64 bits with Neon instruction set build target")
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# else
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# pragma message("GLM: ARM 32 bits with Neon instruction set build target")
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# endif
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# elif(GLM_ARCH == GLM_ARCH_MIPS)
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# elif GLM_ARCH & GLM_ARCH_ARM_BIT
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# if GLM_MODEL == GLM_MODEL_64
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# pragma message("GLM: ARM 64 bits build target")
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# else
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# pragma message("GLM: ARM 32 bits build target")
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# endif
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# elif GLM_ARCH & GLM_ARCH_MIPS_BIT
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# if GLM_MODEL == GLM_MODEL_64
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# pragma message("GLM: MIPS 64 bits build target")
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# else
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# pragma message("GLM: MIPS 32 bits build target")
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# endif
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# elif(GLM_ARCH == GLM_ARCH_PPC)
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# elif GLM_ARCH & GLM_ARCH_PPC_BIT
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# if GLM_MODEL == GLM_MODEL_64
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# pragma message("GLM: PowerPC 64 bits build target")
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# else
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@ -222,23 +222,25 @@
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// User defines: GLM_FORCE_PURE GLM_FORCE_SSE2 GLM_FORCE_SSE3 GLM_FORCE_AVX GLM_FORCE_AVX2 GLM_FORCE_AVX2
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#define GLM_ARCH_SIMD_BIT (0x00001000)
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#define GLM_ARCH_MIPS_BIT (0x10000000)
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#define GLM_ARCH_PPC_BIT (0x20000000)
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#define GLM_ARCH_ARM_BIT (0x40000000)
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#define GLM_ARCH_NEON_BIT (0x00000001 | GLM_ARCH_SIMD_BIT)
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#define GLM_ARCH_X86_BIT (0x80000000)
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#define GLM_ARCH_SSE2_BIT (0x80000002 | GLM_ARCH_SIMD_BIT)
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#define GLM_ARCH_SSE3_BIT (0x80000004 | GLM_ARCH_SIMD_BIT)
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#define GLM_ARCH_SSSE3_BIT (0x80000008 | GLM_ARCH_SIMD_BIT)
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#define GLM_ARCH_SSE41_BIT (0x80000010 | GLM_ARCH_SIMD_BIT)
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#define GLM_ARCH_SSE42_BIT (0x80000020 | GLM_ARCH_SIMD_BIT)
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#define GLM_ARCH_AVX_BIT (0x80000040 | GLM_ARCH_SIMD_BIT)
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#define GLM_ARCH_AVX2_BIT (0x80000080 | GLM_ARCH_SIMD_BIT)
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#define GLM_ARCH_SIMD_BIT (0x00001000)
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#define GLM_ARCH_NEON_BIT (0x00000001)
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#define GLM_ARCH_SSE2_BIT (0x00000002)
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#define GLM_ARCH_SSE3_BIT (0x00000004)
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#define GLM_ARCH_SSSE3_BIT (0x00000008)
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#define GLM_ARCH_SSE41_BIT (0x00000010)
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#define GLM_ARCH_SSE42_BIT (0x00000020)
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#define GLM_ARCH_AVX_BIT (0x00000040)
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#define GLM_ARCH_AVX2_BIT (0x00000080)
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#define GLM_ARCH_UNKNOWED (0)
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#define GLM_ARCH_X86 (GLM_ARCH_X86_BIT)
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#define GLM_ARCH_SSE2 (GLM_ARCH_SSE2_BIT | GLM_ARCH_X86)
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#define GLM_ARCH_SSE2 (GLM_ARCH_SSE2_BIT | GLM_ARCH_SIMD_BIT | GLM_ARCH_X86)
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#define GLM_ARCH_SSE3 (GLM_ARCH_SSE3_BIT | GLM_ARCH_SSE2)
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#define GLM_ARCH_SSSE3 (GLM_ARCH_SSSE3_BIT | GLM_ARCH_SSE3)
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#define GLM_ARCH_SSE41 (GLM_ARCH_SSE41_BIT | GLM_ARCH_SSSE3)
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@ -246,7 +248,7 @@
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#define GLM_ARCH_AVX (GLM_ARCH_AVX_BIT | GLM_ARCH_SSE42)
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#define GLM_ARCH_AVX2 (GLM_ARCH_AVX2_BIT | GLM_ARCH_AVX)
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#define GLM_ARCH_ARM (GLM_ARCH_ARM_BIT)
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#define GLM_ARCH_NEON (GLM_ARCH_NEON_BIT | GLM_ARCH_ARM)
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#define GLM_ARCH_NEON (GLM_ARCH_NEON_BIT | GLM_ARCH_SIMD_BIT | GLM_ARCH_ARM)
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#define GLM_ARCH_MIPS (GLM_ARCH_MIPS_BIT)
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#define GLM_ARCH_PPC (GLM_ARCH_PPC_BIT)
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