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Concept prof for vec4 SIMD specialication
This commit is contained in:
Christophe Riccio
parent
48fcbd6ec4
commit
d9f5e07641
@ -48,7 +48,7 @@ GLM_FUNC_QUALIFIER __m128 sse_dst_ps(__m128 p0, __m128 p1)
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//dot
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GLM_FUNC_QUALIFIER __m128 sse_dot_ps(__m128 v1, __m128 v2)
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{
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# if((GLM_ARCH & GLM_ARCH_SSE4) == GLM_ARCH_SSE4)
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# if(GLM_ARCH & GLM_ARCH_AVX)
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return _mm_dp_ps(v1, v2, 0xff);
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# else
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__m128 mul0 = _mm_mul_ps(v1, v2);
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@ -520,6 +520,13 @@
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((GLM_LANG & GLM_LANG_CXX0X_FLAG) && (GLM_COMPILER & GLM_COMPILER_GCC) && (GLM_COMPILER >= GLM_COMPILER_GCC44)) || \
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__has_feature(cxx_generalized_initializers))
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// N2544 Unrestricted unions
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#define GLM_HAS_UNRESTRICTED_UNIONS ( \
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(GLM_LANG & GLM_LANG_CXX11_FLAG) || \
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(GLM_LANG & GLM_LANG_CXXMS_FLAG) || \
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((GLM_LANG & GLM_LANG_CXX0X_FLAG) && (GLM_COMPILER & GLM_COMPILER_GCC) && (GLM_COMPILER >= GLM_COMPILER_GCC46)) || \
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__has_feature(cxx_unrestricted_unions))
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// OpenMP
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#ifdef _OPENMP
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# if(GLM_COMPILER & GLM_COMPILER_GCC)
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@ -545,14 +552,13 @@
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/////////////////
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// Platform
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// User defines: GLM_FORCE_PURE GLM_FORCE_SSE2 GLM_FORCE_AVX
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// User defines: GLM_FORCE_PURE GLM_FORCE_SSE2 GLM_FORCE_SSE3 GLM_FORCE_AVX GLM_FORCE_AVX2
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#define GLM_ARCH_PURE 0x0000
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#define GLM_ARCH_SSE2 0x0001
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#define GLM_ARCH_SSE3 0x0002// | GLM_ARCH_SSE2
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#define GLM_ARCH_SSE4 0x0004// | GLM_ARCH_SSE3 | GLM_ARCH_SSE2
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#define GLM_ARCH_AVX 0x0008// | GLM_ARCH_SSE4 | GLM_ARCH_SSE3 | GLM_ARCH_SSE2
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#define GLM_ARCH_AVX2 0x0010// | GLM_ARCH_AVX | GLM_ARCH_SSE4 | GLM_ARCH_SSE3 | GLM_ARCH_SSE2
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#define GLM_ARCH_AVX 0x0004// | GLM_ARCH_SSE3 | GLM_ARCH_SSE2
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#define GLM_ARCH_AVX2 0x0008// | GLM_ARCH_AVX | GLM_ARCH_SSE3 | GLM_ARCH_SSE2
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#if(defined(GLM_FORCE_PURE))
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# define GLM_ARCH GLM_ARCH_PURE
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@ -560,12 +566,22 @@
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# define GLM_ARCH (GLM_ARCH_AVX2 | GLM_ARCH_AVX | GLM_ARCH_SSE3 | GLM_ARCH_SSE2)
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#elif(defined(GLM_FORCE_AVX))
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# define GLM_ARCH (GLM_ARCH_AVX | GLM_ARCH_SSE3 | GLM_ARCH_SSE2)
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#elif(defined(GLM_FORCE_SSE4))
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# define GLM_ARCH (GLM_ARCH_SSE4 | GLM_ARCH_SSE3 | GLM_ARCH_SSE2)
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#elif(defined(GLM_FORCE_SSE3))
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# define GLM_ARCH (GLM_ARCH_SSE3 | GLM_ARCH_SSE2)
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#elif(defined(GLM_FORCE_SSE2))
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# define GLM_ARCH (GLM_ARCH_SSE2)
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#elif((GLM_COMPILER & GLM_COMPILER_CLANG) || (GLM_COMPILER & GLM_COMPILER_GCC))
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# if(__AVX2__)
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# define GLM_ARCH (GLM_ARCH_AVX2 | GLM_ARCH_AVX | GLM_ARCH_SSE3 | GLM_ARCH_SSE2)
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# elif(__AVX__)
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# define GLM_ARCH (GLM_ARCH_AVX | GLM_ARCH_SSE3 | GLM_ARCH_SSE2)
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# elif(__SSE3__)
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# define GLM_ARCH (GLM_ARCH_SSE3 | GLM_ARCH_SSE2)
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# elif(__SSE2__)
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# define GLM_ARCH (GLM_ARCH_SSE2)
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# else
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# define GLM_ARCH GLM_ARCH_PURE
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# endif
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#elif((GLM_COMPILER & GLM_COMPILER_VC) && (defined(_M_IX86) || defined(_M_X64)))
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# if(GLM_PLATFORM == GLM_PLATFORM_WINCE)
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# define GLM_ARCH GLM_ARCH_PURE
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@ -596,15 +612,6 @@
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# else
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# define GLM_ARCH GLM_ARCH_PURE
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# endif
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#elif((GLM_PLATFORM & GLM_PLATFORM_APPLE) && (GLM_COMPILER & GLM_COMPILER_GCC))
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# define GLM_ARCH GLM_ARCH_PURE
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#elif(((GLM_COMPILER & GLM_COMPILER_GCC) && (defined(__i386__) || defined(__x86_64__))) || (GLM_COMPILER & GLM_COMPILER_LLVM_GCC))
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# define GLM_ARCH (GLM_ARCH_PURE \
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| (defined(__AVX2__) ? GLM_ARCH_AVX2 : 0) \
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| (defined(__AVX__) ? GLM_ARCH_AVX : 0) \
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| (defined(__SSE4__) ? GLM_ARCH_SSE4 : 0) \
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| (defined(__SSE3__) ? GLM_ARCH_SSE3 : 0) \
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| (defined(__SSE2__) ? GLM_ARCH_SSE2 : 0))
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#else
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# define GLM_ARCH GLM_ARCH_PURE
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#endif
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@ -616,7 +623,6 @@
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# include <intrin.h>
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#endif
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//#if(GLM_ARCH != GLM_ARCH_PURE)
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#if(GLM_ARCH & GLM_ARCH_AVX2)
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# include <immintrin.h>
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#endif//GLM_ARCH
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@ -639,22 +645,19 @@
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inline __m128 _mm_castsi128_ps(__m128i PI) { union { __m128 ps; __m128i pi; } c; c.pi = PI; return c.ps; }
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# endif
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#endif//GLM_ARCH
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//#endif//(GLM_ARCH != GLM_ARCH_PURE)
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#if(defined(GLM_MESSAGES) && !defined(GLM_MESSAGE_ARCH_DISPLAYED))
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# define GLM_MESSAGE_ARCH_DISPLAYED
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# if(GLM_ARCH == GLM_ARCH_PURE)
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# pragma message("GLM: Platform independent")
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# elif(GLM_ARCH & GLM_ARCH_SSE2)
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# pragma message("GLM: SSE2 instruction set")
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# elif(GLM_ARCH & GLM_ARCH_SSE3)
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# pragma message("GLM: SSE3 instruction set")
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# elif(GLM_ARCH & GLM_ARCH_SSE4)
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# pragma message("GLM: SSE4 instruction set")
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# elif(GLM_ARCH & GLM_ARCH_AVX)
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# pragma message("GLM: AVX instruction set")
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# elif(GLM_ARCH & GLM_ARCH_AVX2)
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# pragma message("GLM: AVX2 instruction set")
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# elif(GLM_ARCH & GLM_ARCH_AVX)
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# pragma message("GLM: AVX instruction set")
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# elif(GLM_ARCH & GLM_ARCH_SSE3)
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# pragma message("GLM: SSE3 instruction set")
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# elif(GLM_ARCH & GLM_ARCH_SSE2)
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# pragma message("GLM: SSE2 instruction set")
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# endif//GLM_ARCH
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# pragma message("GLM: #define GLM_FORCE_PURE to avoid using platform specific instruction sets")
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#endif//GLM_MESSAGE
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@ -47,6 +47,28 @@
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namespace glm{
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namespace detail
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{
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template <typename T>
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struct simd
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{
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typedef T type[4];
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};
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# if(GLM_ARCH & GLM_ARCH_SSE2)
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template <>
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struct simd<float>
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{
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typedef __m128 type;
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};
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# endif
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# if(GLM_ARCH & GLM_ARCH_AVX)
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template <>
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struct simd<double>
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{
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typedef __m256d type;
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};
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# endif
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template <typename T, precision P>
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struct tvec4
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{
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@ -86,11 +108,25 @@ namespace detail
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_GLM_SWIZZLE4_4_MEMBERS(T, P, tvec4, s, t, p, q)
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};
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# else
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union { T x, r, s; };
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union { T y, g, t; };
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union { T z, b, p; };
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union { T w, a, q; };
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# if(GLM_HAS_UNRESTRICTED_UNIONS)
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union
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{
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typename simd<T>::type data;
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struct
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{
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union { T x, r, s; };
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union { T y, g, t; };
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union { T z, b, p; };
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union { T w, a, q; };
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};
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};
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# else
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union { T x, r, s; };
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union { T y, g, t; };
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union { T z, b, p; };
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union { T w, a, q; };
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# endif
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# ifdef GLM_SWIZZLE
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GLM_SWIZZLE_GEN_VEC_FROM_VEC4(T, P, detail::tvec4, detail::tvec2, detail::tvec3, detail::tvec4)
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# endif
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@ -13,8 +13,30 @@
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#if(GLM_ARCH != GLM_ARCH_PURE)
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struct value
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{
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value(float x, float y, float z, float w) :
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x(x), y(y), z(z), w(w)
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{}
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union
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{
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__m128 data;
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struct
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{
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union { float x, r, s; };
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union { float y, g, t; };
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union { float z, b, p; };
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union { float w, a, q; };
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};
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};
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};
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int main()
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{
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value Value(1.0, 0.5, 0.0, 0.7);
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glm::simdVec4 A1(0.0f, 0.1f, 0.2f, 0.3f);
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glm::simdVec4 B1(0.4f, 0.5f, 0.6f, 0.7f);
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glm::simdVec4 C1 = A1 + B1;
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