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Author SHA1 Message Date
Christophe Riccio
29fa0f1607 Deprecated GLM_GTX_simd_mat4, GLM_GTX_simd_vec4 and GLM_GTX_simd_quat 2016-05-28 19:34:46 +02:00
Christophe Riccio
7fe2f5fe65 Renamed instruction set flags 2016-05-28 19:26:59 +02:00
Christophe Riccio
d33e3df02a Fixed SIMD code path selection 2016-05-28 18:24:39 +02:00
Christophe Riccio
fdb985a0eb Fixed SIMD code path selection 2016-05-28 18:15:35 +02:00
Christophe Riccio
d0e746e292 Fixed SIMD code path selection 2016-05-28 17:55:24 +02:00
Christophe Riccio
9f00ba86cb Fixed SIMD code path selection 2016-05-28 17:54:37 +02:00
Christophe Riccio
ab159770b3 mad optimizations, fixed build 2016-05-28 17:12:48 +02:00
Christophe Riccio
fdec412ff7 Added FMA SIMD optimization 2016-05-28 12:31:43 +02:00
Christophe Riccio
71e6b537cc Clarify support for SSSE3, SSE4.1 and SSE4.2 2016-05-28 11:52:41 +02:00
Christophe Riccio
0ee3a79bfd Uniformalize low level SIMD API 2016-05-28 11:21:04 +02:00
Christophe Riccio
79894a58cc Added NaN and Inf SIMD optimization 2016-05-28 03:09:22 +02:00
Christophe Riccio
1381a95938 Optimized dot SIMD implementation with SSE3 2016-05-28 02:46:06 +02:00
Christophe Riccio
9c6de96669 Specialized SIMD == and != operators 2016-05-28 02:16:56 +02:00
Christophe Riccio
a9fefc7300 Added vec4 SIMD contructor specialization 2016-05-28 01:33:29 +02:00
Christophe Riccio
c5f48da319 Fixed build with compiler that doesn't support GLM_HAS_UNRESTRICTED_UNIONS 2016-05-28 00:10:18 +02:00
Christophe Riccio
ae6082db5e Added AVX2 bitwise optimization 2016-05-28 00:00:33 +02:00
Christophe Riccio
f577611328 Added bitwise inverse SIMD optimization. Factorized bitwise optimization code 2016-05-27 23:03:38 +02:00
Christophe Riccio
4797ea9540 Added specialized SSE2 and AVX bool mix 2016-05-26 02:47:43 +02:00
Christophe Riccio
740e6d6e56 Merged 0.9.7 branch 2016-05-24 23:51:02 +02:00
Christophe Riccio
767aa16e5b Updated readme for GLM 0.9.7 release 2016-05-24 22:30:51 +02:00
Christophe Riccio
72c741d8ea Fixed sign with signed integer function on non-x86 architecture 2016-05-24 13:29:18 +02:00
Christophe Riccio
1208eb63f7 Added NEON, MIPS and PowerPC detection 2016-05-23 23:35:34 +02:00
Christophe Riccio
316460408a Simplify and more consistency for files headers 2016-05-23 22:55:49 +02:00
Christophe Riccio
62d5e0ce45 Fixed build 2016-05-23 21:59:25 +02:00
Christophe Riccio
8b9d205178 Fixed build 2016-05-23 21:57:26 +02:00
Christophe Riccio
3f74efa2e0 Merge simd branch 2016-05-23 21:52:59 +02:00
Christophe Riccio
b87ead8304 Use unary bit operators for binary implementation 2016-05-23 21:47:35 +02:00
Christophe Riccio
3081b44ed2 Use unary bit operators for binary implementation 2016-05-23 21:45:08 +02:00
Christophe Riccio
d871d753dc Use unary bit operators for binary implementation 2016-05-23 21:39:33 +02:00
Christophe Riccio
5e60c54004 Use unary % operator for binary implementation 2016-05-23 21:24:59 +02:00
Christophe Riccio
eab004bfe5 vec4 add, sub, mul and div binary operators use unary operators implementation 2016-05-23 21:20:04 +02:00
Christophe Riccio
276505f409 add, sub, mul and div vec4 for specialization 2016-05-23 21:13:57 +02:00
Christophe Riccio
b5ebda89d7 Updated readme 2016-05-23 19:30:42 +02:00
Christophe Riccio
9aabeb4075 Merge branch '0.9.7' 2016-05-23 19:29:53 +02:00
Christophe Riccio
2a4c7e77d6 Added Visual C++ Clang toolset detection 2016-05-23 19:29:36 +02:00
Christophe Riccio
74367aca3c Added Visual C++ Clang toolset detection 2016-05-23 19:25:07 +02:00
Christophe Riccio
c0fc71803c Integer SSE code generation 2016-05-23 01:54:55 +02:00
Christophe Riccio
ff74b87b48 Generate SSE instructions for sub, mul and div including lowp div 2016-05-23 00:34:59 +02:00
Christophe Riccio
0e780a5efd - Use Cuda built-in function for abs function implementation with Cuda compiler 2016-05-22 18:04:32 +02:00
Christophe Riccio
cc9916b2c6 Fixed build, missing reference to inverse function 2016-05-22 17:28:18 +02:00
Christophe Riccio
6cf7389c8c Removed the glm_dummy CMake target if glm_shared or glm_static are enabled 2016-05-22 17:20:56 +02:00
Christophe Riccio
757fe39587 Removed simd precision qualifier. All precision qualifiers may generate SIMD instructions, precision may affect the generated instructions accordingly 2016-05-22 17:12:32 +02:00
Christophe Riccio
805939686c Visual C++ genenrate ASM code for GLM tests 2016-05-22 13:16:55 +02:00
Christophe Riccio
93a2f03649 Merge branch '0.9.7' 2016-05-18 22:53:00 +02:00
Christophe Riccio
dcffcbdc97 Fixed GLM_FORCE_INLINE with binary vec4 operators 2016-05-18 22:52:47 +02:00
Christophe Riccio
792151573c Fixed to_string when used with GLM_FORCE_INLINE #506 2016-05-18 22:46:58 +02:00
Christophe Riccio
fd06877778 Too big bug with GCC 4.6 constexpr, haven't tried 4.7, let's see how 4.8 does 2016-05-05 21:06:27 +02:00
Christophe Riccio
60a5f4aea9 Too big bug with GCC 4.6 constexpr, haven't tried 4.7, let's see how 4.8 does 2016-05-05 20:57:37 +02:00
Christophe Riccio
a6047251be Fixed constexpr with SIMD interaction 2016-05-05 20:43:09 +02:00
Christophe Riccio
92a46735d6 Workaround GCC compiler bug with constexpr support 2016-05-05 20:05:31 +02:00