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Precise_ip should be shared in each pair of counters.
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parent
fef507dfa2
commit
089eda0be9
@ -689,8 +689,9 @@ enum TraceEventId
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EventBranchMiss
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};
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static void ProbePreciseIp( perf_event_attr& pe )
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static void ProbePreciseIp( perf_event_attr& pe, unsigned long long config0, unsigned long long config1 )
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{
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pe.config = config1;
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pe.precise_ip = 3;
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while( pe.precise_ip != 0 )
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{
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@ -702,6 +703,17 @@ static void ProbePreciseIp( perf_event_attr& pe )
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}
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pe.precise_ip--;
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}
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pe.config = config0;
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while( pe.precise_ip != 0 )
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{
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const int fd = perf_event_open( &pe, -1, 0, -1, PERF_FLAG_FD_CLOEXEC );
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if( fd != -1 )
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{
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close( fd );
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break;
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}
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pe.precise_ip--;
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}
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TracyDebug( " Probed precise_ip: %i\n", pe.precise_ip );
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}
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@ -769,11 +781,10 @@ static void SetupSampling( int64_t& samplingPeriod )
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s_numBuffers++;
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}
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// CPU cycles
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// CPU cycles + instructions retired
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pe = {};
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pe.type = PERF_TYPE_HARDWARE;
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pe.size = sizeof( perf_event_attr );
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pe.config = PERF_COUNT_HW_CPU_CYCLES;
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pe.sample_freq = 5*1000*1000;
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pe.sample_type = PERF_SAMPLE_IP | PERF_SAMPLE_TID;
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pe.disabled = 1;
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@ -781,8 +792,8 @@ static void SetupSampling( int64_t& samplingPeriod )
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pe.exclude_idle = 1;
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if( !noRetirement )
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{
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TracyDebug( "Setup sampling CPU cycles\n" );
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ProbePreciseIp( pe );
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TracyDebug( "Setup sampling cycles + retirement\n" );
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ProbePreciseIp( pe, PERF_COUNT_HW_CPU_CYCLES, PERF_COUNT_HW_INSTRUCTIONS );
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for( int i=0; i<s_numCpus; i++ )
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{
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const int fd = perf_event_open( &pe, -1, i, -1, PERF_FLAG_FD_CLOEXEC );
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@ -793,14 +804,8 @@ static void SetupSampling( int64_t& samplingPeriod )
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TracyDebug( " Core %i ok\n", i );
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}
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}
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}
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// Instructions retired
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pe.config = PERF_COUNT_HW_INSTRUCTIONS;
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if( !noRetirement )
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{
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TracyDebug( "Setup sampling CPU instruction retirements\n" );
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ProbePreciseIp( pe );
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for( int i=0; i<s_numCpus; i++ )
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{
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const int fd = perf_event_open( &pe, -1, i, -1, PERF_FLAG_FD_CLOEXEC );
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@ -813,12 +818,11 @@ static void SetupSampling( int64_t& samplingPeriod )
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}
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}
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// cache reference
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pe.config = PERF_COUNT_HW_CACHE_REFERENCES;
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// cache reference + miss
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if( !noCache )
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{
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TracyDebug( "Setup sampling CPU cache references\n" );
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ProbePreciseIp( pe );
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TracyDebug( "Setup sampling CPU cache references + misses\n" );
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ProbePreciseIp( pe, PERF_COUNT_HW_CACHE_REFERENCES, PERF_COUNT_HW_CACHE_MISSES );
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for( int i=0; i<s_numCpus; i++ )
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{
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const int fd = perf_event_open( &pe, -1, i, -1, PERF_FLAG_FD_CLOEXEC );
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@ -829,14 +833,8 @@ static void SetupSampling( int64_t& samplingPeriod )
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TracyDebug( " Core %i ok\n", i );
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}
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}
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}
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// cache miss
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pe.config = PERF_COUNT_HW_CACHE_MISSES;
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if( !noCache )
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{
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TracyDebug( "Setup sampling CPU cache misses\n" );
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ProbePreciseIp( pe );
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for( int i=0; i<s_numCpus; i++ )
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{
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const int fd = perf_event_open( &pe, -1, i, -1, PERF_FLAG_FD_CLOEXEC );
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@ -849,12 +847,11 @@ static void SetupSampling( int64_t& samplingPeriod )
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}
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}
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// branch retired
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pe.config = PERF_COUNT_HW_BRANCH_INSTRUCTIONS;
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// branch retired + miss
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if( !noBranch )
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{
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TracyDebug( "Setup sampling CPU branch retirements\n" );
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ProbePreciseIp( pe );
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TracyDebug( "Setup sampling CPU branch retirements + misses\n" );
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ProbePreciseIp( pe, PERF_COUNT_HW_BRANCH_INSTRUCTIONS, PERF_COUNT_HW_BRANCH_MISSES );
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for( int i=0; i<s_numCpus; i++ )
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{
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const int fd = perf_event_open( &pe, -1, i, -1, PERF_FLAG_FD_CLOEXEC );
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@ -865,14 +862,8 @@ static void SetupSampling( int64_t& samplingPeriod )
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TracyDebug( " Core %i ok\n", i );
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}
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}
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}
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// branch miss
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pe.config = PERF_COUNT_HW_BRANCH_MISSES;
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if( !noBranch )
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{
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TracyDebug( "Setup sampling CPU branch misses\n" );
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ProbePreciseIp( pe );
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for( int i=0; i<s_numCpus; i++ )
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{
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const int fd = perf_event_open( &pe, -1, i, -1, PERF_FLAG_FD_CLOEXEC );
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