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Don't require time to be available for samples.
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parent
051b1ba8f5
commit
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@ -928,20 +928,6 @@ static void SetupSampling( int64_t& samplingPeriod )
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InitRpmalloc();
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sched_param sp = { 5 };
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pthread_setschedparam( pthread_self(), SCHED_FIFO, &sp );
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#if defined TRACY_HW_TIMER && ( defined __i386 || defined _M_IX86 || defined __x86_64__ || defined _M_X64 )
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for( int i=0; i<s_numBuffers; i++ )
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{
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if( s_ring[i].GetId() == EventCallstack && !s_ring[i].CheckTscCaps() )
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{
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for( int j=0; j<s_numBuffers; j++ ) s_ring[j].~RingBuffer<RingBufSize>();
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tracy_free_fast( s_ring );
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const char* err = "Tracy Profiler: sampling is disabled due to non-native scheduler clock. Are you running under a VM?";
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TracyDebug( err );
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Profiler::MessageAppInfo( err, strlen( err ) );
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return;
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}
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}
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#endif
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for( int i=0; i<s_numBuffers; i++ ) s_ring[i].Enable();
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for(;;)
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{
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@ -990,48 +976,45 @@ static void SetupSampling( int64_t& samplingPeriod )
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{
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#if defined TRACY_HW_TIMER && ( defined __i386 || defined _M_IX86 || defined __x86_64__ || defined _M_X64 )
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t0 = ring.ConvertTimeToTsc( t0 );
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if( t0 != 0 )
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#endif
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{
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auto trace = (uint64_t*)tracy_malloc_fast( ( 1 + cnt ) * sizeof( uint64_t ) );
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ring.Read( trace+1, offset, sizeof( uint64_t ) * cnt );
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auto trace = (uint64_t*)tracy_malloc_fast( ( 1 + cnt ) * sizeof( uint64_t ) );
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ring.Read( trace+1, offset, sizeof( uint64_t ) * cnt );
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#if defined __x86_64__ || defined _M_X64
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// remove non-canonical pointers
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do
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{
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const auto test = (int64_t)trace[cnt];
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const auto m1 = test >> 63;
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const auto m2 = test >> 47;
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if( m1 == m2 ) break;
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}
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while( --cnt > 0 );
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for( uint64_t j=1; j<cnt; j++ )
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{
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const auto test = (int64_t)trace[j];
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const auto m1 = test >> 63;
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const auto m2 = test >> 47;
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if( m1 != m2 ) trace[j] = 0;
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}
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// remove non-canonical pointers
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do
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{
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const auto test = (int64_t)trace[cnt];
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const auto m1 = test >> 63;
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const auto m2 = test >> 47;
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if( m1 == m2 ) break;
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}
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while( --cnt > 0 );
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for( uint64_t j=1; j<cnt; j++ )
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{
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const auto test = (int64_t)trace[j];
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const auto m1 = test >> 63;
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const auto m2 = test >> 47;
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if( m1 != m2 ) trace[j] = 0;
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}
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#endif
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for( uint64_t j=1; j<=cnt; j++ )
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for( uint64_t j=1; j<=cnt; j++ )
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{
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if( trace[j] >= (uint64_t)-4095 ) // PERF_CONTEXT_MAX
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{
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if( trace[j] >= (uint64_t)-4095 ) // PERF_CONTEXT_MAX
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{
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memmove( trace+j, trace+j+1, sizeof( uint64_t ) * ( cnt - j ) );
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cnt--;
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}
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memmove( trace+j, trace+j+1, sizeof( uint64_t ) * ( cnt - j ) );
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cnt--;
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}
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memcpy( trace, &cnt, sizeof( uint64_t ) );
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TracyLfqPrepare( QueueType::CallstackSample );
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MemWrite( &item->callstackSampleFat.time, t0 );
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MemWrite( &item->callstackSampleFat.thread, tid );
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MemWrite( &item->callstackSampleFat.ptr, (uint64_t)trace );
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TracyLfqCommit;
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}
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memcpy( trace, &cnt, sizeof( uint64_t ) );
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TracyLfqPrepare( QueueType::CallstackSample );
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MemWrite( &item->callstackSampleFat.time, t0 );
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MemWrite( &item->callstackSampleFat.thread, tid );
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MemWrite( &item->callstackSampleFat.ptr, (uint64_t)trace );
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TracyLfqCommit;
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}
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}
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else
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@ -1047,40 +1030,37 @@ static void SetupSampling( int64_t& samplingPeriod )
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#if defined TRACY_HW_TIMER && ( defined __i386 || defined _M_IX86 || defined __x86_64__ || defined _M_X64 )
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t0 = ring.ConvertTimeToTsc( t0 );
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if( t0 != 0 )
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#endif
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QueueType type;
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switch( id )
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{
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QueueType type;
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switch( id )
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{
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case EventCpuCycles:
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type = QueueType::HwSampleCpuCycle;
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break;
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case EventInstructionsRetired:
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type = QueueType::HwSampleInstructionRetired;
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break;
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case EventCacheReference:
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type = QueueType::HwSampleCacheReference;
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break;
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case EventCacheMiss:
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type = QueueType::HwSampleCacheMiss;
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break;
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case EventBranchRetired:
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type = QueueType::HwSampleBranchRetired;
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break;
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case EventBranchMiss:
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type = QueueType::HwSampleBranchMiss;
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break;
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default:
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assert( false );
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break;
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}
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TracyLfqPrepare( type );
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MemWrite( &item->hwSample.ip, ip );
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MemWrite( &item->hwSample.time, t0 );
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TracyLfqCommit;
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case EventCpuCycles:
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type = QueueType::HwSampleCpuCycle;
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break;
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case EventInstructionsRetired:
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type = QueueType::HwSampleInstructionRetired;
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break;
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case EventCacheReference:
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type = QueueType::HwSampleCacheReference;
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break;
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case EventCacheMiss:
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type = QueueType::HwSampleCacheMiss;
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break;
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case EventBranchRetired:
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type = QueueType::HwSampleBranchRetired;
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break;
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case EventBranchMiss:
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type = QueueType::HwSampleBranchMiss;
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break;
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default:
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assert( false );
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break;
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}
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TracyLfqPrepare( type );
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MemWrite( &item->hwSample.ip, ip );
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MemWrite( &item->hwSample.time, t0 );
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TracyLfqCommit;
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}
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}
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pos += hdr.size;
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