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Store list of read and write registers for each asm instruction.
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parent
38116b88a5
commit
8014fce6e1
@ -593,6 +593,35 @@ bool SourceView::Disassemble( uint64_t symAddr, const Worker& worker )
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}
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}
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}
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}
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m_asm.emplace_back( AsmLine { op.address, jumpAddr, op.mnemonic, op.op_str, (uint8_t)op.size, leaData, std::move( params ) } );
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m_asm.emplace_back( AsmLine { op.address, jumpAddr, op.mnemonic, op.op_str, (uint8_t)op.size, leaData, std::move( params ) } );
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auto& entry = m_asm.back();
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cs_regs read, write;
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uint8_t rcnt, wcnt;
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cs_regs_access( handle, &op, read, &rcnt, write, &wcnt );
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int idx;
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switch( m_cpuArch )
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{
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case CpuArchX86:
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case CpuArchX64:
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assert( rcnt < sizeof( entry.readX86 ) );
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assert( wcnt < sizeof( entry.writeX86 ) );
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idx = 0;
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for( int i=0; i<rcnt; i++ )
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{
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if( s_regMapX86[read[i]] != RegsX86::invalid ) entry.readX86[idx++] = s_regMapX86[read[i]];
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entry.readX86[idx] = RegsX86::invalid;
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}
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idx = 0;
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for( int i=0; i<wcnt; i++ )
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{
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if( s_regMapX86[write[i]] != RegsX86::invalid ) entry.writeX86[idx++] = s_regMapX86[write[i]];
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entry.writeX86[idx] = RegsX86::invalid;
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}
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break;
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default:
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break;
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}
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const auto mLen = strlen( op.mnemonic );
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const auto mLen = strlen( op.mnemonic );
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if( mLen > mLenMax ) mLenMax = mLen;
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if( mLen > mLenMax ) mLenMax = mLen;
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if( op.size > bytesMax ) bytesMax = op.size;
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if( op.size > bytesMax ) bytesMax = op.size;
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@ -89,8 +89,18 @@ private:
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uint8_t len;
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uint8_t len;
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LeaData leaData;
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LeaData leaData;
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std::vector<AsmOpParams> params;
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std::vector<AsmOpParams> params;
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union
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{
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RegsX86 readX86[12];
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};
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union
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{
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RegsX86 writeX86[20];
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};
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};
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};
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enum { AsmLineSize = sizeof( AsmLine ) };
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struct JumpData
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struct JumpData
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{
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{
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uint64_t min;
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uint64_t min;
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