mirror of
https://github.com/wolfpld/tracy.git
synced 2024-11-10 02:31:48 +00:00
Process all data available in ring buffers.
This commit is contained in:
Bartosz Taudul
parent
5b7cd06840
commit
ca2130d56c
@ -59,12 +59,6 @@ public:
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ioctl( m_fd, PERF_EVENT_IOC_ENABLE, 0 );
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}
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bool HasData() const
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{
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const auto head = LoadHead();
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return head > m_tail;
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}
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void Read( void* dst, uint64_t offset, uint64_t cnt )
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{
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auto src = ( m_tail + offset ) % Size;
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@ -100,12 +94,17 @@ public:
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return ( quot << m_metadata->time_shift ) + ( rem << m_metadata->time_shift ) / m_metadata->time_mult;
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}
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private:
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uint64_t LoadHead() const
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{
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return std::atomic_load_explicit( (const volatile std::atomic<uint64_t>*)&m_metadata->data_head, std::memory_order_acquire );
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}
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uint64_t GetTail() const
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{
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return m_tail;
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}
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private:
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void StoreTail()
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{
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std::atomic_store_explicit( (volatile std::atomic<uint64_t>*)&m_metadata->data_tail, m_tail, std::memory_order_release );
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@ -933,142 +933,152 @@ static void SetupSampling( int64_t& samplingPeriod )
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for( int i=0; i<s_numBuffers; i++ )
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{
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if( !traceActive.load( std::memory_order_relaxed ) ) break;
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if( !s_ring[i].HasData() ) continue;
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const auto head = s_ring[i].LoadHead();
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const auto tail = s_ring[i].GetTail();
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if( head == tail ) continue;
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assert( head > tail );
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hadData = true;
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perf_event_header hdr;
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s_ring[i].Read( &hdr, 0, sizeof( perf_event_header ) );
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if( hdr.type == PERF_RECORD_SAMPLE )
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const auto end = head - tail;
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uint64_t pos = 0;
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while( pos < end )
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{
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auto offset = sizeof( perf_event_header );
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const auto id = s_ring[i].GetId();
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if( id == EventCallstack )
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perf_event_header hdr;
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s_ring[i].Read( &hdr, pos, sizeof( perf_event_header ) );
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if( hdr.type == PERF_RECORD_SAMPLE )
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{
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// Layout:
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// u32 pid, tid
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// u64 time
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// u64 cnt
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// u64 ip[cnt]
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uint32_t tid;
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uint64_t t0;
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uint64_t cnt;
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offset += sizeof( uint32_t );
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s_ring[i].Read( &tid, offset, sizeof( uint32_t ) );
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offset += sizeof( uint32_t );
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s_ring[i].Read( &t0, offset, sizeof( uint64_t ) );
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offset += sizeof( uint64_t );
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s_ring[i].Read( &cnt, offset, sizeof( uint64_t ) );
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offset += sizeof( uint64_t );
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if( cnt > 0 )
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auto offset = pos + sizeof( perf_event_header );
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const auto id = s_ring[i].GetId();
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if( id == EventCallstack )
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{
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// Layout:
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// u32 pid, tid
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// u64 time
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// u64 cnt
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// u64 ip[cnt]
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uint32_t tid;
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uint64_t t0;
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uint64_t cnt;
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offset += sizeof( uint32_t );
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s_ring[i].Read( &tid, offset, sizeof( uint32_t ) );
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offset += sizeof( uint32_t );
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s_ring[i].Read( &t0, offset, sizeof( uint64_t ) );
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offset += sizeof( uint64_t );
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s_ring[i].Read( &cnt, offset, sizeof( uint64_t ) );
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offset += sizeof( uint64_t );
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if( cnt > 0 )
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{
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#if defined TRACY_HW_TIMER && ( defined __i386 || defined _M_IX86 || defined __x86_64__ || defined _M_X64 )
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t0 = s_ring[i].ConvertTimeToTsc( t0 );
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if( t0 != 0 )
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#endif
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{
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auto trace = (uint64_t*)tracy_malloc_fast( ( 1 + cnt ) * sizeof( uint64_t ) );
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s_ring[i].Read( trace+1, offset, sizeof( uint64_t ) * cnt );
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#if defined __x86_64__ || defined _M_X64
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// remove non-canonical pointers
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do
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{
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const auto test = (int64_t)trace[cnt];
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const auto m1 = test >> 63;
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const auto m2 = test >> 47;
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if( m1 == m2 ) break;
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}
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while( --cnt > 0 );
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for( uint64_t j=1; j<cnt; j++ )
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{
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const auto test = (int64_t)trace[j];
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const auto m1 = test >> 63;
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const auto m2 = test >> 47;
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if( m1 != m2 ) trace[j] = 0;
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}
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#endif
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// skip kernel frames
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uint64_t j;
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for( j=0; j<cnt; j++ )
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{
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if( (int64_t)trace[j+1] >= 0 ) break;
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}
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if( j == cnt )
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{
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tracy_free_fast( trace );
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}
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else
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{
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if( j > 0 )
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{
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cnt -= j;
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memmove( trace+1, trace+1+j, sizeof( uint64_t ) * cnt );
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}
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memcpy( trace, &cnt, sizeof( uint64_t ) );
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TracyLfqPrepare( QueueType::CallstackSample );
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MemWrite( &item->callstackSampleFat.time, t0 );
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MemWrite( &item->callstackSampleFat.thread, (uint64_t)tid );
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MemWrite( &item->callstackSampleFat.ptr, (uint64_t)trace );
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TracyLfqCommit;
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}
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}
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}
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}
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else
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{
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// Layout:
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// u64 ip
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// u64 time
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uint64_t ip, t0;
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s_ring[i].Read( &ip, offset, sizeof( uint64_t ) );
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offset += sizeof( uint64_t );
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s_ring[i].Read( &t0, offset, sizeof( uint64_t ) );
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#if defined TRACY_HW_TIMER && ( defined __i386 || defined _M_IX86 || defined __x86_64__ || defined _M_X64 )
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t0 = s_ring[i].ConvertTimeToTsc( t0 );
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if( t0 != 0 )
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#endif
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{
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auto trace = (uint64_t*)tracy_malloc_fast( ( 1 + cnt ) * sizeof( uint64_t ) );
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s_ring[i].Read( trace+1, offset, sizeof( uint64_t ) * cnt );
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QueueType type;
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switch( id )
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{
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case EventCpuCycles:
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type = QueueType::HwSampleCpuCycle;
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break;
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case EventInstructionsRetired:
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type = QueueType::HwSampleInstructionRetired;
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break;
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case EventCacheReference:
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type = QueueType::HwSampleCacheReference;
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break;
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case EventCacheMiss:
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type = QueueType::HwSampleCacheMiss;
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break;
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case EventBranchRetired:
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type = QueueType::HwSampleBranchRetired;
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break;
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case EventBranchMiss:
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type = QueueType::HwSampleBranchMiss;
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break;
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default:
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assert( false );
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break;
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}
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#if defined __x86_64__ || defined _M_X64
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// remove non-canonical pointers
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do
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{
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const auto test = (int64_t)trace[cnt];
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const auto m1 = test >> 63;
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const auto m2 = test >> 47;
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if( m1 == m2 ) break;
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}
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while( --cnt > 0 );
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for( uint64_t j=1; j<cnt; j++ )
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{
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const auto test = (int64_t)trace[j];
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const auto m1 = test >> 63;
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const auto m2 = test >> 47;
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if( m1 != m2 ) trace[j] = 0;
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}
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#endif
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// skip kernel frames
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uint64_t j;
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for( j=0; j<cnt; j++ )
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{
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if( (int64_t)trace[j+1] >= 0 ) break;
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}
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if( j == cnt )
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{
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tracy_free_fast( trace );
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}
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else
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{
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if( j > 0 )
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{
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cnt -= j;
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memmove( trace+1, trace+1+j, sizeof( uint64_t ) * cnt );
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}
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memcpy( trace, &cnt, sizeof( uint64_t ) );
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TracyLfqPrepare( QueueType::CallstackSample );
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MemWrite( &item->callstackSampleFat.time, t0 );
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MemWrite( &item->callstackSampleFat.thread, (uint64_t)tid );
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MemWrite( &item->callstackSampleFat.ptr, (uint64_t)trace );
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TracyLfqCommit;
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}
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TracyLfqPrepare( type );
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MemWrite( &item->hwSample.ip, ip );
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MemWrite( &item->hwSample.time, t0 );
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TracyLfqCommit;
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}
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}
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}
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else
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{
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// Layout:
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// u64 ip
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// u64 time
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uint64_t ip, t0;
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s_ring[i].Read( &ip, offset, sizeof( uint64_t ) );
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offset += sizeof( uint64_t );
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s_ring[i].Read( &t0, offset, sizeof( uint64_t ) );
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#if defined TRACY_HW_TIMER && ( defined __i386 || defined _M_IX86 || defined __x86_64__ || defined _M_X64 )
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t0 = s_ring[i].ConvertTimeToTsc( t0 );
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if( t0 != 0 )
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#endif
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{
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QueueType type;
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switch( id )
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{
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case EventCpuCycles:
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type = QueueType::HwSampleCpuCycle;
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break;
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case EventInstructionsRetired:
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type = QueueType::HwSampleInstructionRetired;
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break;
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case EventCacheReference:
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type = QueueType::HwSampleCacheReference;
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break;
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case EventCacheMiss:
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type = QueueType::HwSampleCacheMiss;
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break;
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case EventBranchRetired:
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type = QueueType::HwSampleBranchRetired;
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break;
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case EventBranchMiss:
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type = QueueType::HwSampleBranchMiss;
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break;
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default:
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assert( false );
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break;
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}
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TracyLfqPrepare( type );
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MemWrite( &item->hwSample.ip, ip );
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MemWrite( &item->hwSample.time, t0 );
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TracyLfqCommit;
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}
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}
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pos += hdr.size;
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}
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s_ring[i].Advance( hdr.size );
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assert( pos == end );
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s_ring[i].Advance( end );
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}
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if( !traceActive.load( std::memory_order_relaxed) ) break;
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if( !hadData )
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