#once

#subruledef operand
{
    #{immediate: i5} => 0b000 @ immediate
    r{register: u5} => 0b001 @ register
    [r{register: u5}++] => 0b010 @ register
    [r{register: u5}--] => 0b011 @ register
    [r{register: u5}] => 0b100 @ register
    [r{register: u5} + {offset: u2}] => 0b1 @ offset @ register
}

#subruledef crflags
{
    .    => 0b0000
    .l   => 0b0010
    .le  => 0b0100
    .e   => 0b0110
    .ge  => 0b1000
    .g   => 0b1010
    .ne  => 0b1100
    .r   => 0b0001
    .rl  => 0b0011
    .rle => 0b0101
    .re  => 0b0111
    .rge => 0b1001
    .re  => 0b1011
    .rne => 0b1101
}

#ruledef
{
    CNST{flags: crflags} {dst: operand}, #{imm: i16}   => imm @ flags @ 0b0000 @ dst
    CMPR{flags: crflags} {dst: operand}, {a: operand} => 0x00 @ a @ flags @ 0b0001 @ dst
    BWNG{flags: crflags} {dst: operand}, {a: operand} => 0x01 @ a @ flags @ 0b0001 @ dst
    ARNG{flags: crflags} {dst: operand}, {a: operand} => 0x02 @ a @ flags @ 0b0001 @ dst
    LONG{flags: crflags} {dst: operand}, {a: operand} => 0x03 @ a @ flags @ 0b0001 @ dst
    BWOR{flags: crflags} {dst: operand}, {a: operand}, {b: operand} => b @ a @ flags @ 0b0010 @ dst
    BAND{flags: crflags} {dst: operand}, {a: operand}, {b: operand} => b @ a @ flags @ 0b0011 @ dst
    BXOR{flags: crflags} {dst: operand}, {a: operand}, {b: operand} => b @ a @ flags @ 0b0100 @ dst
    URSH{flags: crflags} {dst: operand}, {a: operand}, {b: operand} => b @ a @ flags @ 0b0101 @ dst
    SRSH{flags: crflags} {dst: operand}, {a: operand}, {b: operand} => b @ a @ flags @ 0b0110 @ dst
    ZLSH{flags: crflags} {dst: operand}, {a: operand}, {b: operand} => b @ a @ flags @ 0b0111 @ dst
    CLSH{flags: crflags} {dst: operand}, {a: operand}, {b: operand} => b @ a @ flags @ 0b1000 @ dst
    ADDI{flags: crflags} {dst: operand}, {a: operand}, {b: operand} => b @ a @ flags @ 0b1001 @ dst
    SUBT{flags: crflags} {dst: operand}, {a: operand}, {b: operand} => b @ a @ flags @ 0b1010 @ dst
    MULL{flags: crflags} {dst: operand}, {a: operand}, {b: operand} => b @ a @ flags @ 0b1011 @ dst
    MULS{flags: crflags} {dst: operand}, {a: operand}, {b: operand} => b @ a @ flags @ 0b1100 @ dst
    MULU{flags: crflags} {dst: operand}, {a: operand}, {b: operand} => b @ a @ flags @ 0b1101 @ dst
    DIVI{flags: crflags} {dst: operand}, {a: operand}, {b: operand} => b @ a @ flags @ 0b1110 @ dst
    MODU{flags: crflags} {dst: operand}, {a: operand}, {b: operand} => b @ a @ flags @ 0b1111 @ dst
}

#bankdef mem
{
    #bits 16
    #addr 0
    #size 0x10000
    #outp 0
}

#bank mem