`timescale 1ps / 1ps

module spi(
	input wire nreset,
	input wire clk,
	input wire [7:0] data,
	input wire send_data,
	output wire sck,
	output wire mosi,
	output wire next
);

logic [2:0] current_bit;

always_ff @(posedge clk) begin
	if (send_data == 1) begin
		current_bit <= current_bit + 1;
		if (current_bit == 3'b111) begin
			current_bit <= '0;
		end
	end

	if (nreset == 1'b0) begin
		current_bit <= '0;
	end
end

assign mosi = send_data == 1 ? data[7 - current_bit] : 0;
assign next = current_bit == 3'b110; // one bit early to allow for a response in time

assign sck = clk;

endmodule