`timescale 1ps / 1ps

module testbench;

reg clk;
wire sck;
wire mosi;
wire cs;
wire dc;

top t(
	.CLK(clk),
	.DISPLAY_SCK(sck),
	.DISPLAY_MOSI(mosi),
	.DISPLAY_CS(cs),
	.DISPLAY_DC(dc)
);

initial begin
	$dumpfile("iverilog.vcd");
	$dumpvars(0, testbench);

	clk = 0;

	#10000000
	$finish;
end

always begin
	#1 clk = ~clk;
end


endmodule