`timescale 1ps / 1ps

module top(
  input  CLK,
	output DISPLAY_SCK,
	output DISPLAY_MOSI,
	output DISPLAY_CS,
	output DISPLAY_DC
);

logic nreset_r = 0;

logic [5:0] red_r;
logic [5:0] green_r;
logic [5:0] blue_r;

wire frame;
wire pixel;
wire [7:0] x;
wire [7:0] y;

logic [5:0] counter;

display display_inst(
	.nreset(nreset_r),
	.clk(CLK),
	.red(red_r),
	.green(green_r),
	.blue(blue_r),
	.x(x),
	.y(y),
	.frame(frame),
	.pixel(pixel),
	.sck(DISPLAY_SCK),
	.cs(DISPLAY_CS),
	.mosi(DISPLAY_MOSI),
	.dc(DISPLAY_DC)
);

always_ff @(posedge CLK) begin
	if (nreset_r) begin
		if (frame) begin
			counter <= counter - 1;
		end
		red_r <= y[7:2] + counter[5:0];
		green_r <= 6'b000000;
		blue_r <= 6'b000000;
	end else begin
		nreset_r <= 1;

		counter <= 0;
	end
end

endmodule