39 lines
843 B
Makefile
39 lines
843 B
Makefile
YOSYS = yosys
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NEXTPNR = nextpnr-ice40
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ICEPACK = icepack
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DFU_UTIL = dfu-util
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BIN2UF2 = bin2uf2
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IVERILOG = iverilog
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ICETIME = icetime
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VVP = vvp
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RTL = top.sv spi.sv display.sv
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all: gateware.bin
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clean:
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$(RM) *.json *.asc *.bin *.uf2 *.vcd *.vvp
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sim: iverilog.vcd
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prog: gateware.bin
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$(DFU_UTIL) -d 1209:b1c0 -a 1 -D gateware.bin
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prog_flash: gateware.bin
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$(DFU_UTIL) -d 1209:b1c0 -a 0 -D gateware.bin -R
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gateware.bin: $(RTL)
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$(YOSYS) -q -p "read_verilog -sv $(RTL); synth_ice40 -top top -json $*.json"
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$(NEXTPNR) -q --randomize-seed --up5k --package sg48 --pcf constraints.pcf --json $*.json --asc $*.asc
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$(ICEPACK) $*.asc $@
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$(ICETIME) $*.asc -mtd up5k
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iverilog.vcd: testbench.sv $(RTL)
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$(IVERILOG) -g2012 -Wall -o $*vvp.vvp testbench.sv $(RTL)
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$(VVP) $*vvp.vvp $@
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.bin.uf2:
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$(BIN2UF2) -o $@ $<
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.SUFFIXES: .v .sv .asc .bin .uf2
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