56 lines
777 B
Systemverilog
56 lines
777 B
Systemverilog
`timescale 1ps / 1ps
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module top(
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input CLK,
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output DISPLAY_SCK,
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output DISPLAY_MOSI,
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output DISPLAY_CS,
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output DISPLAY_DC
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);
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logic nreset_r = 0;
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logic [5:0] red_r;
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logic [5:0] green_r;
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logic [5:0] blue_r;
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wire frame;
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wire pixel;
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wire [7:0] x;
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wire [7:0] y;
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logic [5:0] counter;
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display display_inst(
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.nreset(nreset_r),
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.clk(CLK),
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.red(red_r),
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.green(green_r),
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.blue(blue_r),
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.x(x),
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.y(y),
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.frame(frame),
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.pixel(pixel),
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.sck(DISPLAY_SCK),
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.cs(DISPLAY_CS),
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.mosi(DISPLAY_MOSI),
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.dc(DISPLAY_DC)
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);
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always_ff @(posedge CLK) begin
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if (nreset_r) begin
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if (frame) begin
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counter <= counter - 1;
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end
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red_r <= y[7:2] + counter[5:0];
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green_r <= 6'b000000;
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blue_r <= 6'b000000;
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end else begin
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nreset_r <= 1;
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counter <= 0;
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end
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end
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endmodule
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