44 lines
598 B
Systemverilog
44 lines
598 B
Systemverilog
`timescale 1ps / 1ps
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module top(
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input CLK,
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output LED_R,
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output LED_G,
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output LED_B,
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output DISPLAY_SCK,
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output DISPLAY_MOSI,
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output DISPLAY_CS,
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output DISPLAY_DC
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);
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localparam N = 18;
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logic [N:0] counter;
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logic nreset_r = 0;
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display display_inst(
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.nreset(nreset_r),
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.clk(CLK),
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.sck(DISPLAY_SCK),
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.cs(DISPLAY_CS),
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.mosi(DISPLAY_MOSI),
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.dc(DISPLAY_DC)
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);
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always_ff @(posedge CLK) begin
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if (nreset_r) begin
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counter <= counter + 1;
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end else begin
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counter <= '0;
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nreset_r <= 1;
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end
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end
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assign LED_R = 1'b1;
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assign LED_G = counter[N];
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assign LED_B = 1'b1;
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endmodule
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