35 lines
341 B
Systemverilog
35 lines
341 B
Systemverilog
`timescale 1ps / 1ps
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module testbench;
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reg clk;
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wire sck;
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wire mosi;
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wire cs;
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wire dc;
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top t(
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.CLK(clk),
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.DISPLAY_SCK(sck),
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.DISPLAY_MOSI(mosi),
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.DISPLAY_CS(cs),
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.DISPLAY_DC(dc)
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);
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initial begin
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$dumpfile("iverilog.vcd");
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$dumpvars(0, testbench);
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clk = 0;
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#10000000
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$finish;
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end
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always begin
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#1 clk = ~clk;
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end
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endmodule
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