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AMDGPU: Replace some float undef test uses with poison (#131090)

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Matt Arsenault 2025-03-13 20:07:48 +07:00 committed by GitHub
parent d507b3d7ce
commit 024df9c9dc
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63 changed files with 179 additions and 179 deletions
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4
llvm/test/CodeGen/AMDGPU/GlobalISel/i1-copy.ll
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@ -22,7 +22,7 @@ main_body:
%vcc = icmp eq i32 %val, 2 %vcc = icmp eq i32 %val, 2
%a = select i1 %vcc, float %a0, float %a1 %a = select i1 %vcc, float %a0, float %a1
%b = select i1 %vcc, float %b0, float %b1 %b = select i1 %vcc, float %b0, float %b1
call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %a, float %b, float undef, float undef, i1 true, i1 true) call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %a, float %b, float poison, float poison, i1 true, i1 true)
ret void ret void
} }
@ -52,7 +52,7 @@ main_body:
%uniform_i1 = icmp eq i32 %val, 2 %uniform_i1 = icmp eq i32 %val, 2
%a = select i1 %uniform_i1, float %a0, float %a1 %a = select i1 %uniform_i1, float %a0, float %a1
%b = select i1 %uniform_i1, float %b0, float %b1 %b = select i1 %uniform_i1, float %b0, float %b1
call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %a, float %b, float undef, float undef, i1 true, i1 true) call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %a, float %b, float poison, float poison, i1 true, i1 true)
ret void ret void
} }

6
llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_vs.ll
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@ -10,7 +10,7 @@ define amdgpu_vs void @test_f32_inreg(float inreg %arg0) {
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
; CHECK-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.exp), 32, 15, [[COPY]](s32), [[DEF]](s32), [[DEF]](s32), [[DEF]](s32), 0, 0 ; CHECK-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.exp), 32, 15, [[COPY]](s32), [[DEF]](s32), [[DEF]](s32), [[DEF]](s32), 0, 0
; CHECK-NEXT: S_ENDPGM 0 ; CHECK-NEXT: S_ENDPGM 0
call void @llvm.amdgcn.exp.f32(i32 32, i32 15, float %arg0, float undef, float undef, float undef, i1 false, i1 false) #0 call void @llvm.amdgcn.exp.f32(i32 32, i32 15, float %arg0, float poison, float poison, float poison, i1 false, i1 false) #0
ret void ret void
} }
@ -23,7 +23,7 @@ define amdgpu_vs void @test_f32(float %arg0) {
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
; CHECK-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.exp), 32, 15, [[COPY]](s32), [[DEF]](s32), [[DEF]](s32), [[DEF]](s32), 0, 0 ; CHECK-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.exp), 32, 15, [[COPY]](s32), [[DEF]](s32), [[DEF]](s32), [[DEF]](s32), 0, 0
; CHECK-NEXT: S_ENDPGM 0 ; CHECK-NEXT: S_ENDPGM 0
call void @llvm.amdgcn.exp.f32(i32 32, i32 15, float %arg0, float undef, float undef, float undef, i1 false, i1 false) #0 call void @llvm.amdgcn.exp.f32(i32 32, i32 15, float %arg0, float poison, float poison, float poison, i1 false, i1 false) #0
ret void ret void
} }
@ -55,7 +55,7 @@ define amdgpu_vs void @test_sgpr_alignment0(float inreg %arg0, ptr addrspace(4)
; CHECK-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.exp), 32, 15, [[COPY]](s32), [[DEF]](s32), [[DEF]](s32), [[DEF]](s32), 0, 0 ; CHECK-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.exp), 32, 15, [[COPY]](s32), [[DEF]](s32), [[DEF]](s32), [[DEF]](s32), 0, 0
; CHECK-NEXT: S_ENDPGM 0 ; CHECK-NEXT: S_ENDPGM 0
%tmp0 = load volatile i32, ptr addrspace(4) %arg1 %tmp0 = load volatile i32, ptr addrspace(4) %arg1
call void @llvm.amdgcn.exp.f32(i32 32, i32 15, float %arg0, float undef, float undef, float undef, i1 false, i1 false) #0 call void @llvm.amdgcn.exp.f32(i32 32, i32 15, float %arg0, float poison, float poison, float poison, i1 false, i1 false) #0
ret void ret void
} }

6
llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.div.scale.ll
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@ -1543,7 +1543,7 @@ define amdgpu_kernel void @test_div_scale_f32_val_undef_val(ptr addrspace(1) %ou
; GFX11-NEXT: v_div_scale_f32 v0, null, s0, s0, 0x41000000 ; GFX11-NEXT: v_div_scale_f32 v0, null, s0, s0, 0x41000000
; GFX11-NEXT: global_store_b32 v1, v0, s[0:1] ; GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
; GFX11-NEXT: s_endpgm ; GFX11-NEXT: s_endpgm
%result = call { float, i1 } @llvm.amdgcn.div.scale.f32(float 8.0, float undef, i1 false) %result = call { float, i1 } @llvm.amdgcn.div.scale.f32(float 8.0, float poison, i1 false)
%result0 = extractvalue { float, i1 } %result, 0 %result0 = extractvalue { float, i1 } %result, 0
store float %result0, ptr addrspace(1) %out, align 4 store float %result0, ptr addrspace(1) %out, align 4
ret void ret void
@ -1589,7 +1589,7 @@ define amdgpu_kernel void @test_div_scale_f32_undef_val_val(ptr addrspace(1) %ou
; GFX11-NEXT: v_div_scale_f32 v0, null, 0x41000000, 0x41000000, s0 ; GFX11-NEXT: v_div_scale_f32 v0, null, 0x41000000, 0x41000000, s0
; GFX11-NEXT: global_store_b32 v1, v0, s[0:1] ; GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
; GFX11-NEXT: s_endpgm ; GFX11-NEXT: s_endpgm
%result = call { float, i1 } @llvm.amdgcn.div.scale.f32(float undef, float 8.0, i1 false) %result = call { float, i1 } @llvm.amdgcn.div.scale.f32(float poison, float 8.0, i1 false)
%result0 = extractvalue { float, i1 } %result, 0 %result0 = extractvalue { float, i1 } %result, 0
store float %result0, ptr addrspace(1) %out, align 4 store float %result0, ptr addrspace(1) %out, align 4
ret void ret void
@ -1633,7 +1633,7 @@ define amdgpu_kernel void @test_div_scale_f32_undef_undef_val(ptr addrspace(1) %
; GFX11-NEXT: v_div_scale_f32 v0, null, s0, s0, s0 ; GFX11-NEXT: v_div_scale_f32 v0, null, s0, s0, s0
; GFX11-NEXT: global_store_b32 v1, v0, s[0:1] ; GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
; GFX11-NEXT: s_endpgm ; GFX11-NEXT: s_endpgm
%result = call { float, i1 } @llvm.amdgcn.div.scale.f32(float undef, float undef, i1 false) %result = call { float, i1 } @llvm.amdgcn.div.scale.f32(float poison, float poison, i1 false)
%result0 = extractvalue { float, i1 } %result, 0 %result0 = extractvalue { float, i1 } %result, 0
store float %result0, ptr addrspace(1) %out, align 4 store float %result0, ptr addrspace(1) %out, align 4
ret void ret void

6
llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.fmul.legacy.ll
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@ -82,7 +82,7 @@ define float @v_mul_legacy_undef0_f32(float %a) {
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_mul_dx9_zero_f32_e32 v0, s0, v0 ; GFX11-NEXT: v_mul_dx9_zero_f32_e32 v0, s0, v0
; GFX11-NEXT: s_setpc_b64 s[30:31] ; GFX11-NEXT: s_setpc_b64 s[30:31]
%result = call float @llvm.amdgcn.fmul.legacy(float undef, float %a) %result = call float @llvm.amdgcn.fmul.legacy(float poison, float %a)
ret float %result ret float %result
} }
@ -122,7 +122,7 @@ define float @v_mul_legacy_undef1_f32(float %a) {
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_mul_dx9_zero_f32_e32 v0, s0, v0 ; GFX11-NEXT: v_mul_dx9_zero_f32_e32 v0, s0, v0
; GFX11-NEXT: s_setpc_b64 s[30:31] ; GFX11-NEXT: s_setpc_b64 s[30:31]
%result = call float @llvm.amdgcn.fmul.legacy(float %a, float undef) %result = call float @llvm.amdgcn.fmul.legacy(float %a, float poison)
ret float %result ret float %result
} }
@ -162,7 +162,7 @@ define float @v_mul_legacy_undef_f32() {
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_mul_dx9_zero_f32_e64 v0, s0, s0 ; GFX11-NEXT: v_mul_dx9_zero_f32_e64 v0, s0, s0
; GFX11-NEXT: s_setpc_b64 s[30:31] ; GFX11-NEXT: s_setpc_b64 s[30:31]
%result = call float @llvm.amdgcn.fmul.legacy(float undef, float undef) %result = call float @llvm.amdgcn.fmul.legacy(float poison, float poison)
ret float %result ret float %result
} }

2
llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.rsq.clamp.ll
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@ -175,7 +175,7 @@ define float @v_rsq_clamp_undef_f32() #0 {
; GFX12-NEXT: s_delay_alu instid0(TRANS32_DEP_1) | instid1(VALU_DEP_1) ; GFX12-NEXT: s_delay_alu instid0(TRANS32_DEP_1) | instid1(VALU_DEP_1)
; GFX12-NEXT: v_minmax_num_f32 v0, s0, 0x7f7fffff, v0 ; GFX12-NEXT: v_minmax_num_f32 v0, s0, 0x7f7fffff, v0
; GFX12-NEXT: s_setpc_b64 s[30:31] ; GFX12-NEXT: s_setpc_b64 s[30:31]
%rsq_clamp = call float @llvm.amdgcn.rsq.clamp.f32(float undef) %rsq_clamp = call float @llvm.amdgcn.rsq.clamp.f32(float poison)
ret float %rsq_clamp ret float %rsq_clamp
} }

10
llvm/test/CodeGen/AMDGPU/adjust-writemask-invalid-copy.ll
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@ -7,7 +7,7 @@
; GCN: buffer_store_dword v0 ; GCN: buffer_store_dword v0
define amdgpu_ps void @adjust_writemask_crash_0_nochain() #0 { define amdgpu_ps void @adjust_writemask_crash_0_nochain() #0 {
main_body: main_body:
%tmp = call <2 x float> @llvm.amdgcn.image.getlod.1d.v2f32.f32(i32 3, float undef, <8 x i32> poison, <4 x i32> poison, i1 0, i32 0, i32 0) %tmp = call <2 x float> @llvm.amdgcn.image.getlod.1d.v2f32.f32(i32 3, float poison, <8 x i32> poison, <4 x i32> poison, i1 0, i32 0, i32 0)
%tmp1 = bitcast <2 x float> %tmp to <2 x i32> %tmp1 = bitcast <2 x float> %tmp to <2 x i32>
%tmp2 = shufflevector <2 x i32> %tmp1, <2 x i32> poison, <4 x i32> <i32 1, i32 poison, i32 poison, i32 poison> %tmp2 = shufflevector <2 x i32> %tmp1, <2 x i32> poison, <4 x i32> <i32 1, i32 poison, i32 poison, i32 poison>
%tmp3 = bitcast <4 x i32> %tmp2 to <4 x float> %tmp3 = bitcast <4 x i32> %tmp2 to <4 x float>
@ -23,7 +23,7 @@ main_body:
; GCN: buffer_store_dword v0 ; GCN: buffer_store_dword v0
define amdgpu_ps void @adjust_writemask_crash_1_nochain() #0 { define amdgpu_ps void @adjust_writemask_crash_1_nochain() #0 {
main_body: main_body:
%tmp = call <2 x float> @llvm.amdgcn.image.getlod.1d.v2f32.f32(i32 3, float undef, <8 x i32> poison, <4 x i32> poison, i1 0, i32 0, i32 0) %tmp = call <2 x float> @llvm.amdgcn.image.getlod.1d.v2f32.f32(i32 3, float poison, <8 x i32> poison, <4 x i32> poison, i1 0, i32 0, i32 0)
%tmp1 = bitcast <2 x float> %tmp to <2 x i32> %tmp1 = bitcast <2 x float> %tmp to <2 x i32>
%tmp2 = shufflevector <2 x i32> %tmp1, <2 x i32> poison, <4 x i32> <i32 1, i32 0, i32 poison, i32 poison> %tmp2 = shufflevector <2 x i32> %tmp1, <2 x i32> poison, <4 x i32> <i32 1, i32 0, i32 poison, i32 poison>
%tmp3 = bitcast <4 x i32> %tmp2 to <4 x float> %tmp3 = bitcast <4 x i32> %tmp2 to <4 x float>
@ -39,7 +39,7 @@ main_body:
; GCN: buffer_store_dword v0 ; GCN: buffer_store_dword v0
define amdgpu_ps void @adjust_writemask_crash_0_chain() #0 { define amdgpu_ps void @adjust_writemask_crash_0_chain() #0 {
main_body: main_body:
%tmp = call <2 x float> @llvm.amdgcn.image.sample.1d.v2f32.f32(i32 3, float undef, <8 x i32> poison, <4 x i32> poison, i1 0, i32 0, i32 0) %tmp = call <2 x float> @llvm.amdgcn.image.sample.1d.v2f32.f32(i32 3, float poison, <8 x i32> poison, <4 x i32> poison, i1 0, i32 0, i32 0)
%tmp1 = bitcast <2 x float> %tmp to <2 x i32> %tmp1 = bitcast <2 x float> %tmp to <2 x i32>
%tmp2 = shufflevector <2 x i32> %tmp1, <2 x i32> poison, <4 x i32> <i32 1, i32 poison, i32 poison, i32 poison> %tmp2 = shufflevector <2 x i32> %tmp1, <2 x i32> poison, <4 x i32> <i32 1, i32 poison, i32 poison, i32 poison>
%tmp3 = bitcast <4 x i32> %tmp2 to <4 x float> %tmp3 = bitcast <4 x i32> %tmp2 to <4 x float>
@ -55,7 +55,7 @@ main_body:
; GCN: buffer_store_dword v0 ; GCN: buffer_store_dword v0
define amdgpu_ps void @adjust_writemask_crash_1_chain() #0 { define amdgpu_ps void @adjust_writemask_crash_1_chain() #0 {
main_body: main_body:
%tmp = call <2 x float> @llvm.amdgcn.image.sample.1d.v2f32.f32(i32 3, float undef, <8 x i32> poison, <4 x i32> poison, i1 0, i32 0, i32 0) %tmp = call <2 x float> @llvm.amdgcn.image.sample.1d.v2f32.f32(i32 3, float poison, <8 x i32> poison, <4 x i32> poison, i1 0, i32 0, i32 0)
%tmp1 = bitcast <2 x float> %tmp to <2 x i32> %tmp1 = bitcast <2 x float> %tmp to <2 x i32>
%tmp2 = shufflevector <2 x i32> %tmp1, <2 x i32> poison, <4 x i32> <i32 1, i32 0, i32 poison, i32 poison> %tmp2 = shufflevector <2 x i32> %tmp1, <2 x i32> poison, <4 x i32> <i32 1, i32 0, i32 poison, i32 poison>
%tmp3 = bitcast <4 x i32> %tmp2 to <4 x float> %tmp3 = bitcast <4 x i32> %tmp2 to <4 x float>
@ -66,7 +66,7 @@ main_body:
define amdgpu_ps void @adjust_writemask_crash_0_v4() #0 { define amdgpu_ps void @adjust_writemask_crash_0_v4() #0 {
main_body: main_body:
%tmp = call <4 x float> @llvm.amdgcn.image.getlod.1d.v4f32.f32(i32 5, float undef, <8 x i32> poison, <4 x i32> poison, i1 0, i32 0, i32 0) %tmp = call <4 x float> @llvm.amdgcn.image.getlod.1d.v4f32.f32(i32 5, float poison, <8 x i32> poison, <4 x i32> poison, i1 0, i32 0, i32 0)
%tmp1 = bitcast <4 x float> %tmp to <4 x i32> %tmp1 = bitcast <4 x float> %tmp to <4 x i32>
%tmp2 = shufflevector <4 x i32> %tmp1, <4 x i32> poison, <4 x i32> <i32 1, i32 poison, i32 poison, i32 poison> %tmp2 = shufflevector <4 x i32> %tmp1, <4 x i32> poison, <4 x i32> <i32 1, i32 poison, i32 poison, i32 poison>
%tmp3 = bitcast <4 x i32> %tmp2 to <4 x float> %tmp3 = bitcast <4 x i32> %tmp2 to <4 x float>

10
llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-fdiv.ll
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@ -4009,7 +4009,7 @@ define <4 x float> @fdiv_constant_f32_vector(ptr addrspace(1) %out, <2 x float>
; IEEE-GOODFREXP-NEXT: [[TMP14:%.*]] = extractvalue { float, i32 } [[TMP13]], 0 ; IEEE-GOODFREXP-NEXT: [[TMP14:%.*]] = extractvalue { float, i32 } [[TMP13]], 0
; IEEE-GOODFREXP-NEXT: [[TMP15:%.*]] = extractvalue { float, i32 } [[TMP13]], 1 ; IEEE-GOODFREXP-NEXT: [[TMP15:%.*]] = extractvalue { float, i32 } [[TMP13]], 1
; IEEE-GOODFREXP-NEXT: [[TMP16:%.*]] = call float @llvm.amdgcn.rcp.f32(float [[TMP14]]) ; IEEE-GOODFREXP-NEXT: [[TMP16:%.*]] = call float @llvm.amdgcn.rcp.f32(float [[TMP14]])
; IEEE-GOODFREXP-NEXT: [[TMP17:%.*]] = call { float, i32 } @llvm.frexp.f32.i32(float undef) ; IEEE-GOODFREXP-NEXT: [[TMP17:%.*]] = call { float, i32 } @llvm.frexp.f32.i32(float poison)
; IEEE-GOODFREXP-NEXT: [[TMP18:%.*]] = extractvalue { float, i32 } [[TMP17]], 0 ; IEEE-GOODFREXP-NEXT: [[TMP18:%.*]] = extractvalue { float, i32 } [[TMP17]], 0
; IEEE-GOODFREXP-NEXT: [[TMP19:%.*]] = extractvalue { float, i32 } [[TMP17]], 1 ; IEEE-GOODFREXP-NEXT: [[TMP19:%.*]] = extractvalue { float, i32 } [[TMP17]], 1
; IEEE-GOODFREXP-NEXT: [[TMP20:%.*]] = fmul float [[TMP18]], [[TMP16]] ; IEEE-GOODFREXP-NEXT: [[TMP20:%.*]] = fmul float [[TMP18]], [[TMP16]]
@ -4049,9 +4049,9 @@ define <4 x float> @fdiv_constant_f32_vector(ptr addrspace(1) %out, <2 x float>
; IEEE-BADFREXP-NEXT: [[TMP14:%.*]] = extractvalue { float, i32 } [[TMP13]], 0 ; IEEE-BADFREXP-NEXT: [[TMP14:%.*]] = extractvalue { float, i32 } [[TMP13]], 0
; IEEE-BADFREXP-NEXT: [[TMP15:%.*]] = call i32 @llvm.amdgcn.frexp.exp.i32.f32(float 3.200000e+01) ; IEEE-BADFREXP-NEXT: [[TMP15:%.*]] = call i32 @llvm.amdgcn.frexp.exp.i32.f32(float 3.200000e+01)
; IEEE-BADFREXP-NEXT: [[TMP16:%.*]] = call float @llvm.amdgcn.rcp.f32(float [[TMP14]]) ; IEEE-BADFREXP-NEXT: [[TMP16:%.*]] = call float @llvm.amdgcn.rcp.f32(float [[TMP14]])
; IEEE-BADFREXP-NEXT: [[TMP17:%.*]] = call { float, i32 } @llvm.frexp.f32.i32(float undef) ; IEEE-BADFREXP-NEXT: [[TMP17:%.*]] = call { float, i32 } @llvm.frexp.f32.i32(float poison)
; IEEE-BADFREXP-NEXT: [[TMP18:%.*]] = extractvalue { float, i32 } [[TMP17]], 0 ; IEEE-BADFREXP-NEXT: [[TMP18:%.*]] = extractvalue { float, i32 } [[TMP17]], 0
; IEEE-BADFREXP-NEXT: [[TMP19:%.*]] = call i32 @llvm.amdgcn.frexp.exp.i32.f32(float undef) ; IEEE-BADFREXP-NEXT: [[TMP19:%.*]] = call i32 @llvm.amdgcn.frexp.exp.i32.f32(float poison)
; IEEE-BADFREXP-NEXT: [[TMP20:%.*]] = fmul float [[TMP18]], [[TMP16]] ; IEEE-BADFREXP-NEXT: [[TMP20:%.*]] = fmul float [[TMP18]], [[TMP16]]
; IEEE-BADFREXP-NEXT: [[TMP21:%.*]] = sub i32 [[TMP19]], [[TMP15]] ; IEEE-BADFREXP-NEXT: [[TMP21:%.*]] = sub i32 [[TMP19]], [[TMP15]]
; IEEE-BADFREXP-NEXT: [[TMP22:%.*]] = call float @llvm.ldexp.f32.i32(float [[TMP20]], i32 [[TMP21]]) ; IEEE-BADFREXP-NEXT: [[TMP22:%.*]] = call float @llvm.ldexp.f32.i32(float [[TMP20]], i32 [[TMP21]])
@ -4079,7 +4079,7 @@ define <4 x float> @fdiv_constant_f32_vector(ptr addrspace(1) %out, <2 x float>
; DAZ-NEXT: [[TMP4:%.*]] = extractvalue { float, i32 } [[TMP3]], 0 ; DAZ-NEXT: [[TMP4:%.*]] = extractvalue { float, i32 } [[TMP3]], 0
; DAZ-NEXT: [[TMP5:%.*]] = extractvalue { float, i32 } [[TMP3]], 1 ; DAZ-NEXT: [[TMP5:%.*]] = extractvalue { float, i32 } [[TMP3]], 1
; DAZ-NEXT: [[TMP6:%.*]] = call float @llvm.amdgcn.rcp.f32(float [[TMP4]]) ; DAZ-NEXT: [[TMP6:%.*]] = call float @llvm.amdgcn.rcp.f32(float [[TMP4]])
; DAZ-NEXT: [[TMP7:%.*]] = call { float, i32 } @llvm.frexp.f32.i32(float undef) ; DAZ-NEXT: [[TMP7:%.*]] = call { float, i32 } @llvm.frexp.f32.i32(float poison)
; DAZ-NEXT: [[TMP8:%.*]] = extractvalue { float, i32 } [[TMP7]], 0 ; DAZ-NEXT: [[TMP8:%.*]] = extractvalue { float, i32 } [[TMP7]], 0
; DAZ-NEXT: [[TMP9:%.*]] = extractvalue { float, i32 } [[TMP7]], 1 ; DAZ-NEXT: [[TMP9:%.*]] = extractvalue { float, i32 } [[TMP7]], 1
; DAZ-NEXT: [[TMP10:%.*]] = fmul float [[TMP8]], [[TMP6]] ; DAZ-NEXT: [[TMP10:%.*]] = fmul float [[TMP8]], [[TMP6]]
@ -4101,7 +4101,7 @@ define <4 x float> @fdiv_constant_f32_vector(ptr addrspace(1) %out, <2 x float>
; DAZ-NEXT: [[CONST_PARTIAL_RCP:%.*]] = insertelement <4 x float> [[TMP25]], float [[TMP22]], i64 3 ; DAZ-NEXT: [[CONST_PARTIAL_RCP:%.*]] = insertelement <4 x float> [[TMP25]], float [[TMP22]], i64 3
; DAZ-NEXT: ret <4 x float> [[CONST_PARTIAL_RCP]] ; DAZ-NEXT: ret <4 x float> [[CONST_PARTIAL_RCP]]
; ;
%const.partial.rcp = fdiv <4 x float> <float 1.0, float -1.0, float undef, float 2.0>, <float 0.5, float 2.0, float 32.0, float 10.0>, !fpmath !2 %const.partial.rcp = fdiv <4 x float> <float 1.0, float -1.0, float poison, float 2.0>, <float 0.5, float 2.0, float 32.0, float 10.0>, !fpmath !2
ret <4 x float> %const.partial.rcp ret <4 x float> %const.partial.rcp
} }

2
llvm/test/CodeGen/AMDGPU/amdgpu-reloc-const.ll
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@ -17,7 +17,7 @@
define amdgpu_ps void @ps_main(i32 %arg, i32 inreg %arg1, i32 inreg %arg2) local_unnamed_addr #0 { define amdgpu_ps void @ps_main(i32 %arg, i32 inreg %arg1, i32 inreg %arg2) local_unnamed_addr #0 {
%rc = call i32 @llvm.amdgcn.reloc.constant(metadata !1) %rc = call i32 @llvm.amdgcn.reloc.constant(metadata !1)
%rcf = bitcast i32 %rc to float %rcf = bitcast i32 %rc to float
call void @llvm.amdgcn.exp.f32(i32 40, i32 15, float %rcf, float undef, float undef, float undef, i1 false, i1 false) #0 call void @llvm.amdgcn.exp.f32(i32 40, i32 15, float %rcf, float poison, float poison, float poison, i1 false, i1 false) #0
ret void ret void
} }

2
llvm/test/CodeGen/AMDGPU/cndmask-no-def-vcc.ll
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@ -37,7 +37,7 @@ bb2:
define amdgpu_kernel void @preserve_condition_undef_flag(float %arg, i32 %arg1, float %arg2) { define amdgpu_kernel void @preserve_condition_undef_flag(float %arg, i32 %arg1, float %arg2) {
bb0: bb0:
%tmp = icmp sgt i32 %arg1, 4 %tmp = icmp sgt i32 %arg1, 4
%undef = call i1 @llvm.amdgcn.class.f32(float undef, i32 undef) %undef = call i1 @llvm.amdgcn.class.f32(float poison, i32 undef)
%tmp4 = select i1 %undef, float %arg, float 1.000000e+00 %tmp4 = select i1 %undef, float %arg, float 1.000000e+00
%tmp5 = fcmp ogt float %arg2, 0.000000e+00 %tmp5 = fcmp ogt float %arg2, 0.000000e+00
%tmp6 = fcmp olt float %arg2, 1.000000e+00 %tmp6 = fcmp olt float %arg2, 1.000000e+00

2
llvm/test/CodeGen/AMDGPU/commute-shifts.ll
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@ -38,7 +38,7 @@ bb:
%tmp5 = and i32 %tmp2, %tmp4 %tmp5 = and i32 %tmp2, %tmp4
%tmp6 = icmp eq i32 %tmp5, 0 %tmp6 = icmp eq i32 %tmp5, 0
%tmp7 = select i1 %tmp6, float 0.000000e+00, float %arg1 %tmp7 = select i1 %tmp6, float 0.000000e+00, float %arg1
%tmp8 = call <2 x half> @llvm.amdgcn.cvt.pkrtz(float undef, float %tmp7) %tmp8 = call <2 x half> @llvm.amdgcn.cvt.pkrtz(float poison, float %tmp7)
%tmp9 = bitcast <2 x half> %tmp8 to float %tmp9 = bitcast <2 x half> %tmp8 to float
ret float %tmp9 ret float %tmp9
} }

2
llvm/test/CodeGen/AMDGPU/cse-phi-incoming-val.ll
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@ -31,7 +31,7 @@ bb9: ; preds = %bb5
bb10: ; preds = %bb9, %bb5, %bb3, %bb bb10: ; preds = %bb9, %bb5, %bb3, %bb
%tmp11 = phi float [ 1.000000e+00, %bb3 ], [ 0.000000e+00, %bb9 ], [ 1.000000e+00, %bb ], [ poison, %bb5 ] %tmp11 = phi float [ 1.000000e+00, %bb3 ], [ 0.000000e+00, %bb9 ], [ 1.000000e+00, %bb ], [ poison, %bb5 ]
call void @llvm.amdgcn.exp.f32(i32 40, i32 15, float %tmp11, float undef, float undef, float undef, i1 false, i1 false) #0 call void @llvm.amdgcn.exp.f32(i32 40, i32 15, float %tmp11, float poison, float poison, float poison, i1 false, i1 false) #0
ret void ret void
} }

20
llvm/test/CodeGen/AMDGPU/dagcombine-fma-fmad.ll
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@ -143,21 +143,21 @@ define amdgpu_ps float @_amdgpu_ps_main() #0 {
; GFX11-NEXT: v_max_f32_e32 v0, 0, v1 ; GFX11-NEXT: v_max_f32_e32 v0, 0, v1
; GFX11-NEXT: ; return to shader part epilog ; GFX11-NEXT: ; return to shader part epilog
.entry: .entry:
%0 = call <3 x float> @llvm.amdgcn.image.sample.2d.v3f32.f32(i32 7, float undef, float undef, <8 x i32> poison, <4 x i32> poison, i1 false, i32 0, i32 0) %0 = call <3 x float> @llvm.amdgcn.image.sample.2d.v3f32.f32(i32 7, float poison, float poison, <8 x i32> poison, <4 x i32> poison, i1 false, i32 0, i32 0)
%.i2243 = extractelement <3 x float> %0, i32 2 %.i2243 = extractelement <3 x float> %0, i32 2
%1 = call <3 x i32> @llvm.amdgcn.s.buffer.load.v3i32(<4 x i32> poison, i32 0, i32 0) %1 = call <3 x i32> @llvm.amdgcn.s.buffer.load.v3i32(<4 x i32> poison, i32 0, i32 0)
%2 = shufflevector <3 x i32> %1, <3 x i32> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 poison> %2 = shufflevector <3 x i32> %1, <3 x i32> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 poison>
%3 = bitcast <4 x i32> %2 to <4 x float> %3 = bitcast <4 x i32> %2 to <4 x float>
%.i2248 = extractelement <4 x float> %3, i32 2 %.i2248 = extractelement <4 x float> %3, i32 2
%.i2249 = fmul reassoc nnan nsz arcp contract afn float %.i2243, %.i2248 %.i2249 = fmul reassoc nnan nsz arcp contract afn float %.i2243, %.i2248
%4 = call reassoc nnan nsz arcp contract afn float @llvm.amdgcn.fmed3.f32(float undef, float 0.000000e+00, float 1.000000e+00) %4 = call reassoc nnan nsz arcp contract afn float @llvm.amdgcn.fmed3.f32(float poison, float 0.000000e+00, float 1.000000e+00)
%5 = call <3 x float> @llvm.amdgcn.image.sample.2d.v3f32.f32(i32 7, float undef, float undef, <8 x i32> poison, <4 x i32> poison, i1 false, i32 0, i32 0) %5 = call <3 x float> @llvm.amdgcn.image.sample.2d.v3f32.f32(i32 7, float poison, float poison, <8 x i32> poison, <4 x i32> poison, i1 false, i32 0, i32 0)
%.i2333 = extractelement <3 x float> %5, i32 2 %.i2333 = extractelement <3 x float> %5, i32 2
%6 = call reassoc nnan nsz arcp contract afn float @llvm.amdgcn.fmed3.f32(float undef, float 0.000000e+00, float 1.000000e+00) %6 = call reassoc nnan nsz arcp contract afn float @llvm.amdgcn.fmed3.f32(float poison, float 0.000000e+00, float 1.000000e+00)
%7 = call <2 x float> @llvm.amdgcn.image.sample.2d.v2f32.f32(i32 3, float undef, float undef, <8 x i32> poison, <4 x i32> poison, i1 false, i32 0, i32 0) %7 = call <2 x float> @llvm.amdgcn.image.sample.2d.v2f32.f32(i32 3, float poison, float poison, <8 x i32> poison, <4 x i32> poison, i1 false, i32 0, i32 0)
%.i1408 = extractelement <2 x float> %7, i32 1 %.i1408 = extractelement <2 x float> %7, i32 1
%.i0364 = extractelement <2 x float> %7, i32 0 %.i0364 = extractelement <2 x float> %7, i32 0
%8 = call float @llvm.amdgcn.image.sample.2d.f32.f32(i32 1, float undef, float undef, <8 x i32> poison, <4 x i32> poison, i1 false, i32 0, i32 0) %8 = call float @llvm.amdgcn.image.sample.2d.f32.f32(i32 1, float poison, float poison, <8 x i32> poison, <4 x i32> poison, i1 false, i32 0, i32 0)
%9 = call <3 x i32> @llvm.amdgcn.s.buffer.load.v3i32(<4 x i32> poison, i32 112, i32 0) %9 = call <3 x i32> @llvm.amdgcn.s.buffer.load.v3i32(<4 x i32> poison, i32 112, i32 0)
%10 = shufflevector <3 x i32> %9, <3 x i32> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 poison> %10 = shufflevector <3 x i32> %9, <3 x i32> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 poison>
%11 = bitcast <4 x i32> %10 to <4 x float> %11 = bitcast <4 x i32> %10 to <4 x float>
@ -175,7 +175,7 @@ define amdgpu_ps float @_amdgpu_ps_main() #0 {
%.i2376 = fsub reassoc nnan nsz arcp contract afn float %.i2373, %.i2370 %.i2376 = fsub reassoc nnan nsz arcp contract afn float %.i2373, %.i2370
%.i2383 = fmul reassoc nnan nsz arcp contract afn float %.i2376, %6 %.i2383 = fmul reassoc nnan nsz arcp contract afn float %.i2376, %6
%.i2386 = fadd reassoc nnan nsz arcp contract afn float %.i2370, %.i2383 %.i2386 = fadd reassoc nnan nsz arcp contract afn float %.i2370, %.i2383
%18 = call reassoc nnan nsz arcp contract afn float @llvm.amdgcn.fmed3.f32(float undef, float 0.000000e+00, float 1.000000e+00) %18 = call reassoc nnan nsz arcp contract afn float @llvm.amdgcn.fmed3.f32(float poison, float 0.000000e+00, float 1.000000e+00)
%19 = fmul reassoc nnan nsz arcp contract afn float %18, %.i2363 %19 = fmul reassoc nnan nsz arcp contract afn float %18, %.i2363
%.i2394 = fsub reassoc nnan nsz arcp contract afn float %.i2386, %19 %.i2394 = fsub reassoc nnan nsz arcp contract afn float %.i2386, %19
%.i2397 = fmul reassoc nnan nsz arcp contract afn float %.i2363, %18 %.i2397 = fmul reassoc nnan nsz arcp contract afn float %.i2363, %18
@ -206,8 +206,8 @@ define amdgpu_ps float @_amdgpu_ps_main() #0 {
%.i2415 = fmul reassoc nnan nsz arcp contract afn float %.i2407, %41 %.i2415 = fmul reassoc nnan nsz arcp contract afn float %.i2407, %41
%42 = call <3 x float> @llvm.amdgcn.image.load.mip.2d.v3f32.i32(i32 7, i32 undef, i32 undef, i32 0, <8 x i32> poison, i32 0, i32 0) %42 = call <3 x float> @llvm.amdgcn.image.load.mip.2d.v3f32.i32(i32 7, i32 undef, i32 undef, i32 0, <8 x i32> poison, i32 0, i32 0)
%.i2521 = extractelement <3 x float> %42, i32 2 %.i2521 = extractelement <3 x float> %42, i32 2
%43 = call reassoc nnan nsz arcp contract afn float @llvm.amdgcn.fmed3.f32(float undef, float 0.000000e+00, float 1.000000e+00) %43 = call reassoc nnan nsz arcp contract afn float @llvm.amdgcn.fmed3.f32(float poison, float 0.000000e+00, float 1.000000e+00)
%44 = call <3 x float> @llvm.amdgcn.image.sample.2d.v3f32.f32(i32 7, float undef, float undef, <8 x i32> poison, <4 x i32> poison, i1 false, i32 0, i32 0) %44 = call <3 x float> @llvm.amdgcn.image.sample.2d.v3f32.f32(i32 7, float poison, float poison, <8 x i32> poison, <4 x i32> poison, i1 false, i32 0, i32 0)
%.i2465 = extractelement <3 x float> %44, i32 2 %.i2465 = extractelement <3 x float> %44, i32 2
%.i2466 = fmul reassoc nnan nsz arcp contract afn float %.i2465, %43 %.i2466 = fmul reassoc nnan nsz arcp contract afn float %.i2465, %43
%.i2469 = fmul reassoc nnan nsz arcp contract afn float %.i2415, %.i2466 %.i2469 = fmul reassoc nnan nsz arcp contract afn float %.i2415, %.i2466
@ -224,7 +224,7 @@ define amdgpu_ps float @_amdgpu_ps_main() #0 {
%.i2488 = fmul reassoc nnan nsz arcp contract afn float %.i2249, %18 %.i2488 = fmul reassoc nnan nsz arcp contract afn float %.i2249, %18
%.i2491 = fmul reassoc nnan nsz arcp contract afn float %.i2485, %4 %.i2491 = fmul reassoc nnan nsz arcp contract afn float %.i2485, %4
%.i2494 = fadd reassoc nnan nsz arcp contract afn float %.i2479, %.i2491 %.i2494 = fadd reassoc nnan nsz arcp contract afn float %.i2479, %.i2491
%51 = call <3 x float> @llvm.amdgcn.image.sample.2d.v3f32.f32(i32 7, float undef, float undef, <8 x i32> poison, <4 x i32> poison, i1 false, i32 0, i32 0) %51 = call <3 x float> @llvm.amdgcn.image.sample.2d.v3f32.f32(i32 7, float poison, float poison, <8 x i32> poison, <4 x i32> poison, i1 false, i32 0, i32 0)
%.i2515 = extractelement <3 x float> %51, i32 2 %.i2515 = extractelement <3 x float> %51, i32 2
%.i2516 = fadd reassoc nnan nsz arcp contract afn float %.i2515, %.i2494 %.i2516 = fadd reassoc nnan nsz arcp contract afn float %.i2515, %.i2494
%.i2522 = fadd reassoc nnan nsz arcp contract afn float %.i2521, %.i2516 %.i2522 = fadd reassoc nnan nsz arcp contract afn float %.i2521, %.i2516

2
llvm/test/CodeGen/AMDGPU/diverge-extra-formal-args.ll
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@ -19,7 +19,7 @@ define dllexport amdgpu_vs void @_amdgpu_vs_main(i32 inreg %arg, i32 inreg %arg1
%tmp11 = load <2 x float>, ptr addrspace(4) %tmp10, align 8 %tmp11 = load <2 x float>, ptr addrspace(4) %tmp10, align 8
%tmp12 = fadd nnan arcp contract <2 x float> zeroinitializer, %tmp11 %tmp12 = fadd nnan arcp contract <2 x float> zeroinitializer, %tmp11
%tmp13 = extractelement <2 x float> %tmp12, i32 1 %tmp13 = extractelement <2 x float> %tmp12, i32 1
call void @llvm.amdgcn.exp.f32(i32 12, i32 15, float undef, float %tmp13, float 0.000000e+00, float 1.000000e+00, i1 true, i1 false) #1 call void @llvm.amdgcn.exp.f32(i32 12, i32 15, float poison, float %tmp13, float 0.000000e+00, float 1.000000e+00, i1 true, i1 false) #1
ret void ret void
} }

2
llvm/test/CodeGen/AMDGPU/diverge-interp-mov-lower.ll
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@ -20,7 +20,7 @@ define dllexport amdgpu_ps void @_amdgpu_ps_main(i32 inreg %arg) local_unnamed_a
%tmp5 = getelementptr [4 x <4 x float>], ptr addrspace(4) @0, i64 0, i64 %tmp4 %tmp5 = getelementptr [4 x <4 x float>], ptr addrspace(4) @0, i64 0, i64 %tmp4
%tmp6 = load <4 x float>, ptr addrspace(4) %tmp5, align 16 %tmp6 = load <4 x float>, ptr addrspace(4) %tmp5, align 16
%tmp7 = extractelement <4 x float> %tmp6, i32 3 %tmp7 = extractelement <4 x float> %tmp6, i32 3
%tmp8 = call <2 x half> @llvm.amdgcn.cvt.pkrtz(float undef, float %tmp7) #1 %tmp8 = call <2 x half> @llvm.amdgcn.cvt.pkrtz(float poison, float %tmp7) #1
call void @llvm.amdgcn.exp.compr.v2f16(i32 0, i32 15, <2 x half> undef, <2 x half> %tmp8, i1 true, i1 true) #2 call void @llvm.amdgcn.exp.compr.v2f16(i32 0, i32 15, <2 x half> undef, <2 x half> %tmp8, i1 true, i1 true) #2
ret void ret void
} }

4
llvm/test/CodeGen/AMDGPU/dual-source-blend-export.ll
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@ -83,8 +83,8 @@ define amdgpu_ps void @_amdgpu_ps_main(i32 inreg %PrimMask, <2 x float> %InterpC
%i50 = select i1 %.not, i32 %i47, i32 %i45 %i50 = select i1 %.not, i32 %i47, i32 %i45
%i51 = call i32 @llvm.amdgcn.mov.dpp8.i32(i32 %i50, i32 14570689) %i51 = call i32 @llvm.amdgcn.mov.dpp8.i32(i32 %i50, i32 14570689)
%i52 = bitcast i32 %i51 to float %i52 = bitcast i32 %i51 to float
call void @llvm.amdgcn.exp.f32(i32 21, i32 3, float %i41, float %i49, float undef, float undef, i1 false, i1 true) call void @llvm.amdgcn.exp.f32(i32 21, i32 3, float %i41, float %i49, float poison, float poison, i1 false, i1 true)
call void @llvm.amdgcn.exp.f32(i32 22, i32 3, float %i44, float %i52, float undef, float undef, i1 true, i1 true) call void @llvm.amdgcn.exp.f32(i32 22, i32 3, float %i44, float %i52, float poison, float poison, i1 true, i1 true)
ret void ret void
} }

2
llvm/test/CodeGen/AMDGPU/i1-copy-from-loop.ll
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@ -74,7 +74,7 @@ for.end:
br i1 %cc, label %if, label %end br i1 %cc, label %if, label %end
if: if:
call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float undef, float undef, float undef, float undef, i1 true, i1 true) call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float poison, float poison, float poison, float poison, i1 true, i1 true)
br label %end br label %end
end: end:

2
llvm/test/CodeGen/AMDGPU/insert_vector_elt.ll
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@ -390,7 +390,7 @@ define <4 x float> @insertelement_to_sgpr() nounwind {
; GCN-NEXT: s_setpc_b64 s[30:31] ; GCN-NEXT: s_setpc_b64 s[30:31]
%tmp = load <4 x i32>, ptr addrspace(4) undef %tmp = load <4 x i32>, ptr addrspace(4) undef
%tmp1 = insertelement <4 x i32> %tmp, i32 0, i32 0 %tmp1 = insertelement <4 x i32> %tmp, i32 0, i32 0
%tmp2 = call <4 x float> @llvm.amdgcn.image.gather4.lz.2d.v4f32.f32(i32 1, float undef, float undef, <8 x i32> poison, <4 x i32> %tmp1, i1 0, i32 0, i32 0) %tmp2 = call <4 x float> @llvm.amdgcn.image.gather4.lz.2d.v4f32.f32(i32 1, float poison, float poison, <8 x i32> poison, <4 x i32> %tmp1, i1 0, i32 0, i32 0)
ret <4 x float> %tmp2 ret <4 x float> %tmp2
} }

4
llvm/test/CodeGen/AMDGPU/ipra-return-address-save-restore.ll
View File

@ -113,7 +113,7 @@ bsdf_alloc.exit2188: ; preds = %if.end.i2186, %clos
br i1 false, label %common.ret, label %if.then534 br i1 false, label %common.ret, label %if.then534
if.then534: ; preds = %bsdf_alloc.exit2188 if.then534: ; preds = %bsdf_alloc.exit2188
%.op7 = fmul nsz float undef, 0.000000e+00 %.op7 = fmul nsz float poison, 0.000000e+00
%mul558 = select i1 %cmp440, float 0.000000e+00, float %1 %mul558 = select i1 %cmp440, float 0.000000e+00, float %1
%15 = tail call float @llvm.amdgcn.fmed3.f32(float 0.000000e+00, float 0.000000e+00, float 0.000000e+00) %15 = tail call float @llvm.amdgcn.fmed3.f32(float 0.000000e+00, float 0.000000e+00, float 0.000000e+00)
store float %mul558, ptr addrspace(1) null, align 4 store float %mul558, ptr addrspace(1) null, align 4
@ -185,7 +185,7 @@ sw.bb10:
; GCN-DAG: v_readlane_b32 s30, [[CSR_VGPR]], ; GCN-DAG: v_readlane_b32 s30, [[CSR_VGPR]],
; GCN: s_waitcnt vmcnt(0) ; GCN: s_waitcnt vmcnt(0)
; GCN: s_setpc_b64 s[30:31] ; GCN: s_setpc_b64 s[30:31]
call fastcc void @svm_node_closure_bsdf(ptr addrspace(1) null, ptr null, <4 x i32> zeroinitializer, ptr null, i32 undef, i8 undef, float undef, float undef, float undef, i1 undef, <4 x i32> poison, float undef, i32 undef, i1 undef, i1 undef, i1 undef, float undef, ptr addrspace(1) poison, ptr addrspace(1) poison, ptr addrspace(1) poison, i1 undef, ptr addrspace(1) poison, i32 undef, i1 undef, i32 undef, i64 undef, i32 undef) call fastcc void @svm_node_closure_bsdf(ptr addrspace(1) null, ptr null, <4 x i32> zeroinitializer, ptr null, i32 undef, i8 undef, float poison, float poison, float poison, i1 undef, <4 x i32> poison, float poison, i32 undef, i1 undef, i1 undef, i1 undef, float poison, ptr addrspace(1) poison, ptr addrspace(1) poison, ptr addrspace(1) poison, i1 undef, ptr addrspace(1) poison, i32 undef, i1 undef, i32 undef, i64 undef, i32 undef)
ret void ret void
} }

2
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.class.ll
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@ -501,7 +501,7 @@ define amdgpu_kernel void @test_class_0_f64(ptr addrspace(1) %out, double %a) #0
; SI: buffer_store_dword [[RESULT]] ; SI: buffer_store_dword [[RESULT]]
; SI: s_endpgm ; SI: s_endpgm
define amdgpu_kernel void @test_class_undef_f32(ptr addrspace(1) %out, float %a, i32 %b) #0 { define amdgpu_kernel void @test_class_undef_f32(ptr addrspace(1) %out, float %a, i32 %b) #0 {
%result = call i1 @llvm.amdgcn.class.f32(float undef, i32 %b) #1 %result = call i1 @llvm.amdgcn.class.f32(float poison, i32 %b) #1
%sext = sext i1 %result to i32 %sext = sext i1 %result to i32
store i32 %sext, ptr addrspace(1) %out, align 4 store i32 %sext, ptr addrspace(1) %out, align 4
ret void ret void

2
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pkrtz.ll
View File

@ -133,7 +133,7 @@ define amdgpu_kernel void @s_cvt_pkrtz_undef_undef(ptr addrspace(1) %out) #0 {
; GFX11-LABEL: s_cvt_pkrtz_undef_undef: ; GFX11-LABEL: s_cvt_pkrtz_undef_undef:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_endpgm ; GFX11-NEXT: s_endpgm
%result = call <2 x half> @llvm.amdgcn.cvt.pkrtz(float undef, float undef) %result = call <2 x half> @llvm.amdgcn.cvt.pkrtz(float poison, float poison)
store <2 x half> %result, ptr addrspace(1) %out store <2 x half> %result, ptr addrspace(1) %out
ret void ret void
} }

6
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.div.scale.ll
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@ -413,7 +413,7 @@ define amdgpu_kernel void @test_div_scale_f32_fabs_den(ptr addrspace(1) %out, pt
; SI: s_mov_b32 [[K:s[0-9]+]], 0x41000000 ; SI: s_mov_b32 [[K:s[0-9]+]], 0x41000000
; SI: v_div_scale_f32 v{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, [[K]], v{{[0-9]+}}, [[K]] ; SI: v_div_scale_f32 v{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, [[K]], v{{[0-9]+}}, [[K]]
define amdgpu_kernel void @test_div_scale_f32_val_undef_val(ptr addrspace(1) %out) #0 { define amdgpu_kernel void @test_div_scale_f32_val_undef_val(ptr addrspace(1) %out) #0 {
%result = call { float, i1 } @llvm.amdgcn.div.scale.f32(float 8.0, float undef, i1 false) %result = call { float, i1 } @llvm.amdgcn.div.scale.f32(float 8.0, float poison, i1 false)
%result0 = extractvalue { float, i1 } %result, 0 %result0 = extractvalue { float, i1 } %result, 0
store float %result0, ptr addrspace(1) %out, align 4 store float %result0, ptr addrspace(1) %out, align 4
ret void ret void
@ -423,7 +423,7 @@ define amdgpu_kernel void @test_div_scale_f32_val_undef_val(ptr addrspace(1) %ou
; SI: s_mov_b32 [[K:s[0-9]+]], 0x41000000 ; SI: s_mov_b32 [[K:s[0-9]+]], 0x41000000
; SI: v_div_scale_f32 v{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, [[K]], [[K]], v{{[0-9]+}} ; SI: v_div_scale_f32 v{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, [[K]], [[K]], v{{[0-9]+}}
define amdgpu_kernel void @test_div_scale_f32_undef_val_val(ptr addrspace(1) %out) #0 { define amdgpu_kernel void @test_div_scale_f32_undef_val_val(ptr addrspace(1) %out) #0 {
%result = call { float, i1 } @llvm.amdgcn.div.scale.f32(float undef, float 8.0, i1 false) %result = call { float, i1 } @llvm.amdgcn.div.scale.f32(float poison, float 8.0, i1 false)
%result0 = extractvalue { float, i1 } %result, 0 %result0 = extractvalue { float, i1 } %result, 0
store float %result0, ptr addrspace(1) %out, align 4 store float %result0, ptr addrspace(1) %out, align 4
ret void ret void
@ -433,7 +433,7 @@ define amdgpu_kernel void @test_div_scale_f32_undef_val_val(ptr addrspace(1) %ou
; SI-NOT: v0 ; SI-NOT: v0
; SI: v_div_scale_f32 v{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, s0, s0, v0 ; SI: v_div_scale_f32 v{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, s0, s0, v0
define amdgpu_kernel void @test_div_scale_f32_undef_undef_val(ptr addrspace(1) %out) #0 { define amdgpu_kernel void @test_div_scale_f32_undef_undef_val(ptr addrspace(1) %out) #0 {
%result = call { float, i1 } @llvm.amdgcn.div.scale.f32(float undef, float undef, i1 false) %result = call { float, i1 } @llvm.amdgcn.div.scale.f32(float poison, float poison, i1 false)
%result0 = extractvalue { float, i1 } %result, 0 %result0 = extractvalue { float, i1 } %result, 0
store float %result0, ptr addrspace(1) %out, align 4 store float %result0, ptr addrspace(1) %out, align 4
ret void ret void

8
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.exp.row.ll
View File

@ -41,8 +41,8 @@ define amdgpu_kernel void @undef_f32() #0 {
; GFX12-NEXT: export pos0 off, off, off, off row_en ; GFX12-NEXT: export pos0 off, off, off, off row_en
; GFX12-NEXT: export pos1 off, off, off, off done row_en ; GFX12-NEXT: export pos1 off, off, off, off done row_en
; GFX12-NEXT: s_endpgm ; GFX12-NEXT: s_endpgm
call void @llvm.amdgcn.exp.row.f32(i32 12, i32 0, float undef, float undef, float undef, float undef, i1 false, i32 0) call void @llvm.amdgcn.exp.row.f32(i32 12, i32 0, float poison, float poison, float poison, float poison, i1 false, i32 0)
call void @llvm.amdgcn.exp.row.f32(i32 13, i32 0, float undef, float undef, float undef, float undef, i1 true, i32 0) call void @llvm.amdgcn.exp.row.f32(i32 13, i32 0, float poison, float poison, float poison, float poison, i1 true, i32 0)
ret void ret void
} }
@ -83,8 +83,8 @@ define amdgpu_kernel void @one_f32() #0 {
; GFX12-NEXT: export pos0 v0, v0, v0, off row_en ; GFX12-NEXT: export pos0 v0, v0, v0, off row_en
; GFX12-NEXT: export pos1 v0, v0, v0, off done row_en ; GFX12-NEXT: export pos1 v0, v0, v0, off done row_en
; GFX12-NEXT: s_endpgm ; GFX12-NEXT: s_endpgm
call void @llvm.amdgcn.exp.row.f32(i32 12, i32 7, float 1.0, float 1.0, float 1.0, float undef, i1 false, i32 0) call void @llvm.amdgcn.exp.row.f32(i32 12, i32 7, float 1.0, float 1.0, float 1.0, float poison, i1 false, i32 0)
call void @llvm.amdgcn.exp.row.f32(i32 13, i32 7, float 1.0, float 1.0, float 1.0, float undef, i1 true, i32 0) call void @llvm.amdgcn.exp.row.f32(i32 13, i32 7, float 1.0, float 1.0, float 1.0, float poison, i1 true, i32 0)
ret void ret void
} }

4
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fmul.legacy.ll
View File

@ -19,7 +19,7 @@ define amdgpu_kernel void @test_mul_legacy_f32(ptr addrspace(1) %out, float %a,
; GCN: v_mul_legacy_f32{{[_e3264]*}} v{{[0-9]+}}, s{{[0-9]+}}, {{[sv][0-9]+}} ; GCN: v_mul_legacy_f32{{[_e3264]*}} v{{[0-9]+}}, s{{[0-9]+}}, {{[sv][0-9]+}}
; GFX11: v_mul_dx9_zero_f32_e64 v{{[0-9]+}}, s{{[0-9]+}}, s{{[0-9]+}} ; GFX11: v_mul_dx9_zero_f32_e64 v{{[0-9]+}}, s{{[0-9]+}}, s{{[0-9]+}}
define amdgpu_kernel void @test_mul_legacy_undef0_f32(ptr addrspace(1) %out, float %a) #0 { define amdgpu_kernel void @test_mul_legacy_undef0_f32(ptr addrspace(1) %out, float %a) #0 {
%result = call float @llvm.amdgcn.fmul.legacy(float undef, float %a) %result = call float @llvm.amdgcn.fmul.legacy(float poison, float %a)
store float %result, ptr addrspace(1) %out, align 4 store float %result, ptr addrspace(1) %out, align 4
ret void ret void
} }
@ -28,7 +28,7 @@ define amdgpu_kernel void @test_mul_legacy_undef0_f32(ptr addrspace(1) %out, flo
; GCN: v_mul_legacy_f32{{[_e3264]*}} v{{[0-9]+}}, s{{[0-9]+}}, {{[sv][0-9]+}} ; GCN: v_mul_legacy_f32{{[_e3264]*}} v{{[0-9]+}}, s{{[0-9]+}}, {{[sv][0-9]+}}
; GFX11: v_mul_dx9_zero_f32_e64 v{{[0-9]+}}, s{{[0-9]+}}, s{{[0-9]+}} ; GFX11: v_mul_dx9_zero_f32_e64 v{{[0-9]+}}, s{{[0-9]+}}, s{{[0-9]+}}
define amdgpu_kernel void @test_mul_legacy_undef1_f32(ptr addrspace(1) %out, float %a) #0 { define amdgpu_kernel void @test_mul_legacy_undef1_f32(ptr addrspace(1) %out, float %a) #0 {
%result = call float @llvm.amdgcn.fmul.legacy(float %a, float undef) %result = call float @llvm.amdgcn.fmul.legacy(float %a, float poison)
store float %result, ptr addrspace(1) %out, align 4 store float %result, ptr addrspace(1) %out, align 4
ret void ret void
} }

2
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fract.ll
View File

@ -24,7 +24,7 @@ define amdgpu_kernel void @v_fract_f64(ptr addrspace(1) %out, double %src) #1 {
; GCN-NOT: v_fract_f32 ; GCN-NOT: v_fract_f32
; GCN-NOT: store_dword ; GCN-NOT: store_dword
define amdgpu_kernel void @v_fract_undef_f32(ptr addrspace(1) %out) #1 { define amdgpu_kernel void @v_fract_undef_f32(ptr addrspace(1) %out) #1 {
%fract = call float @llvm.amdgcn.fract.f32(float undef) %fract = call float @llvm.amdgcn.fract.f32(float poison)
store float %fract, ptr addrspace(1) %out store float %fract, ptr addrspace(1) %out
ret void ret void
} }

8
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.nsa.ll
View File

@ -116,7 +116,7 @@ main_body:
; GCN-LABEL: {{^}}sample_undef_undef_undef_undef: ; GCN-LABEL: {{^}}sample_undef_undef_undef_undef:
; GCN: image_sample_c_b v0, v[0:3], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_1D_ARRAY ; GCN: image_sample_c_b v0, v[0:3], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_1D_ARRAY
define amdgpu_ps float @sample_undef_undef_undef_undef(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp) { define amdgpu_ps float @sample_undef_undef_undef_undef(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp) {
%r = call float @llvm.amdgcn.image.sample.c.b.1darray.f32.f32.f32(i32 1, float undef, float undef, float undef, float undef, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0) %r = call float @llvm.amdgcn.image.sample.c.b.1darray.f32.f32.f32(i32 1, float poison, float poison, float poison, float poison, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0)
ret float %r ret float %r
} }
@ -125,7 +125,7 @@ define amdgpu_ps float @sample_undef_undef_undef_undef(<8 x i32> inreg %rsrc, <4
; NONSA: image_sample_c_b v0, v[0:3], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_1D_ARRAY ; NONSA: image_sample_c_b v0, v[0:3], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_1D_ARRAY
; NSA: image_sample_c_b v0, [v0, v0, v0, v0], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_1D_ARRAY ; NSA: image_sample_c_b v0, [v0, v0, v0, v0], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_1D_ARRAY
define amdgpu_ps float @sample_undef_undef_undef_def(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %layer) { define amdgpu_ps float @sample_undef_undef_undef_def(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %layer) {
%r = call float @llvm.amdgcn.image.sample.c.b.1darray.f32.f32.f32(i32 1, float undef, float undef, float undef, float %layer, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0) %r = call float @llvm.amdgcn.image.sample.c.b.1darray.f32.f32.f32(i32 1, float poison, float poison, float poison, float %layer, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0)
ret float %r ret float %r
} }
@ -134,7 +134,7 @@ define amdgpu_ps float @sample_undef_undef_undef_def(<8 x i32> inreg %rsrc, <4 x
; GCN: image_sample_c_b v0, v[0:3], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_1D_ARRAY ; GCN: image_sample_c_b v0, v[0:3], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_1D_ARRAY
define amdgpu_ps float @sample_undef_undef_undef_def_rnd(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %layer) { define amdgpu_ps float @sample_undef_undef_undef_def_rnd(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %layer) {
%layer_rnd = call float @llvm.rint.f32(float %layer) %layer_rnd = call float @llvm.rint.f32(float %layer)
%r = call float @llvm.amdgcn.image.sample.c.b.1darray.f32.f32.f32(i32 1, float undef, float undef, float undef, float %layer_rnd, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0) %r = call float @llvm.amdgcn.image.sample.c.b.1darray.f32.f32.f32(i32 1, float poison, float poison, float poison, float %layer_rnd, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0)
ret float %r ret float %r
} }
@ -147,7 +147,7 @@ define amdgpu_ps float @sample_def_undef_undef_undef(<8 x i32> inreg %rsrc, <4 x
; eliminated in the presence of undef, just add an arbitrary intermediate ; eliminated in the presence of undef, just add an arbitrary intermediate
; computation. ; computation.
%c0 = fadd float %z0, 1.0 %c0 = fadd float %z0, 1.0
%r = call float @llvm.amdgcn.image.sample.c.b.1darray.f32.f32.f32(i32 1, float %c0, float undef, float undef, float undef, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0) %r = call float @llvm.amdgcn.image.sample.c.b.1darray.f32.f32.f32(i32 1, float %c0, float poison, float poison, float poison, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0)
ret float %r ret float %r
} }

14
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.load.ll
View File

@ -556,7 +556,7 @@ main_body:
%r5 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %a5, i32 0, i32 0) %r5 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %a5, i32 0, i32 0)
%r6 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %a6, i32 0, i32 0) %r6 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %a6, i32 0, i32 0)
call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r1, float %r2, float %r3, float %r4, i1 true, i1 true) call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r1, float %r2, float %r3, float %r4, i1 true, i1 true)
call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r5, float %r6, float undef, float undef, i1 true, i1 true) call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r5, float %r6, float poison, float poison, i1 true, i1 true)
ret void ret void
} }
@ -644,7 +644,7 @@ main_body:
%r5 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %a5, i32 0, i32 0) %r5 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %a5, i32 0, i32 0)
%r6 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %a6, i32 0, i32 0) %r6 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %a6, i32 0, i32 0)
call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r1, float %r2, float %r3, float %r4, i1 true, i1 true) call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r1, float %r2, float %r3, float %r4, i1 true, i1 true)
call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r5, float %r6, float undef, float undef, i1 true, i1 true) call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r5, float %r6, float poison, float poison, i1 true, i1 true)
ret void ret void
} }
@ -709,7 +709,7 @@ main_body:
%r5 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %a5, i32 0, i32 3) %r5 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %a5, i32 0, i32 3)
%r6 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %a6, i32 0, i32 3) %r6 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %a6, i32 0, i32 3)
call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r1, float %r2, float %r3, float %r4, i1 true, i1 true) call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r1, float %r2, float %r3, float %r4, i1 true, i1 true)
call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r5, float %r6, float undef, float undef, i1 true, i1 true) call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r5, float %r6, float poison, float poison, i1 true, i1 true)
ret void ret void
} }
@ -851,7 +851,7 @@ main_body:
%r5 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 28, i32 0, i32 0) %r5 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 28, i32 0, i32 0)
%r6 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 32, i32 0, i32 0) %r6 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 32, i32 0, i32 0)
call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r1, float %r2, float %r3, float %r4, i1 true, i1 true) call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r1, float %r2, float %r3, float %r4, i1 true, i1 true)
call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r5, float %r6, float undef, float undef, i1 true, i1 true) call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r5, float %r6, float poison, float poison, i1 true, i1 true)
ret void ret void
} }
@ -1308,7 +1308,7 @@ main_body:
%r5 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 28, i32 0, i32 0) %r5 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 28, i32 0, i32 0)
%r6 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 32, i32 0, i32 0) %r6 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 32, i32 0, i32 0)
call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r1, float %r2, float %r3, float %r4, i1 true, i1 true) call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r1, float %r2, float %r3, float %r4, i1 true, i1 true)
call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r5, float %r6, float undef, float undef, i1 true, i1 true) call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r5, float %r6, float poison, float poison, i1 true, i1 true)
ret void ret void
} }
@ -1375,7 +1375,7 @@ main_body:
%r5 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 28, i32 0, i32 8) %r5 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 28, i32 0, i32 8)
%r6 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 32, i32 0, i32 8) %r6 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 32, i32 0, i32 8)
call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r1, float %r2, float %r3, float %r4, i1 true, i1 true) call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r1, float %r2, float %r3, float %r4, i1 true, i1 true)
call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r5, float %r6, float undef, float undef, i1 true, i1 true) call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r5, float %r6, float poison, float poison, i1 true, i1 true)
ret void ret void
} }
@ -1434,7 +1434,7 @@ main_body:
%r5 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 28, i32 0, i32 64) %r5 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 28, i32 0, i32 64)
%r6 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 32, i32 0, i32 64) %r6 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 32, i32 0, i32 64)
call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r1, float %r2, float %r3, float %r4, i1 true, i1 true) call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r1, float %r2, float %r3, float %r4, i1 true, i1 true)
call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r5, float %r6, float undef, float undef, i1 true, i1 true) call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r5, float %r6, float poison, float poison, i1 true, i1 true)
ret void ret void
} }

12
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.load.ll
View File

@ -476,7 +476,7 @@ main_body:
%r5 = call float @llvm.amdgcn.raw.ptr.buffer.load.f32(ptr addrspace(8) %rsrc, i32 %a5, i32 0, i32 0) %r5 = call float @llvm.amdgcn.raw.ptr.buffer.load.f32(ptr addrspace(8) %rsrc, i32 %a5, i32 0, i32 0)
%r6 = call float @llvm.amdgcn.raw.ptr.buffer.load.f32(ptr addrspace(8) %rsrc, i32 %a6, i32 0, i32 0) %r6 = call float @llvm.amdgcn.raw.ptr.buffer.load.f32(ptr addrspace(8) %rsrc, i32 %a6, i32 0, i32 0)
call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r1, float %r2, float %r3, float %r4, i1 true, i1 true) call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r1, float %r2, float %r3, float %r4, i1 true, i1 true)
call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r5, float %r6, float undef, float undef, i1 true, i1 true) call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r5, float %r6, float poison, float poison, i1 true, i1 true)
ret void ret void
} }
@ -530,7 +530,7 @@ main_body:
%r5 = call float @llvm.amdgcn.raw.ptr.buffer.load.f32(ptr addrspace(8) %rsrc, i32 %a5, i32 0, i32 0) %r5 = call float @llvm.amdgcn.raw.ptr.buffer.load.f32(ptr addrspace(8) %rsrc, i32 %a5, i32 0, i32 0)
%r6 = call float @llvm.amdgcn.raw.ptr.buffer.load.f32(ptr addrspace(8) %rsrc, i32 %a6, i32 0, i32 0) %r6 = call float @llvm.amdgcn.raw.ptr.buffer.load.f32(ptr addrspace(8) %rsrc, i32 %a6, i32 0, i32 0)
call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r1, float %r2, float %r3, float %r4, i1 true, i1 true) call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r1, float %r2, float %r3, float %r4, i1 true, i1 true)
call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r5, float %r6, float undef, float undef, i1 true, i1 true) call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r5, float %r6, float poison, float poison, i1 true, i1 true)
ret void ret void
} }
@ -583,7 +583,7 @@ main_body:
%r5 = call float @llvm.amdgcn.raw.ptr.buffer.load.f32(ptr addrspace(8) %rsrc, i32 %a5, i32 0, i32 3) %r5 = call float @llvm.amdgcn.raw.ptr.buffer.load.f32(ptr addrspace(8) %rsrc, i32 %a5, i32 0, i32 3)
%r6 = call float @llvm.amdgcn.raw.ptr.buffer.load.f32(ptr addrspace(8) %rsrc, i32 %a6, i32 0, i32 3) %r6 = call float @llvm.amdgcn.raw.ptr.buffer.load.f32(ptr addrspace(8) %rsrc, i32 %a6, i32 0, i32 3)
call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r1, float %r2, float %r3, float %r4, i1 true, i1 true) call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r1, float %r2, float %r3, float %r4, i1 true, i1 true)
call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r5, float %r6, float undef, float undef, i1 true, i1 true) call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r5, float %r6, float poison, float poison, i1 true, i1 true)
ret void ret void
} }
@ -699,7 +699,7 @@ main_body:
%r5 = call float @llvm.amdgcn.raw.ptr.buffer.load.f32(ptr addrspace(8) %rsrc, i32 28, i32 0, i32 0) %r5 = call float @llvm.amdgcn.raw.ptr.buffer.load.f32(ptr addrspace(8) %rsrc, i32 28, i32 0, i32 0)
%r6 = call float @llvm.amdgcn.raw.ptr.buffer.load.f32(ptr addrspace(8) %rsrc, i32 32, i32 0, i32 0) %r6 = call float @llvm.amdgcn.raw.ptr.buffer.load.f32(ptr addrspace(8) %rsrc, i32 32, i32 0, i32 0)
call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r1, float %r2, float %r3, float %r4, i1 true, i1 true) call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r1, float %r2, float %r3, float %r4, i1 true, i1 true)
call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r5, float %r6, float undef, float undef, i1 true, i1 true) call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r5, float %r6, float poison, float poison, i1 true, i1 true)
ret void ret void
} }
@ -1116,7 +1116,7 @@ main_body:
%r5 = call float @llvm.amdgcn.raw.ptr.buffer.load.f32(ptr addrspace(8) %rsrc, i32 28, i32 0, i32 0) %r5 = call float @llvm.amdgcn.raw.ptr.buffer.load.f32(ptr addrspace(8) %rsrc, i32 28, i32 0, i32 0)
%r6 = call float @llvm.amdgcn.raw.ptr.buffer.load.f32(ptr addrspace(8) %rsrc, i32 32, i32 0, i32 0) %r6 = call float @llvm.amdgcn.raw.ptr.buffer.load.f32(ptr addrspace(8) %rsrc, i32 32, i32 0, i32 0)
call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r1, float %r2, float %r3, float %r4, i1 true, i1 true) call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r1, float %r2, float %r3, float %r4, i1 true, i1 true)
call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r5, float %r6, float undef, float undef, i1 true, i1 true) call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r5, float %r6, float poison, float poison, i1 true, i1 true)
ret void ret void
} }
@ -1172,7 +1172,7 @@ main_body:
%r5 = call float @llvm.amdgcn.raw.ptr.buffer.load.f32(ptr addrspace(8) %rsrc, i32 28, i32 0, i32 8) %r5 = call float @llvm.amdgcn.raw.ptr.buffer.load.f32(ptr addrspace(8) %rsrc, i32 28, i32 0, i32 8)
%r6 = call float @llvm.amdgcn.raw.ptr.buffer.load.f32(ptr addrspace(8) %rsrc, i32 32, i32 0, i32 8) %r6 = call float @llvm.amdgcn.raw.ptr.buffer.load.f32(ptr addrspace(8) %rsrc, i32 32, i32 0, i32 8)
call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r1, float %r2, float %r3, float %r4, i1 true, i1 true) call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r1, float %r2, float %r3, float %r4, i1 true, i1 true)
call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r5, float %r6, float undef, float undef, i1 true, i1 true) call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r5, float %r6, float poison, float poison, i1 true, i1 true)
ret void ret void
} }

2
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rcp.legacy.ll
View File

@ -33,7 +33,7 @@ define amdgpu_kernel void @rcp_legacy_f32_constant_100.0(ptr addrspace(1) %out)
; GCN-LABEL: {{^}}rcp_legacy_undef_f32: ; GCN-LABEL: {{^}}rcp_legacy_undef_f32:
; GCN-NOT: v_rcp_legacy_f32 ; GCN-NOT: v_rcp_legacy_f32
define amdgpu_kernel void @rcp_legacy_undef_f32(ptr addrspace(1) %out) #1 { define amdgpu_kernel void @rcp_legacy_undef_f32(ptr addrspace(1) %out) #1 {
%rcp = call float @llvm.amdgcn.rcp.legacy(float undef) %rcp = call float @llvm.amdgcn.rcp.legacy(float poison)
store float %rcp, ptr addrspace(1) %out, align 4 store float %rcp, ptr addrspace(1) %out, align 4
ret void ret void
} }

2
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rcp.ll
View File

@ -13,7 +13,7 @@ declare float @llvm.sqrt.f32(float) #0
; SI-NOT: [[NAN]] ; SI-NOT: [[NAN]]
; SI: buffer_store_dword [[NAN]] ; SI: buffer_store_dword [[NAN]]
define amdgpu_kernel void @rcp_undef_f32(ptr addrspace(1) %out) #1 { define amdgpu_kernel void @rcp_undef_f32(ptr addrspace(1) %out) #1 {
%rcp = call float @llvm.amdgcn.rcp.f32(float undef) %rcp = call float @llvm.amdgcn.rcp.f32(float poison)
store float %rcp, ptr addrspace(1) %out, align 4 store float %rcp, ptr addrspace(1) %out, align 4
ret void ret void
} }

2
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rsq.clamp.ll
View File

@ -39,7 +39,7 @@ define amdgpu_kernel void @rsq_clamp_f64(ptr addrspace(1) %out, double %src) #0
; FUNC-LABEL: {{^}}rsq_clamp_undef_f32: ; FUNC-LABEL: {{^}}rsq_clamp_undef_f32:
; SI-NOT: v_rsq_clamp_f32 ; SI-NOT: v_rsq_clamp_f32
define amdgpu_kernel void @rsq_clamp_undef_f32(ptr addrspace(1) %out) #0 { define amdgpu_kernel void @rsq_clamp_undef_f32(ptr addrspace(1) %out) #0 {
%rsq_clamp = call float @llvm.amdgcn.rsq.clamp.f32(float undef) %rsq_clamp = call float @llvm.amdgcn.rsq.clamp.f32(float poison)
store float %rsq_clamp, ptr addrspace(1) %out store float %rsq_clamp, ptr addrspace(1) %out
ret void ret void
} }

2
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rsq.legacy.ll
View File

@ -30,7 +30,7 @@ define amdgpu_kernel void @rsq_legacy_f32_constant_100.0(ptr addrspace(1) %out)
; FUNC-LABEL: {{^}}rsq_legacy_undef_f32: ; FUNC-LABEL: {{^}}rsq_legacy_undef_f32:
; SI-NOT: v_rsq_legacy_f32 ; SI-NOT: v_rsq_legacy_f32
define amdgpu_kernel void @rsq_legacy_undef_f32(ptr addrspace(1) %out) #1 { define amdgpu_kernel void @rsq_legacy_undef_f32(ptr addrspace(1) %out) #1 {
%rsq = call float @llvm.amdgcn.rsq.legacy(float undef) %rsq = call float @llvm.amdgcn.rsq.legacy(float poison)
store float %rsq, ptr addrspace(1) %out, align 4 store float %rsq, ptr addrspace(1) %out, align 4
ret void ret void
} }

2
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rsq.ll
View File

@ -57,7 +57,7 @@ define amdgpu_kernel void @rsq_f64_constant_100.0(ptr addrspace(1) %out) #1 {
; FUNC-LABEL: {{^}}rsq_undef_f32: ; FUNC-LABEL: {{^}}rsq_undef_f32:
; SI-NOT: v_rsq_f32 ; SI-NOT: v_rsq_f32
define amdgpu_kernel void @rsq_undef_f32(ptr addrspace(1) %out) #1 { define amdgpu_kernel void @rsq_undef_f32(ptr addrspace(1) %out) #1 {
%rsq = call float @llvm.amdgcn.rsq.f32(float undef) %rsq = call float @llvm.amdgcn.rsq.f32(float poison)
store float %rsq, ptr addrspace(1) %out, align 4 store float %rsq, ptr addrspace(1) %out, align 4
ret void ret void
} }

24
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.buffer.load.ll
View File

@ -42,7 +42,7 @@ define amdgpu_ps void @s_buffer_load_imm(<4 x i32> inreg %desc) {
main_body: main_body:
%load = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %desc, i32 4, i32 0) %load = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %desc, i32 4, i32 0)
%bitcast = bitcast i32 %load to float %bitcast = bitcast i32 %load to float
call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %bitcast, float undef, float undef, float undef, i1 true, i1 true) call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %bitcast, float poison, float poison, float poison, i1 true, i1 true)
ret void ret void
} }
@ -81,7 +81,7 @@ define amdgpu_ps void @s_buffer_load_index(<4 x i32> inreg %desc, i32 inreg %ind
main_body: main_body:
%load = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %desc, i32 %index, i32 0) %load = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %desc, i32 %index, i32 0)
%bitcast = bitcast i32 %load to float %bitcast = bitcast i32 %load to float
call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %bitcast, float undef, float undef, float undef, i1 true, i1 true) call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %bitcast, float poison, float poison, float poison, i1 true, i1 true)
ret void ret void
} }
@ -109,7 +109,7 @@ define amdgpu_ps void @s_buffer_load_index_divergent(<4 x i32> inreg %desc, i32
main_body: main_body:
%load = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %desc, i32 %index, i32 0) %load = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %desc, i32 %index, i32 0)
%bitcast = bitcast i32 %load to float %bitcast = bitcast i32 %load to float
call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %bitcast, float undef, float undef, float undef, i1 true, i1 true) call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %bitcast, float poison, float poison, float poison, i1 true, i1 true)
ret void ret void
} }
@ -154,7 +154,7 @@ main_body:
%bitcast = bitcast <2 x i32> %load to <2 x float> %bitcast = bitcast <2 x i32> %load to <2 x float>
%x = extractelement <2 x float> %bitcast, i32 0 %x = extractelement <2 x float> %bitcast, i32 0
%y = extractelement <2 x float> %bitcast, i32 1 %y = extractelement <2 x float> %bitcast, i32 1
call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %x, float %y, float undef, float undef, i1 true, i1 true) call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %x, float %y, float poison, float poison, i1 true, i1 true)
ret void ret void
} }
@ -199,7 +199,7 @@ main_body:
%bitcast = bitcast <2 x i32> %load to <2 x float> %bitcast = bitcast <2 x i32> %load to <2 x float>
%x = extractelement <2 x float> %bitcast, i32 0 %x = extractelement <2 x float> %bitcast, i32 0
%y = extractelement <2 x float> %bitcast, i32 1 %y = extractelement <2 x float> %bitcast, i32 1
call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %x, float %y, float undef, float undef, i1 true, i1 true) call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %x, float %y, float poison, float poison, i1 true, i1 true)
ret void ret void
} }
@ -229,7 +229,7 @@ main_body:
%bitcast = bitcast <2 x i32> %load to <2 x float> %bitcast = bitcast <2 x i32> %load to <2 x float>
%x = extractelement <2 x float> %bitcast, i32 0 %x = extractelement <2 x float> %bitcast, i32 0
%y = extractelement <2 x float> %bitcast, i32 1 %y = extractelement <2 x float> %bitcast, i32 1
call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %x, float %y, float undef, float undef, i1 true, i1 true) call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %x, float %y, float poison, float poison, i1 true, i1 true)
ret void ret void
} }
@ -279,7 +279,7 @@ main_body:
%x = extractelement <3 x float> %bitcast, i32 0 %x = extractelement <3 x float> %bitcast, i32 0
%y = extractelement <3 x float> %bitcast, i32 1 %y = extractelement <3 x float> %bitcast, i32 1
%z = extractelement <3 x float> %bitcast, i32 2 %z = extractelement <3 x float> %bitcast, i32 2
call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %x, float %y, float %z, float undef, i1 true, i1 true) call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %x, float %y, float %z, float poison, i1 true, i1 true)
ret void ret void
} }
@ -329,7 +329,7 @@ main_body:
%x = extractelement <3 x float> %bitcast, i32 0 %x = extractelement <3 x float> %bitcast, i32 0
%y = extractelement <3 x float> %bitcast, i32 1 %y = extractelement <3 x float> %bitcast, i32 1
%z = extractelement <3 x float> %bitcast, i32 2 %z = extractelement <3 x float> %bitcast, i32 2
call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %x, float %y, float %z, float undef, i1 true, i1 true) call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %x, float %y, float %z, float poison, i1 true, i1 true)
ret void ret void
} }
@ -367,7 +367,7 @@ main_body:
%x = extractelement <3 x float> %bitcast, i32 0 %x = extractelement <3 x float> %bitcast, i32 0
%y = extractelement <3 x float> %bitcast, i32 1 %y = extractelement <3 x float> %bitcast, i32 1
%z = extractelement <3 x float> %bitcast, i32 2 %z = extractelement <3 x float> %bitcast, i32 2
call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %x, float %y, float %z, float undef, i1 true, i1 true) call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %x, float %y, float %z, float poison, i1 true, i1 true)
ret void ret void
} }
@ -563,7 +563,7 @@ main_body:
%load1 = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %desc, i32 8, i32 0) %load1 = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %desc, i32 8, i32 0)
%x = bitcast i32 %load0 to float %x = bitcast i32 %load0 to float
%y = bitcast i32 %load1 to float %y = bitcast i32 %load1 to float
call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %x, float %y, float undef, float undef, i1 true, i1 true) call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %x, float %y, float poison, float poison, i1 true, i1 true)
ret void ret void
} }
@ -763,7 +763,7 @@ bb1: ; preds = %main_body
%tmp1 = or i32 %tmp, 8 %tmp1 = or i32 %tmp, 8
%load = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %desc, i32 %tmp1, i32 0) %load = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %desc, i32 %tmp1, i32 0)
%bitcast = bitcast i32 %load to float %bitcast = bitcast i32 %load to float
call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %bitcast, float undef, float undef, float undef, i1 true, i1 true) call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %bitcast, float poison, float poison, float poison, i1 true, i1 true)
ret void ret void
} }
@ -802,7 +802,7 @@ bb1: ; preds = %main_body
%load2 = tail call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %desc, i32 %tmp2, i32 0) %load2 = tail call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %desc, i32 %tmp2, i32 0)
%bitcast = bitcast i32 %load to float %bitcast = bitcast i32 %load to float
%bitcast2 = bitcast i32 %load2 to float %bitcast2 = bitcast i32 %load2 to float
call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %bitcast, float %bitcast2, float undef, float undef, i1 true, i1 true) call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %bitcast, float %bitcast2, float poison, float poison, i1 true, i1 true)
ret void ret void
} }

2
llvm/test/CodeGen/AMDGPU/llvm.exp.ll
View File

@ -5338,7 +5338,7 @@ define float @v_exp_f32_undef() {
; CM: ; %bb.0: ; CM: ; %bb.0:
; CM-NEXT: CF_END ; CM-NEXT: CF_END
; CM-NEXT: PAD ; CM-NEXT: PAD
%result = call float @llvm.exp.f32(float undef) %result = call float @llvm.exp.f32(float poison)
ret float %result ret float %result
} }

2
llvm/test/CodeGen/AMDGPU/llvm.exp10.ll
View File

@ -5416,7 +5416,7 @@ define float @v_exp10_f32_undef() {
; CM: ; %bb.0: ; CM: ; %bb.0:
; CM-NEXT: CF_END ; CM-NEXT: CF_END
; CM-NEXT: PAD ; CM-NEXT: PAD
%result = call float @llvm.exp10.f32(float undef) %result = call float @llvm.exp10.f32(float poison)
ret float %result ret float %result
} }

2
llvm/test/CodeGen/AMDGPU/llvm.exp2.ll
View File

@ -2843,7 +2843,7 @@ define float @v_exp2_f32_undef() {
; CM: ; %bb.0: ; CM: ; %bb.0:
; CM-NEXT: CF_END ; CM-NEXT: CF_END
; CM-NEXT: PAD ; CM-NEXT: PAD
%result = call float @llvm.exp2.f32(float undef) %result = call float @llvm.exp2.f32(float poison)
ret float %result ret float %result
} }

2
llvm/test/CodeGen/AMDGPU/llvm.log.ll
View File

@ -5753,7 +5753,7 @@ define float @v_log_f32_undef() {
; CM: ; %bb.0: ; CM: ; %bb.0:
; CM-NEXT: CF_END ; CM-NEXT: CF_END
; CM-NEXT: PAD ; CM-NEXT: PAD
%result = call float @llvm.log.f32(float undef) %result = call float @llvm.log.f32(float poison)
ret float %result ret float %result
} }

2
llvm/test/CodeGen/AMDGPU/llvm.log10.ll
View File

@ -5753,7 +5753,7 @@ define float @v_log10_f32_undef() {
; CM: ; %bb.0: ; CM: ; %bb.0:
; CM-NEXT: CF_END ; CM-NEXT: CF_END
; CM-NEXT: PAD ; CM-NEXT: PAD
%result = call float @llvm.log10.f32(float undef) %result = call float @llvm.log10.f32(float poison)
ret float %result ret float %result
} }

2
llvm/test/CodeGen/AMDGPU/llvm.log2.ll
View File

@ -3589,7 +3589,7 @@ define float @v_log2_f32_undef() {
; CM: ; %bb.0: ; CM: ; %bb.0:
; CM-NEXT: CF_END ; CM-NEXT: CF_END
; CM-NEXT: PAD ; CM-NEXT: PAD
%result = call float @llvm.log2.f32(float undef) %result = call float @llvm.log2.f32(float poison)
ret float %result ret float %result
} }

4
llvm/test/CodeGen/AMDGPU/load-local-redundant-copies.ll
View File

@ -20,7 +20,7 @@ define amdgpu_vs void @test(ptr addrspace(8) inreg %arg1, ptr addrspace(3) %arg2
; CHECK-NEXT: v_mov_b32_e32 v4, 0 ; CHECK-NEXT: v_mov_b32_e32 v4, 0
; CHECK-NEXT: tbuffer_store_format_xyzw v[0:3], v4, s[0:3], 0 format:[BUF_DATA_FORMAT_32_32_32_32,BUF_NUM_FORMAT_FLOAT] idxen ; CHECK-NEXT: tbuffer_store_format_xyzw v[0:3], v4, s[0:3], 0 format:[BUF_DATA_FORMAT_32_32_32_32,BUF_NUM_FORMAT_FLOAT] idxen
; CHECK-NEXT: s_endpgm ; CHECK-NEXT: s_endpgm
call void @llvm.amdgcn.exp.f32(i32 0, i32 0, float undef, float undef, float undef, float undef, i1 false, i1 false) call void @llvm.amdgcn.exp.f32(i32 0, i32 0, float poison, float poison, float poison, float poison, i1 false, i1 false)
%var1 = load <6 x float>, ptr addrspace(3) %arg2, align 4 %var1 = load <6 x float>, ptr addrspace(3) %arg2, align 4
%var2 = shufflevector <6 x float> %var1, <6 x float> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3> %var2 = shufflevector <6 x float> %var1, <6 x float> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
call void @llvm.amdgcn.struct.ptr.tbuffer.store.v4f32(<4 x float> %var2, ptr addrspace(8) %arg1, i32 0, i32 0, i32 0, i32 126, i32 0) call void @llvm.amdgcn.struct.ptr.tbuffer.store.v4f32(<4 x float> %var2, ptr addrspace(8) %arg1, i32 0, i32 0, i32 0, i32 126, i32 0)
@ -107,7 +107,7 @@ define amdgpu_vs void @test_3(i32 inreg %arg1, i32 inreg %arg2, ptr addrspace(8)
%vec12 = shufflevector <6 x float> %load1, <6 x float> poison, <2 x i32> <i32 4, i32 5> %vec12 = shufflevector <6 x float> %load1, <6 x float> poison, <2 x i32> <i32 4, i32 5>
call void @llvm.amdgcn.struct.ptr.tbuffer.store.v2f32(<2 x float> %vec12, ptr addrspace(8) %arg3, i32 %arg1, i32 280, i32 %arg2, i32 64, i32 3) call void @llvm.amdgcn.struct.ptr.tbuffer.store.v2f32(<2 x float> %vec12, ptr addrspace(8) %arg3, i32 %arg1, i32 280, i32 %arg2, i32 64, i32 3)
call void @llvm.amdgcn.exp.f32(i32 0, i32 0, float undef, float undef, float undef, float undef, i1 false, i1 false) call void @llvm.amdgcn.exp.f32(i32 0, i32 0, float poison, float poison, float poison, float poison, i1 false, i1 false)
%load2 = load <6 x float>, ptr addrspace(3) %arg6, align 4 %load2 = load <6 x float>, ptr addrspace(3) %arg6, align 4
%vec21 = shufflevector <6 x float> %load2, <6 x float> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3> %vec21 = shufflevector <6 x float> %load2, <6 x float> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>

6
llvm/test/CodeGen/AMDGPU/loop_exit_with_xor.ll
View File

@ -46,7 +46,7 @@ loop:
br i1 %tmp27, label %then, label %endif br i1 %tmp27, label %then, label %endif
then: ; preds = %bb then: ; preds = %bb
call void @llvm.amdgcn.raw.ptr.buffer.store.f32(float undef, ptr addrspace(8) poison, i32 0, i32 undef, i32 0) call void @llvm.amdgcn.raw.ptr.buffer.store.f32(float poison, ptr addrspace(8) poison, i32 0, i32 undef, i32 0)
br label %endif br label %endif
endif: ; preds = %bb28, %bb endif: ; preds = %bb28, %bb
@ -85,7 +85,7 @@ loop:
%tmp23phi = phi i32 [ %tmp23, %loop ], [ 0, %entry ] %tmp23phi = phi i32 [ %tmp23, %loop ], [ 0, %entry ]
%tmp23 = add nuw i32 %tmp23phi, 1 %tmp23 = add nuw i32 %tmp23phi, 1
%tmp27 = icmp ult i32 %arg, %tmp23 %tmp27 = icmp ult i32 %arg, %tmp23
call void @llvm.amdgcn.raw.ptr.buffer.store.f32(float undef, ptr addrspace(8) poison, i32 0, i32 undef, i32 0) call void @llvm.amdgcn.raw.ptr.buffer.store.f32(float poison, ptr addrspace(8) poison, i32 0, i32 undef, i32 0)
br i1 %tmp27, label %loop, label %loopexit br i1 %tmp27, label %loop, label %loopexit
loopexit: loopexit:
@ -136,7 +136,7 @@ loop:
br i1 %tmp27, label %then, label %endif br i1 %tmp27, label %then, label %endif
then: ; preds = %bb then: ; preds = %bb
call void @llvm.amdgcn.raw.ptr.buffer.store.f32(float undef, ptr addrspace(8) poison, i32 0, i32 undef, i32 0) call void @llvm.amdgcn.raw.ptr.buffer.store.f32(float poison, ptr addrspace(8) poison, i32 0, i32 undef, i32 0)
br label %endif br label %endif
endif: ; preds = %bb28, %bb endif: ; preds = %bb28, %bb

4
llvm/test/CodeGen/AMDGPU/memory_clause.ll
View File

@ -447,7 +447,7 @@ define amdgpu_kernel void @flat_scratch_load(float %a, float %b, <8 x i32> %desc
%val = call <2 x float> @llvm.amdgcn.image.sample.2d.v2f32.f32(i32 9, float %a, float %b, <8 x i32> %desc, <4 x i32> <i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 0>, i1 false, i32 0, i32 0) %val = call <2 x float> @llvm.amdgcn.image.sample.2d.v2f32.f32(i32 9, float %a, float %b, <8 x i32> %desc, <4 x i32> <i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 0>, i1 false, i32 0, i32 0)
%val0 = extractelement <2 x float> %val, i32 0 %val0 = extractelement <2 x float> %val, i32 0
%valadd = fadd float %load, %val0 %valadd = fadd float %load, %val0
call void @llvm.amdgcn.exp.f32(i32 0, i32 1, float %valadd, float undef, float undef, float undef, i1 true, i1 true) call void @llvm.amdgcn.exp.f32(i32 0, i32 1, float %valadd, float poison, float poison, float poison, i1 true, i1 true)
ret void ret void
} }
@ -505,7 +505,7 @@ define amdgpu_kernel void @flat_scratch_load_clause(float %a, float %b, <8 x i32
%load0 = load float, ptr addrspace(5) %alloca %load0 = load float, ptr addrspace(5) %alloca
%load1 = load float, ptr addrspace(5) %alloca2 %load1 = load float, ptr addrspace(5) %alloca2
%valadd = fadd float %load0, %load1 %valadd = fadd float %load0, %load1
call void @llvm.amdgcn.exp.f32(i32 0, i32 1, float %valadd, float undef, float undef, float undef, i1 true, i1 true) call void @llvm.amdgcn.exp.f32(i32 0, i32 1, float %valadd, float poison, float poison, float poison, i1 true, i1 true)
ret void ret void
} }

4
llvm/test/CodeGen/AMDGPU/mixed-wave32-wave64.ll
View File

@ -12,8 +12,8 @@ define amdgpu_hs void @_amdgpu_hs_main() #0 {
define amdgpu_ps void @_amdgpu_ps_main(i32 %arg) local_unnamed_addr #1 { define amdgpu_ps void @_amdgpu_ps_main(i32 %arg) local_unnamed_addr #1 {
.entry: .entry:
%tmp = tail call float @llvm.amdgcn.interp.p2(float undef, float undef, i32 1, i32 0, i32 %arg) #2 %tmp = tail call float @llvm.amdgcn.interp.p2(float poison, float poison, i32 1, i32 0, i32 %arg) #2
%tmp1 = tail call float @llvm.amdgcn.image.sample.2d.f32.f32(i32 1, float undef, float %tmp, <8 x i32> poison, <4 x i32> poison, i1 false, i32 0, i32 0) %tmp1 = tail call float @llvm.amdgcn.image.sample.2d.f32.f32(i32 1, float poison, float %tmp, <8 x i32> poison, <4 x i32> poison, i1 false, i32 0, i32 0)
%tmp2 = fcmp olt float %tmp1, 5.000000e-01 %tmp2 = fcmp olt float %tmp1, 5.000000e-01
br i1 %tmp2, label %bb, label %l br i1 %tmp2, label %bb, label %l

2
llvm/test/CodeGen/AMDGPU/rename-disconnected-bug.ll
View File

@ -11,7 +11,7 @@ B1:
br label %B2 br label %B2
B2: B2:
%v0 = phi <4 x float> [ zeroinitializer, %B1 ], [ <float 0.0, float 0.0, float 0.0, float undef>, %B0 ] %v0 = phi <4 x float> [ zeroinitializer, %B1 ], [ <float 0.0, float 0.0, float 0.0, float poison>, %B0 ]
br i1 %c1, label %B20.1, label %B20.2 br i1 %c1, label %B20.1, label %B20.2
B20.1: B20.1:

2
llvm/test/CodeGen/AMDGPU/ret.ll
View File

@ -244,7 +244,7 @@ bb:
; GCN-LABEL: {{^}}ret_return_to_epilog_pseudo_size: ; GCN-LABEL: {{^}}ret_return_to_epilog_pseudo_size:
; GCN: codeLenInByte = 0{{$}} ; GCN: codeLenInByte = 0{{$}}
define amdgpu_ps float @ret_return_to_epilog_pseudo_size() #0 { define amdgpu_ps float @ret_return_to_epilog_pseudo_size() #0 {
ret float undef ret float poison
} }
declare void @llvm.amdgcn.exp.f32(i32, i32, float, float, float, float, i1, i1) #0 declare void @llvm.amdgcn.exp.f32(i32, i32, float, float, float, float, i1, i1) #0

2
llvm/test/CodeGen/AMDGPU/scalar-store-cache-flush.mir
View File

@ -40,7 +40,7 @@
} }
define amdgpu_ps float @si_return() { define amdgpu_ps float @si_return() {
ret float undef ret float poison
} }
... ...

8
llvm/test/CodeGen/AMDGPU/sched-crash-dbg-value.mir
View File

@ -101,12 +101,12 @@
%tmp = fmul fast float %tmp67, undef %tmp = fmul fast float %tmp67, undef
%tmp71 = fsub fast float %tmp, %tmp70 %tmp71 = fsub fast float %tmp, %tmp70
%tmp73 = fadd fast float %tmp, undef %tmp73 = fadd fast float %tmp, undef
%tmp74 = insertelement <4 x float> <float undef, float undef, float undef, float 0.000000e+00>, float %tmp69, i32 0 %tmp74 = insertelement <4 x float> <float poison, float poison, float poison, float 0.000000e+00>, float %tmp69, i32 0
%tmp75 = insertelement <4 x float> %tmp74, float %tmp71, i32 1 %tmp75 = insertelement <4 x float> %tmp74, float %tmp71, i32 1
%tmp76 = insertelement <4 x float> %tmp75, float %tmp73, i32 2 %tmp76 = insertelement <4 x float> %tmp75, float %tmp73, i32 2
store <4 x float> %tmp76, ptr addrspace(5) %tmp24, align 16 store <4 x float> %tmp76, ptr addrspace(5) %tmp24, align 16
%tmp77 = fsub float undef, %tmp60 %tmp77 = fsub float poison, %tmp60
%tmp78 = fsub float undef, %tmp61 %tmp78 = fsub float poison, %tmp61
%tmp79 = extractelement <4 x float> %tmp66, i32 2 %tmp79 = extractelement <4 x float> %tmp66, i32 2
%tmp80 = extractelement <4 x float> %tmp59, i32 2 %tmp80 = extractelement <4 x float> %tmp59, i32 2
%tmp81 = fsub float %tmp79, %tmp80 %tmp81 = fsub float %tmp79, %tmp80
@ -124,7 +124,7 @@
%tmp92 = fsub float %tmp91, %tmp90 %tmp92 = fsub float %tmp91, %tmp90
%tmp93 = fmul float %tmp42, %tmp87 %tmp93 = fmul float %tmp42, %tmp87
%tmp94 = call float @llvm.fmuladd.f32(float %tmp92, float %tmp36, float %tmp93) %tmp94 = call float @llvm.fmuladd.f32(float %tmp92, float %tmp36, float %tmp93)
%tmp95 = call float @llvm.fmuladd.f32(float %tmp48, float undef, float %tmp94) %tmp95 = call float @llvm.fmuladd.f32(float %tmp48, float poison, float %tmp94)
%fmul = fmul <2 x float> undef, undef %fmul = fmul <2 x float> undef, undef
%fadd = fadd <2 x float> %fmul, undef %fadd = fadd <2 x float> %fmul, undef
%extractelement = extractelement <2 x float> %fadd, i64 1 %extractelement = extractelement <2 x float> %fadd, i64 1

28
llvm/test/CodeGen/AMDGPU/scratch-simple.ll
View File

@ -86,8 +86,8 @@
; FLATSCR: scratch_load_dword {{v[0-9]+}}, [[LO_OFF]], off ; FLATSCR: scratch_load_dword {{v[0-9]+}}, [[LO_OFF]], off
; GFX11-FLATSCR: scratch_load_b32 {{v[0-9]+}}, [[CLAMP_IDX]], off{{$}} ; GFX11-FLATSCR: scratch_load_b32 {{v[0-9]+}}, [[CLAMP_IDX]], off{{$}}
define amdgpu_ps float @ps_main(i32 %idx) { define amdgpu_ps float @ps_main(i32 %idx) {
%v1 = extractelement <81 x float> <float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float 0x3FE41CFEA0000000, float 0xBFE7A693C0000000, float 0xBFEA477C60000000, float 0xBFEBE5DC60000000, float 0xBFEC71C720000000, float 0xBFEBE5DC60000000, float 0xBFEA477C60000000, float 0xBFE7A693C0000000, float 0xBFE41CFEA0000000, float 0x3FDF9B13E0000000, float 0x3FDF9B1380000000, float 0x3FD5C53B80000000, float 0x3FD5C53B00000000, float 0x3FC6326AC0000000, float 0x3FC63269E0000000, float 0xBEE05CEB00000000, float 0xBEE086A320000000, float 0xBFC63269E0000000, float 0xBFC6326AC0000000, float 0xBFD5C53B80000000, float 0xBFD5C53B80000000, float 0xBFDF9B13E0000000, float 0xBFDF9B1460000000, float 0xBFE41CFE80000000, float 0x3FE7A693C0000000, float 0x3FEA477C20000000, float 0x3FEBE5DC40000000, float 0x3FEC71C6E0000000, float 0x3FEBE5DC40000000, float 0x3FEA477C20000000, float 0x3FE7A693C0000000, float 0xBFE41CFE80000000>, i32 %idx %v1 = extractelement <81 x float> <float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float 0x3FE41CFEA0000000, float 0xBFE7A693C0000000, float 0xBFEA477C60000000, float 0xBFEBE5DC60000000, float 0xBFEC71C720000000, float 0xBFEBE5DC60000000, float 0xBFEA477C60000000, float 0xBFE7A693C0000000, float 0xBFE41CFEA0000000, float 0x3FDF9B13E0000000, float 0x3FDF9B1380000000, float 0x3FD5C53B80000000, float 0x3FD5C53B00000000, float 0x3FC6326AC0000000, float 0x3FC63269E0000000, float 0xBEE05CEB00000000, float 0xBEE086A320000000, float 0xBFC63269E0000000, float 0xBFC6326AC0000000, float 0xBFD5C53B80000000, float 0xBFD5C53B80000000, float 0xBFDF9B13E0000000, float 0xBFDF9B1460000000, float 0xBFE41CFE80000000, float 0x3FE7A693C0000000, float 0x3FEA477C20000000, float 0x3FEBE5DC40000000, float 0x3FEC71C6E0000000, float 0x3FEBE5DC40000000, float 0x3FEA477C20000000, float 0x3FE7A693C0000000, float 0xBFE41CFE80000000>, i32 %idx
%v2 = extractelement <81 x float> <float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float 0xBFE41CFEA0000000, float 0xBFDF9B13E0000000, float 0xBFD5C53B80000000, float 0xBFC6326AC0000000, float 0x3EE0789320000000, float 0x3FC6326AC0000000, float 0x3FD5C53B80000000, float 0x3FDF9B13E0000000, float 0x3FE41CFEA0000000, float 0xBFE7A693C0000000, float 0x3FE7A693C0000000, float 0xBFEA477C20000000, float 0x3FEA477C20000000, float 0xBFEBE5DC40000000, float 0x3FEBE5DC40000000, float 0xBFEC71C720000000, float 0x3FEC71C6E0000000, float 0xBFEBE5DC60000000, float 0x3FEBE5DC40000000, float 0xBFEA477C20000000, float 0x3FEA477C20000000, float 0xBFE7A693C0000000, float 0x3FE7A69380000000, float 0xBFE41CFEA0000000, float 0xBFDF9B13E0000000, float 0xBFD5C53B80000000, float 0xBFC6326AC0000000, float 0x3EE0789320000000, float 0x3FC6326AC0000000, float 0x3FD5C53B80000000, float 0x3FDF9B13E0000000, float 0x3FE41CFE80000000>, i32 %idx %v2 = extractelement <81 x float> <float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float 0xBFE41CFEA0000000, float 0xBFDF9B13E0000000, float 0xBFD5C53B80000000, float 0xBFC6326AC0000000, float 0x3EE0789320000000, float 0x3FC6326AC0000000, float 0x3FD5C53B80000000, float 0x3FDF9B13E0000000, float 0x3FE41CFEA0000000, float 0xBFE7A693C0000000, float 0x3FE7A693C0000000, float 0xBFEA477C20000000, float 0x3FEA477C20000000, float 0xBFEBE5DC40000000, float 0x3FEBE5DC40000000, float 0xBFEC71C720000000, float 0x3FEC71C6E0000000, float 0xBFEBE5DC60000000, float 0x3FEBE5DC40000000, float 0xBFEA477C20000000, float 0x3FEA477C20000000, float 0xBFE7A693C0000000, float 0x3FE7A69380000000, float 0xBFE41CFEA0000000, float 0xBFDF9B13E0000000, float 0xBFD5C53B80000000, float 0xBFC6326AC0000000, float 0x3EE0789320000000, float 0x3FC6326AC0000000, float 0x3FD5C53B80000000, float 0x3FDF9B13E0000000, float 0x3FE41CFE80000000>, i32 %idx
%r = fadd float %v1, %v2 %r = fadd float %v1, %v2
ret float %r ret float %r
} }
@ -139,8 +139,8 @@ define amdgpu_ps float @ps_main(i32 %idx) {
; GFX11-FLATSCR: scratch_load_b32 {{v[0-9]+}}, {{v[0-9]+}}, off ; GFX11-FLATSCR: scratch_load_b32 {{v[0-9]+}}, {{v[0-9]+}}, off
define amdgpu_vs float @vs_main(i32 %idx) { define amdgpu_vs float @vs_main(i32 %idx) {
%v1 = extractelement <81 x float> <float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float 0x3FE41CFEA0000000, float 0xBFE7A693C0000000, float 0xBFEA477C60000000, float 0xBFEBE5DC60000000, float 0xBFEC71C720000000, float 0xBFEBE5DC60000000, float 0xBFEA477C60000000, float 0xBFE7A693C0000000, float 0xBFE41CFEA0000000, float 0x3FDF9B13E0000000, float 0x3FDF9B1380000000, float 0x3FD5C53B80000000, float 0x3FD5C53B00000000, float 0x3FC6326AC0000000, float 0x3FC63269E0000000, float 0xBEE05CEB00000000, float 0xBEE086A320000000, float 0xBFC63269E0000000, float 0xBFC6326AC0000000, float 0xBFD5C53B80000000, float 0xBFD5C53B80000000, float 0xBFDF9B13E0000000, float 0xBFDF9B1460000000, float 0xBFE41CFE80000000, float 0x3FE7A693C0000000, float 0x3FEA477C20000000, float 0x3FEBE5DC40000000, float 0x3FEC71C6E0000000, float 0x3FEBE5DC40000000, float 0x3FEA477C20000000, float 0x3FE7A693C0000000, float 0xBFE41CFE80000000>, i32 %idx %v1 = extractelement <81 x float> <float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float 0x3FE41CFEA0000000, float 0xBFE7A693C0000000, float 0xBFEA477C60000000, float 0xBFEBE5DC60000000, float 0xBFEC71C720000000, float 0xBFEBE5DC60000000, float 0xBFEA477C60000000, float 0xBFE7A693C0000000, float 0xBFE41CFEA0000000, float 0x3FDF9B13E0000000, float 0x3FDF9B1380000000, float 0x3FD5C53B80000000, float 0x3FD5C53B00000000, float 0x3FC6326AC0000000, float 0x3FC63269E0000000, float 0xBEE05CEB00000000, float 0xBEE086A320000000, float 0xBFC63269E0000000, float 0xBFC6326AC0000000, float 0xBFD5C53B80000000, float 0xBFD5C53B80000000, float 0xBFDF9B13E0000000, float 0xBFDF9B1460000000, float 0xBFE41CFE80000000, float 0x3FE7A693C0000000, float 0x3FEA477C20000000, float 0x3FEBE5DC40000000, float 0x3FEC71C6E0000000, float 0x3FEBE5DC40000000, float 0x3FEA477C20000000, float 0x3FE7A693C0000000, float 0xBFE41CFE80000000>, i32 %idx
%v2 = extractelement <81 x float> <float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float 0xBFE41CFEA0000000, float 0xBFDF9B13E0000000, float 0xBFD5C53B80000000, float 0xBFC6326AC0000000, float 0x3EE0789320000000, float 0x3FC6326AC0000000, float 0x3FD5C53B80000000, float 0x3FDF9B13E0000000, float 0x3FE41CFEA0000000, float 0xBFE7A693C0000000, float 0x3FE7A693C0000000, float 0xBFEA477C20000000, float 0x3FEA477C20000000, float 0xBFEBE5DC40000000, float 0x3FEBE5DC40000000, float 0xBFEC71C720000000, float 0x3FEC71C6E0000000, float 0xBFEBE5DC60000000, float 0x3FEBE5DC40000000, float 0xBFEA477C20000000, float 0x3FEA477C20000000, float 0xBFE7A693C0000000, float 0x3FE7A69380000000, float 0xBFE41CFEA0000000, float 0xBFDF9B13E0000000, float 0xBFD5C53B80000000, float 0xBFC6326AC0000000, float 0x3EE0789320000000, float 0x3FC6326AC0000000, float 0x3FD5C53B80000000, float 0x3FDF9B13E0000000, float 0x3FE41CFE80000000>, i32 %idx %v2 = extractelement <81 x float> <float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float 0xBFE41CFEA0000000, float 0xBFDF9B13E0000000, float 0xBFD5C53B80000000, float 0xBFC6326AC0000000, float 0x3EE0789320000000, float 0x3FC6326AC0000000, float 0x3FD5C53B80000000, float 0x3FDF9B13E0000000, float 0x3FE41CFEA0000000, float 0xBFE7A693C0000000, float 0x3FE7A693C0000000, float 0xBFEA477C20000000, float 0x3FEA477C20000000, float 0xBFEBE5DC40000000, float 0x3FEBE5DC40000000, float 0xBFEC71C720000000, float 0x3FEC71C6E0000000, float 0xBFEBE5DC60000000, float 0x3FEBE5DC40000000, float 0xBFEA477C20000000, float 0x3FEA477C20000000, float 0xBFE7A693C0000000, float 0x3FE7A69380000000, float 0xBFE41CFEA0000000, float 0xBFDF9B13E0000000, float 0xBFD5C53B80000000, float 0xBFC6326AC0000000, float 0x3EE0789320000000, float 0x3FC6326AC0000000, float 0x3FD5C53B80000000, float 0x3FDF9B13E0000000, float 0x3FE41CFE80000000>, i32 %idx
%r = fadd float %v1, %v2 %r = fadd float %v1, %v2
ret float %r ret float %r
} }
@ -189,8 +189,8 @@ define amdgpu_vs float @vs_main(i32 %idx) {
; GFX11-FLATSCR: scratch_load_b32 {{v[0-9]+}}, {{v[0-9]+}}, off ; GFX11-FLATSCR: scratch_load_b32 {{v[0-9]+}}, {{v[0-9]+}}, off
define amdgpu_cs float @cs_main(i32 %idx) { define amdgpu_cs float @cs_main(i32 %idx) {
%v1 = extractelement <81 x float> <float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float 0x3FE41CFEA0000000, float 0xBFE7A693C0000000, float 0xBFEA477C60000000, float 0xBFEBE5DC60000000, float 0xBFEC71C720000000, float 0xBFEBE5DC60000000, float 0xBFEA477C60000000, float 0xBFE7A693C0000000, float 0xBFE41CFEA0000000, float 0x3FDF9B13E0000000, float 0x3FDF9B1380000000, float 0x3FD5C53B80000000, float 0x3FD5C53B00000000, float 0x3FC6326AC0000000, float 0x3FC63269E0000000, float 0xBEE05CEB00000000, float 0xBEE086A320000000, float 0xBFC63269E0000000, float 0xBFC6326AC0000000, float 0xBFD5C53B80000000, float 0xBFD5C53B80000000, float 0xBFDF9B13E0000000, float 0xBFDF9B1460000000, float 0xBFE41CFE80000000, float 0x3FE7A693C0000000, float 0x3FEA477C20000000, float 0x3FEBE5DC40000000, float 0x3FEC71C6E0000000, float 0x3FEBE5DC40000000, float 0x3FEA477C20000000, float 0x3FE7A693C0000000, float 0xBFE41CFE80000000>, i32 %idx %v1 = extractelement <81 x float> <float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float 0x3FE41CFEA0000000, float 0xBFE7A693C0000000, float 0xBFEA477C60000000, float 0xBFEBE5DC60000000, float 0xBFEC71C720000000, float 0xBFEBE5DC60000000, float 0xBFEA477C60000000, float 0xBFE7A693C0000000, float 0xBFE41CFEA0000000, float 0x3FDF9B13E0000000, float 0x3FDF9B1380000000, float 0x3FD5C53B80000000, float 0x3FD5C53B00000000, float 0x3FC6326AC0000000, float 0x3FC63269E0000000, float 0xBEE05CEB00000000, float 0xBEE086A320000000, float 0xBFC63269E0000000, float 0xBFC6326AC0000000, float 0xBFD5C53B80000000, float 0xBFD5C53B80000000, float 0xBFDF9B13E0000000, float 0xBFDF9B1460000000, float 0xBFE41CFE80000000, float 0x3FE7A693C0000000, float 0x3FEA477C20000000, float 0x3FEBE5DC40000000, float 0x3FEC71C6E0000000, float 0x3FEBE5DC40000000, float 0x3FEA477C20000000, float 0x3FE7A693C0000000, float 0xBFE41CFE80000000>, i32 %idx
%v2 = extractelement <81 x float> <float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float 0xBFE41CFEA0000000, float 0xBFDF9B13E0000000, float 0xBFD5C53B80000000, float 0xBFC6326AC0000000, float 0x3EE0789320000000, float 0x3FC6326AC0000000, float 0x3FD5C53B80000000, float 0x3FDF9B13E0000000, float 0x3FE41CFEA0000000, float 0xBFE7A693C0000000, float 0x3FE7A693C0000000, float 0xBFEA477C20000000, float 0x3FEA477C20000000, float 0xBFEBE5DC40000000, float 0x3FEBE5DC40000000, float 0xBFEC71C720000000, float 0x3FEC71C6E0000000, float 0xBFEBE5DC60000000, float 0x3FEBE5DC40000000, float 0xBFEA477C20000000, float 0x3FEA477C20000000, float 0xBFE7A693C0000000, float 0x3FE7A69380000000, float 0xBFE41CFEA0000000, float 0xBFDF9B13E0000000, float 0xBFD5C53B80000000, float 0xBFC6326AC0000000, float 0x3EE0789320000000, float 0x3FC6326AC0000000, float 0x3FD5C53B80000000, float 0x3FDF9B13E0000000, float 0x3FE41CFE80000000>, i32 %idx %v2 = extractelement <81 x float> <float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float 0xBFE41CFEA0000000, float 0xBFDF9B13E0000000, float 0xBFD5C53B80000000, float 0xBFC6326AC0000000, float 0x3EE0789320000000, float 0x3FC6326AC0000000, float 0x3FD5C53B80000000, float 0x3FDF9B13E0000000, float 0x3FE41CFEA0000000, float 0xBFE7A693C0000000, float 0x3FE7A693C0000000, float 0xBFEA477C20000000, float 0x3FEA477C20000000, float 0xBFEBE5DC40000000, float 0x3FEBE5DC40000000, float 0xBFEC71C720000000, float 0x3FEC71C6E0000000, float 0xBFEBE5DC60000000, float 0x3FEBE5DC40000000, float 0xBFEA477C20000000, float 0x3FEA477C20000000, float 0xBFE7A693C0000000, float 0x3FE7A69380000000, float 0xBFE41CFEA0000000, float 0xBFDF9B13E0000000, float 0xBFD5C53B80000000, float 0xBFC6326AC0000000, float 0x3EE0789320000000, float 0x3FC6326AC0000000, float 0x3FD5C53B80000000, float 0x3FDF9B13E0000000, float 0x3FE41CFE80000000>, i32 %idx
%r = fadd float %v1, %v2 %r = fadd float %v1, %v2
ret float %r ret float %r
} }
@ -221,8 +221,8 @@ define amdgpu_cs float @cs_main(i32 %idx) {
; GFX11-FLATSCR: scratch_load_b32 {{v[0-9]+}}, {{v[0-9]+}}, off ; GFX11-FLATSCR: scratch_load_b32 {{v[0-9]+}}, {{v[0-9]+}}, off
; GFX11-FLATSCR: scratch_load_b32 {{v[0-9]+}}, {{v[0-9]+}}, off ; GFX11-FLATSCR: scratch_load_b32 {{v[0-9]+}}, {{v[0-9]+}}, off
define amdgpu_hs float @hs_main(i32 %idx) { define amdgpu_hs float @hs_main(i32 %idx) {
%v1 = extractelement <81 x float> <float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float 0x3FE41CFEA0000000, float 0xBFE7A693C0000000, float 0xBFEA477C60000000, float 0xBFEBE5DC60000000, float 0xBFEC71C720000000, float 0xBFEBE5DC60000000, float 0xBFEA477C60000000, float 0xBFE7A693C0000000, float 0xBFE41CFEA0000000, float 0x3FDF9B13E0000000, float 0x3FDF9B1380000000, float 0x3FD5C53B80000000, float 0x3FD5C53B00000000, float 0x3FC6326AC0000000, float 0x3FC63269E0000000, float 0xBEE05CEB00000000, float 0xBEE086A320000000, float 0xBFC63269E0000000, float 0xBFC6326AC0000000, float 0xBFD5C53B80000000, float 0xBFD5C53B80000000, float 0xBFDF9B13E0000000, float 0xBFDF9B1460000000, float 0xBFE41CFE80000000, float 0x3FE7A693C0000000, float 0x3FEA477C20000000, float 0x3FEBE5DC40000000, float 0x3FEC71C6E0000000, float 0x3FEBE5DC40000000, float 0x3FEA477C20000000, float 0x3FE7A693C0000000, float 0xBFE41CFE80000000>, i32 %idx %v1 = extractelement <81 x float> <float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float 0x3FE41CFEA0000000, float 0xBFE7A693C0000000, float 0xBFEA477C60000000, float 0xBFEBE5DC60000000, float 0xBFEC71C720000000, float 0xBFEBE5DC60000000, float 0xBFEA477C60000000, float 0xBFE7A693C0000000, float 0xBFE41CFEA0000000, float 0x3FDF9B13E0000000, float 0x3FDF9B1380000000, float 0x3FD5C53B80000000, float 0x3FD5C53B00000000, float 0x3FC6326AC0000000, float 0x3FC63269E0000000, float 0xBEE05CEB00000000, float 0xBEE086A320000000, float 0xBFC63269E0000000, float 0xBFC6326AC0000000, float 0xBFD5C53B80000000, float 0xBFD5C53B80000000, float 0xBFDF9B13E0000000, float 0xBFDF9B1460000000, float 0xBFE41CFE80000000, float 0x3FE7A693C0000000, float 0x3FEA477C20000000, float 0x3FEBE5DC40000000, float 0x3FEC71C6E0000000, float 0x3FEBE5DC40000000, float 0x3FEA477C20000000, float 0x3FE7A693C0000000, float 0xBFE41CFE80000000>, i32 %idx
%v2 = extractelement <81 x float> <float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float 0xBFE41CFEA0000000, float 0xBFDF9B13E0000000, float 0xBFD5C53B80000000, float 0xBFC6326AC0000000, float 0x3EE0789320000000, float 0x3FC6326AC0000000, float 0x3FD5C53B80000000, float 0x3FDF9B13E0000000, float 0x3FE41CFEA0000000, float 0xBFE7A693C0000000, float 0x3FE7A693C0000000, float 0xBFEA477C20000000, float 0x3FEA477C20000000, float 0xBFEBE5DC40000000, float 0x3FEBE5DC40000000, float 0xBFEC71C720000000, float 0x3FEC71C6E0000000, float 0xBFEBE5DC60000000, float 0x3FEBE5DC40000000, float 0xBFEA477C20000000, float 0x3FEA477C20000000, float 0xBFE7A693C0000000, float 0x3FE7A69380000000, float 0xBFE41CFEA0000000, float 0xBFDF9B13E0000000, float 0xBFD5C53B80000000, float 0xBFC6326AC0000000, float 0x3EE0789320000000, float 0x3FC6326AC0000000, float 0x3FD5C53B80000000, float 0x3FDF9B13E0000000, float 0x3FE41CFE80000000>, i32 %idx %v2 = extractelement <81 x float> <float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float 0xBFE41CFEA0000000, float 0xBFDF9B13E0000000, float 0xBFD5C53B80000000, float 0xBFC6326AC0000000, float 0x3EE0789320000000, float 0x3FC6326AC0000000, float 0x3FD5C53B80000000, float 0x3FDF9B13E0000000, float 0x3FE41CFEA0000000, float 0xBFE7A693C0000000, float 0x3FE7A693C0000000, float 0xBFEA477C20000000, float 0x3FEA477C20000000, float 0xBFEBE5DC40000000, float 0x3FEBE5DC40000000, float 0xBFEC71C720000000, float 0x3FEC71C6E0000000, float 0xBFEBE5DC60000000, float 0x3FEBE5DC40000000, float 0xBFEA477C20000000, float 0x3FEA477C20000000, float 0xBFE7A693C0000000, float 0x3FE7A69380000000, float 0xBFE41CFEA0000000, float 0xBFDF9B13E0000000, float 0xBFD5C53B80000000, float 0xBFC6326AC0000000, float 0x3EE0789320000000, float 0x3FC6326AC0000000, float 0x3FD5C53B80000000, float 0x3FDF9B13E0000000, float 0x3FE41CFE80000000>, i32 %idx
%r = fadd float %v1, %v2 %r = fadd float %v1, %v2
ret float %r ret float %r
} }
@ -272,8 +272,8 @@ define amdgpu_hs float @hs_main(i32 %idx) {
; GFX11-FLATSCR: scratch_load_b32 {{v[0-9]+}}, {{v[0-9]+}}, off ; GFX11-FLATSCR: scratch_load_b32 {{v[0-9]+}}, {{v[0-9]+}}, off
; GFX11-FLATSCR: scratch_load_b32 {{v[0-9]+}}, {{v[0-9]+}}, off ; GFX11-FLATSCR: scratch_load_b32 {{v[0-9]+}}, {{v[0-9]+}}, off
define amdgpu_gs float @gs_main(i32 %idx) { define amdgpu_gs float @gs_main(i32 %idx) {
%v1 = extractelement <81 x float> <float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float 0x3FE41CFEA0000000, float 0xBFE7A693C0000000, float 0xBFEA477C60000000, float 0xBFEBE5DC60000000, float 0xBFEC71C720000000, float 0xBFEBE5DC60000000, float 0xBFEA477C60000000, float 0xBFE7A693C0000000, float 0xBFE41CFEA0000000, float 0x3FDF9B13E0000000, float 0x3FDF9B1380000000, float 0x3FD5C53B80000000, float 0x3FD5C53B00000000, float 0x3FC6326AC0000000, float 0x3FC63269E0000000, float 0xBEE05CEB00000000, float 0xBEE086A320000000, float 0xBFC63269E0000000, float 0xBFC6326AC0000000, float 0xBFD5C53B80000000, float 0xBFD5C53B80000000, float 0xBFDF9B13E0000000, float 0xBFDF9B1460000000, float 0xBFE41CFE80000000, float 0x3FE7A693C0000000, float 0x3FEA477C20000000, float 0x3FEBE5DC40000000, float 0x3FEC71C6E0000000, float 0x3FEBE5DC40000000, float 0x3FEA477C20000000, float 0x3FE7A693C0000000, float 0xBFE41CFE80000000>, i32 %idx %v1 = extractelement <81 x float> <float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float 0x3FE41CFEA0000000, float 0xBFE7A693C0000000, float 0xBFEA477C60000000, float 0xBFEBE5DC60000000, float 0xBFEC71C720000000, float 0xBFEBE5DC60000000, float 0xBFEA477C60000000, float 0xBFE7A693C0000000, float 0xBFE41CFEA0000000, float 0x3FDF9B13E0000000, float 0x3FDF9B1380000000, float 0x3FD5C53B80000000, float 0x3FD5C53B00000000, float 0x3FC6326AC0000000, float 0x3FC63269E0000000, float 0xBEE05CEB00000000, float 0xBEE086A320000000, float 0xBFC63269E0000000, float 0xBFC6326AC0000000, float 0xBFD5C53B80000000, float 0xBFD5C53B80000000, float 0xBFDF9B13E0000000, float 0xBFDF9B1460000000, float 0xBFE41CFE80000000, float 0x3FE7A693C0000000, float 0x3FEA477C20000000, float 0x3FEBE5DC40000000, float 0x3FEC71C6E0000000, float 0x3FEBE5DC40000000, float 0x3FEA477C20000000, float 0x3FE7A693C0000000, float 0xBFE41CFE80000000>, i32 %idx
%v2 = extractelement <81 x float> <float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float 0xBFE41CFEA0000000, float 0xBFDF9B13E0000000, float 0xBFD5C53B80000000, float 0xBFC6326AC0000000, float 0x3EE0789320000000, float 0x3FC6326AC0000000, float 0x3FD5C53B80000000, float 0x3FDF9B13E0000000, float 0x3FE41CFEA0000000, float 0xBFE7A693C0000000, float 0x3FE7A693C0000000, float 0xBFEA477C20000000, float 0x3FEA477C20000000, float 0xBFEBE5DC40000000, float 0x3FEBE5DC40000000, float 0xBFEC71C720000000, float 0x3FEC71C6E0000000, float 0xBFEBE5DC60000000, float 0x3FEBE5DC40000000, float 0xBFEA477C20000000, float 0x3FEA477C20000000, float 0xBFE7A693C0000000, float 0x3FE7A69380000000, float 0xBFE41CFEA0000000, float 0xBFDF9B13E0000000, float 0xBFD5C53B80000000, float 0xBFC6326AC0000000, float 0x3EE0789320000000, float 0x3FC6326AC0000000, float 0x3FD5C53B80000000, float 0x3FDF9B13E0000000, float 0x3FE41CFE80000000>, i32 %idx %v2 = extractelement <81 x float> <float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float 0xBFE41CFEA0000000, float 0xBFDF9B13E0000000, float 0xBFD5C53B80000000, float 0xBFC6326AC0000000, float 0x3EE0789320000000, float 0x3FC6326AC0000000, float 0x3FD5C53B80000000, float 0x3FDF9B13E0000000, float 0x3FE41CFEA0000000, float 0xBFE7A693C0000000, float 0x3FE7A693C0000000, float 0xBFEA477C20000000, float 0x3FEA477C20000000, float 0xBFEBE5DC40000000, float 0x3FEBE5DC40000000, float 0xBFEC71C720000000, float 0x3FEC71C6E0000000, float 0xBFEBE5DC60000000, float 0x3FEBE5DC40000000, float 0xBFEA477C20000000, float 0x3FEA477C20000000, float 0xBFE7A693C0000000, float 0x3FE7A69380000000, float 0xBFE41CFEA0000000, float 0xBFDF9B13E0000000, float 0xBFD5C53B80000000, float 0xBFC6326AC0000000, float 0x3EE0789320000000, float 0x3FC6326AC0000000, float 0x3FD5C53B80000000, float 0x3FDF9B13E0000000, float 0x3FE41CFE80000000>, i32 %idx
%r = fadd float %v1, %v2 %r = fadd float %v1, %v2
ret float %r ret float %r
} }
@ -331,8 +331,8 @@ define amdgpu_gs float @gs_main(i32 %idx) {
; GFX11-FLATSCR: scratch_load_b32 {{v[0-9]+}}, {{v[0-9]+}}, off ; GFX11-FLATSCR: scratch_load_b32 {{v[0-9]+}}, {{v[0-9]+}}, off
; GFX11-FLATSCR: scratch_load_b32 {{v[0-9]+}}, {{v[0-9]+}}, off ; GFX11-FLATSCR: scratch_load_b32 {{v[0-9]+}}, {{v[0-9]+}}, off
define amdgpu_hs <{i32, i32, i32, float}> @hs_ir_uses_scratch_offset(i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg %swo, i32 %idx) { define amdgpu_hs <{i32, i32, i32, float}> @hs_ir_uses_scratch_offset(i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg %swo, i32 %idx) {
%v1 = extractelement <81 x float> <float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float 0x3FE41CFEA0000000, float 0xBFE7A693C0000000, float 0xBFEA477C60000000, float 0xBFEBE5DC60000000, float 0xBFEC71C720000000, float 0xBFEBE5DC60000000, float 0xBFEA477C60000000, float 0xBFE7A693C0000000, float 0xBFE41CFEA0000000, float 0x3FDF9B13E0000000, float 0x3FDF9B1380000000, float 0x3FD5C53B80000000, float 0x3FD5C53B00000000, float 0x3FC6326AC0000000, float 0x3FC63269E0000000, float 0xBEE05CEB00000000, float 0xBEE086A320000000, float 0xBFC63269E0000000, float 0xBFC6326AC0000000, float 0xBFD5C53B80000000, float 0xBFD5C53B80000000, float 0xBFDF9B13E0000000, float 0xBFDF9B1460000000, float 0xBFE41CFE80000000, float 0x3FE7A693C0000000, float 0x3FEA477C20000000, float 0x3FEBE5DC40000000, float 0x3FEC71C6E0000000, float 0x3FEBE5DC40000000, float 0x3FEA477C20000000, float 0x3FE7A693C0000000, float 0xBFE41CFE80000000>, i32 %idx %v1 = extractelement <81 x float> <float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float 0x3FE41CFEA0000000, float 0xBFE7A693C0000000, float 0xBFEA477C60000000, float 0xBFEBE5DC60000000, float 0xBFEC71C720000000, float 0xBFEBE5DC60000000, float 0xBFEA477C60000000, float 0xBFE7A693C0000000, float 0xBFE41CFEA0000000, float 0x3FDF9B13E0000000, float 0x3FDF9B1380000000, float 0x3FD5C53B80000000, float 0x3FD5C53B00000000, float 0x3FC6326AC0000000, float 0x3FC63269E0000000, float 0xBEE05CEB00000000, float 0xBEE086A320000000, float 0xBFC63269E0000000, float 0xBFC6326AC0000000, float 0xBFD5C53B80000000, float 0xBFD5C53B80000000, float 0xBFDF9B13E0000000, float 0xBFDF9B1460000000, float 0xBFE41CFE80000000, float 0x3FE7A693C0000000, float 0x3FEA477C20000000, float 0x3FEBE5DC40000000, float 0x3FEC71C6E0000000, float 0x3FEBE5DC40000000, float 0x3FEA477C20000000, float 0x3FE7A693C0000000, float 0xBFE41CFE80000000>, i32 %idx
%v2 = extractelement <81 x float> <float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float 0xBFE41CFEA0000000, float 0xBFDF9B13E0000000, float 0xBFD5C53B80000000, float 0xBFC6326AC0000000, float 0x3EE0789320000000, float 0x3FC6326AC0000000, float 0x3FD5C53B80000000, float 0x3FDF9B13E0000000, float 0x3FE41CFEA0000000, float 0xBFE7A693C0000000, float 0x3FE7A693C0000000, float 0xBFEA477C20000000, float 0x3FEA477C20000000, float 0xBFEBE5DC40000000, float 0x3FEBE5DC40000000, float 0xBFEC71C720000000, float 0x3FEC71C6E0000000, float 0xBFEBE5DC60000000, float 0x3FEBE5DC40000000, float 0xBFEA477C20000000, float 0x3FEA477C20000000, float 0xBFE7A693C0000000, float 0x3FE7A69380000000, float 0xBFE41CFEA0000000, float 0xBFDF9B13E0000000, float 0xBFD5C53B80000000, float 0xBFC6326AC0000000, float 0x3EE0789320000000, float 0x3FC6326AC0000000, float 0x3FD5C53B80000000, float 0x3FDF9B13E0000000, float 0x3FE41CFE80000000>, i32 %idx %v2 = extractelement <81 x float> <float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float 0xBFE41CFEA0000000, float 0xBFDF9B13E0000000, float 0xBFD5C53B80000000, float 0xBFC6326AC0000000, float 0x3EE0789320000000, float 0x3FC6326AC0000000, float 0x3FD5C53B80000000, float 0x3FDF9B13E0000000, float 0x3FE41CFEA0000000, float 0xBFE7A693C0000000, float 0x3FE7A693C0000000, float 0xBFEA477C20000000, float 0x3FEA477C20000000, float 0xBFEBE5DC40000000, float 0x3FEBE5DC40000000, float 0xBFEC71C720000000, float 0x3FEC71C6E0000000, float 0xBFEBE5DC60000000, float 0x3FEBE5DC40000000, float 0xBFEA477C20000000, float 0x3FEA477C20000000, float 0xBFE7A693C0000000, float 0x3FE7A69380000000, float 0xBFE41CFEA0000000, float 0xBFDF9B13E0000000, float 0xBFD5C53B80000000, float 0xBFC6326AC0000000, float 0x3EE0789320000000, float 0x3FC6326AC0000000, float 0x3FD5C53B80000000, float 0x3FDF9B13E0000000, float 0x3FE41CFE80000000>, i32 %idx
%f = fadd float %v1, %v2 %f = fadd float %v1, %v2
%r1 = insertvalue <{i32, i32, i32, float}> poison, i32 %swo, 2 %r1 = insertvalue <{i32, i32, i32, float}> poison, i32 %swo, 2
%r2 = insertvalue <{i32, i32, i32, float}> %r1, float %f, 3 %r2 = insertvalue <{i32, i32, i32, float}> %r1, float %f, 3
@ -386,8 +386,8 @@ define amdgpu_hs <{i32, i32, i32, float}> @hs_ir_uses_scratch_offset(i32 inreg,
; GFX11-FLATSCR: scratch_load_b32 {{v[0-9]+}}, {{v[0-9]+}}, off ; GFX11-FLATSCR: scratch_load_b32 {{v[0-9]+}}, {{v[0-9]+}}, off
; GFX11-FLATSCR: scratch_load_b32 {{v[0-9]+}}, {{v[0-9]+}}, off ; GFX11-FLATSCR: scratch_load_b32 {{v[0-9]+}}, {{v[0-9]+}}, off
define amdgpu_gs <{i32, i32, i32, float}> @gs_ir_uses_scratch_offset(i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg %swo, i32 %idx) { define amdgpu_gs <{i32, i32, i32, float}> @gs_ir_uses_scratch_offset(i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg %swo, i32 %idx) {
%v1 = extractelement <81 x float> <float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float 0x3FE41CFEA0000000, float 0xBFE7A693C0000000, float 0xBFEA477C60000000, float 0xBFEBE5DC60000000, float 0xBFEC71C720000000, float 0xBFEBE5DC60000000, float 0xBFEA477C60000000, float 0xBFE7A693C0000000, float 0xBFE41CFEA0000000, float 0x3FDF9B13E0000000, float 0x3FDF9B1380000000, float 0x3FD5C53B80000000, float 0x3FD5C53B00000000, float 0x3FC6326AC0000000, float 0x3FC63269E0000000, float 0xBEE05CEB00000000, float 0xBEE086A320000000, float 0xBFC63269E0000000, float 0xBFC6326AC0000000, float 0xBFD5C53B80000000, float 0xBFD5C53B80000000, float 0xBFDF9B13E0000000, float 0xBFDF9B1460000000, float 0xBFE41CFE80000000, float 0x3FE7A693C0000000, float 0x3FEA477C20000000, float 0x3FEBE5DC40000000, float 0x3FEC71C6E0000000, float 0x3FEBE5DC40000000, float 0x3FEA477C20000000, float 0x3FE7A693C0000000, float 0xBFE41CFE80000000>, i32 %idx %v1 = extractelement <81 x float> <float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float 0x3FE41CFEA0000000, float 0xBFE7A693C0000000, float 0xBFEA477C60000000, float 0xBFEBE5DC60000000, float 0xBFEC71C720000000, float 0xBFEBE5DC60000000, float 0xBFEA477C60000000, float 0xBFE7A693C0000000, float 0xBFE41CFEA0000000, float 0x3FDF9B13E0000000, float 0x3FDF9B1380000000, float 0x3FD5C53B80000000, float 0x3FD5C53B00000000, float 0x3FC6326AC0000000, float 0x3FC63269E0000000, float 0xBEE05CEB00000000, float 0xBEE086A320000000, float 0xBFC63269E0000000, float 0xBFC6326AC0000000, float 0xBFD5C53B80000000, float 0xBFD5C53B80000000, float 0xBFDF9B13E0000000, float 0xBFDF9B1460000000, float 0xBFE41CFE80000000, float 0x3FE7A693C0000000, float 0x3FEA477C20000000, float 0x3FEBE5DC40000000, float 0x3FEC71C6E0000000, float 0x3FEBE5DC40000000, float 0x3FEA477C20000000, float 0x3FE7A693C0000000, float 0xBFE41CFE80000000>, i32 %idx
%v2 = extractelement <81 x float> <float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float 0xBFE41CFEA0000000, float 0xBFDF9B13E0000000, float 0xBFD5C53B80000000, float 0xBFC6326AC0000000, float 0x3EE0789320000000, float 0x3FC6326AC0000000, float 0x3FD5C53B80000000, float 0x3FDF9B13E0000000, float 0x3FE41CFEA0000000, float 0xBFE7A693C0000000, float 0x3FE7A693C0000000, float 0xBFEA477C20000000, float 0x3FEA477C20000000, float 0xBFEBE5DC40000000, float 0x3FEBE5DC40000000, float 0xBFEC71C720000000, float 0x3FEC71C6E0000000, float 0xBFEBE5DC60000000, float 0x3FEBE5DC40000000, float 0xBFEA477C20000000, float 0x3FEA477C20000000, float 0xBFE7A693C0000000, float 0x3FE7A69380000000, float 0xBFE41CFEA0000000, float 0xBFDF9B13E0000000, float 0xBFD5C53B80000000, float 0xBFC6326AC0000000, float 0x3EE0789320000000, float 0x3FC6326AC0000000, float 0x3FD5C53B80000000, float 0x3FDF9B13E0000000, float 0x3FE41CFE80000000>, i32 %idx %v2 = extractelement <81 x float> <float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float 0xBFE41CFEA0000000, float 0xBFDF9B13E0000000, float 0xBFD5C53B80000000, float 0xBFC6326AC0000000, float 0x3EE0789320000000, float 0x3FC6326AC0000000, float 0x3FD5C53B80000000, float 0x3FDF9B13E0000000, float 0x3FE41CFEA0000000, float 0xBFE7A693C0000000, float 0x3FE7A693C0000000, float 0xBFEA477C20000000, float 0x3FEA477C20000000, float 0xBFEBE5DC40000000, float 0x3FEBE5DC40000000, float 0xBFEC71C720000000, float 0x3FEC71C6E0000000, float 0xBFEBE5DC60000000, float 0x3FEBE5DC40000000, float 0xBFEA477C20000000, float 0x3FEA477C20000000, float 0xBFE7A693C0000000, float 0x3FE7A69380000000, float 0xBFE41CFEA0000000, float 0xBFDF9B13E0000000, float 0xBFD5C53B80000000, float 0xBFC6326AC0000000, float 0x3EE0789320000000, float 0x3FC6326AC0000000, float 0x3FD5C53B80000000, float 0x3FDF9B13E0000000, float 0x3FE41CFE80000000>, i32 %idx
%f = fadd float %v1, %v2 %f = fadd float %v1, %v2
%r1 = insertvalue <{i32, i32, i32, float}> poison, i32 %swo, 2 %r1 = insertvalue <{i32, i32, i32, float}> poison, i32 %swo, 2
%r2 = insertvalue <{i32, i32, i32, float}> %r1, float %f, 3 %r2 = insertvalue <{i32, i32, i32, float}> %r1, float %f, 3

8
llvm/test/CodeGen/AMDGPU/select-undef.ll
View File

@ -6,7 +6,7 @@
; GCN-NOT: v_cndmask ; GCN-NOT: v_cndmask
; GCN-NEXT: s_setpc_b64 ; GCN-NEXT: s_setpc_b64
define float @select_undef_lhs(float %val, i1 %cond) { define float @select_undef_lhs(float %val, i1 %cond) {
%sel = select i1 %cond, float undef, float %val %sel = select i1 %cond, float poison, float %val
ret float %sel ret float %sel
} }
@ -16,7 +16,7 @@ define float @select_undef_lhs(float %val, i1 %cond) {
; GCN-NOT: v_cndmask ; GCN-NOT: v_cndmask
; GCN-NEXT: s_setpc_b64 ; GCN-NEXT: s_setpc_b64
define float @select_undef_rhs(float %val, i1 %cond) { define float @select_undef_rhs(float %val, i1 %cond) {
%sel = select i1 %cond, float %val, float undef %sel = select i1 %cond, float %val, float poison
ret float %sel ret float %sel
} }
@ -25,7 +25,7 @@ define float @select_undef_rhs(float %val, i1 %cond) {
; GCN: store_dword {{[^,]+}}, [[RES]] ; GCN: store_dword {{[^,]+}}, [[RES]]
define void @select_undef_n1(ptr addrspace(1) %a, i32 %c) { define void @select_undef_n1(ptr addrspace(1) %a, i32 %c) {
%cc = icmp eq i32 %c, 0 %cc = icmp eq i32 %c, 0
%sel = select i1 %cc, float 1.000000e+00, float undef %sel = select i1 %cc, float 1.000000e+00, float poison
store float %sel, ptr addrspace(1) %a store float %sel, ptr addrspace(1) %a
ret void ret void
} }
@ -35,7 +35,7 @@ define void @select_undef_n1(ptr addrspace(1) %a, i32 %c) {
; GCN: store_dword {{[^,]+}}, [[RES]] ; GCN: store_dword {{[^,]+}}, [[RES]]
define void @select_undef_n2(ptr addrspace(1) %a, i32 %c) { define void @select_undef_n2(ptr addrspace(1) %a, i32 %c) {
%cc = icmp eq i32 %c, 0 %cc = icmp eq i32 %c, 0
%sel = select i1 %cc, float undef, float 1.000000e+00 %sel = select i1 %cc, float poison, float 1.000000e+00
store float %sel, ptr addrspace(1) %a store float %sel, ptr addrspace(1) %a
ret void ret void
} }

4
llvm/test/CodeGen/AMDGPU/sgpr-copy.ll
View File

@ -370,7 +370,7 @@ bb:
%tmp8 = load <8 x i32>, ptr addrspace(4) %tmp7, align 32, !tbaa !0 %tmp8 = load <8 x i32>, ptr addrspace(4) %tmp7, align 32, !tbaa !0
%tmp = call <4 x float> @llvm.amdgcn.image.sample.2d.v4f32.f32(i32 15, float 7.500000e-01, float 2.500000e-01, <8 x i32> %tmp8, <4 x i32> poison, i1 0, i32 0, i32 0) %tmp = call <4 x float> @llvm.amdgcn.image.sample.2d.v4f32.f32(i32 15, float 7.500000e-01, float 2.500000e-01, <8 x i32> %tmp8, <4 x i32> poison, i1 0, i32 0, i32 0)
%tmp10 = extractelement <4 x float> %tmp, i32 0 %tmp10 = extractelement <4 x float> %tmp, i32 0
%tmp12 = call <2 x half> @llvm.amdgcn.cvt.pkrtz(float undef, float %tmp10) %tmp12 = call <2 x half> @llvm.amdgcn.cvt.pkrtz(float poison, float %tmp10)
call void @llvm.amdgcn.exp.compr.v2f16(i32 0, i32 15, <2 x half> %tmp12, <2 x half> undef, i1 true, i1 true) #0 call void @llvm.amdgcn.exp.compr.v2f16(i32 0, i32 15, <2 x half> %tmp12, <2 x half> undef, i1 true, i1 true) #0
ret void ret void
} }
@ -385,7 +385,7 @@ bb:
%tmp8 = load <4 x i32>, ptr addrspace(4) %tmp7, align 16, !tbaa !0 %tmp8 = load <4 x i32>, ptr addrspace(4) %tmp7, align 16, !tbaa !0
%tmp = call <4 x float> @llvm.amdgcn.image.sample.2d.v4f32.f32(i32 15, float 7.500000e-01, float 2.500000e-01, <8 x i32> poison, <4 x i32> %tmp8, i1 0, i32 0, i32 0) %tmp = call <4 x float> @llvm.amdgcn.image.sample.2d.v4f32.f32(i32 15, float 7.500000e-01, float 2.500000e-01, <8 x i32> poison, <4 x i32> %tmp8, i1 0, i32 0, i32 0)
%tmp10 = extractelement <4 x float> %tmp, i32 0 %tmp10 = extractelement <4 x float> %tmp, i32 0
%tmp12 = call <2 x half> @llvm.amdgcn.cvt.pkrtz(float %tmp10, float undef) %tmp12 = call <2 x half> @llvm.amdgcn.cvt.pkrtz(float %tmp10, float poison)
call void @llvm.amdgcn.exp.compr.v2f16(i32 0, i32 15, <2 x half> %tmp12, <2 x half> undef, i1 true, i1 true) #0 call void @llvm.amdgcn.exp.compr.v2f16(i32 0, i32 15, <2 x half> %tmp12, <2 x half> undef, i1 true, i1 true) #0
ret void ret void
} }

54
llvm/test/CodeGen/AMDGPU/si-spill-cf.ll
View File

@ -90,7 +90,7 @@ ENDLOOP: ; preds = %ELSE2566, %LOOP
%one.sub.ac.i = fmul float %one.sub.a.i, undef %one.sub.ac.i = fmul float %one.sub.a.i, undef
%fmul = fmul float undef, undef %fmul = fmul float undef, undef
%result.i = fadd float %fmul, %one.sub.ac.i %result.i = fadd float %fmul, %one.sub.ac.i
call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float undef, float %result.i, float undef, float 1.000000e+00, i1 true, i1 true) #0 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float poison, float %result.i, float undef, float 1.000000e+00, i1 true, i1 true) #0
ret void ret void
ENDIF: ; preds = %LOOP ENDIF: ; preds = %LOOP
@ -107,9 +107,9 @@ ENDIF: ; preds = %LOOP
%tmp78 = call float @llvm.minnum.f32(float %tmp73, float %tmp77) %tmp78 = call float @llvm.minnum.f32(float %tmp73, float %tmp77)
%tmp79 = call float @llvm.maxnum.f32(float %tmp71, float 0.000000e+00) %tmp79 = call float @llvm.maxnum.f32(float %tmp71, float 0.000000e+00)
%tmp80 = call float @llvm.maxnum.f32(float %tmp72, float %tmp76) %tmp80 = call float @llvm.maxnum.f32(float %tmp72, float %tmp76)
%tmp81 = call float @llvm.maxnum.f32(float undef, float %tmp78) %tmp81 = call float @llvm.maxnum.f32(float poison, float %tmp78)
%tmp82 = call float @llvm.minnum.f32(float %tmp79, float %tmp80) %tmp82 = call float @llvm.minnum.f32(float %tmp79, float %tmp80)
%tmp83 = call float @llvm.minnum.f32(float %tmp82, float undef) %tmp83 = call float @llvm.minnum.f32(float %tmp82, float poison)
%tmp84 = fsub float %tmp14, undef %tmp84 = fsub float %tmp14, undef
%tmp85 = fsub float %tmp15, undef %tmp85 = fsub float %tmp15, undef
%tmp86 = fsub float %tmp16, undef %tmp86 = fsub float %tmp16, undef
@ -125,19 +125,19 @@ ENDIF: ; preds = %LOOP
%tmp96 = call float @llvm.minnum.f32(float %tmp88, float %tmp94) %tmp96 = call float @llvm.minnum.f32(float %tmp88, float %tmp94)
%tmp97 = call float @llvm.maxnum.f32(float %tmp87, float %tmp93) %tmp97 = call float @llvm.maxnum.f32(float %tmp87, float %tmp93)
%tmp98 = call float @llvm.maxnum.f32(float %tmp89, float %tmp95) %tmp98 = call float @llvm.maxnum.f32(float %tmp89, float %tmp95)
%tmp99 = call float @llvm.maxnum.f32(float undef, float %tmp96) %tmp99 = call float @llvm.maxnum.f32(float poison, float %tmp96)
%tmp100 = call float @llvm.maxnum.f32(float %tmp99, float undef) %tmp100 = call float @llvm.maxnum.f32(float %tmp99, float poison)
%tmp101 = call float @llvm.minnum.f32(float %tmp97, float undef) %tmp101 = call float @llvm.minnum.f32(float %tmp97, float poison)
%tmp102 = call float @llvm.minnum.f32(float %tmp101, float %tmp98) %tmp102 = call float @llvm.minnum.f32(float %tmp101, float %tmp98)
%tmp103 = fsub float %tmp30, undef %tmp103 = fsub float %tmp30, undef
%tmp104 = fsub float %tmp31, undef %tmp104 = fsub float %tmp31, undef
%tmp105 = fmul float %tmp103, 0.000000e+00 %tmp105 = fmul float %tmp103, 0.000000e+00
%tmp106 = fmul float %tmp104, 0.000000e+00 %tmp106 = fmul float %tmp104, 0.000000e+00
%tmp107 = call float @llvm.minnum.f32(float undef, float %tmp105) %tmp107 = call float @llvm.minnum.f32(float poison, float %tmp105)
%tmp108 = call float @llvm.maxnum.f32(float undef, float %tmp106) %tmp108 = call float @llvm.maxnum.f32(float poison, float %tmp106)
%tmp109 = call float @llvm.maxnum.f32(float undef, float %tmp107) %tmp109 = call float @llvm.maxnum.f32(float poison, float %tmp107)
%tmp110 = call float @llvm.maxnum.f32(float %tmp109, float undef) %tmp110 = call float @llvm.maxnum.f32(float %tmp109, float poison)
%tmp111 = call float @llvm.minnum.f32(float undef, float %tmp108) %tmp111 = call float @llvm.minnum.f32(float poison, float %tmp108)
%tmp112 = fsub float %tmp32, undef %tmp112 = fsub float %tmp32, undef
%tmp113 = fsub float %tmp33, undef %tmp113 = fsub float %tmp33, undef
%tmp114 = fsub float %tmp34, undef %tmp114 = fsub float %tmp34, undef
@ -219,18 +219,18 @@ ENDIF: ; preds = %LOOP
%tmp190 = fmul float %tmp188, undef %tmp190 = fmul float %tmp188, undef
%tmp191 = call float @llvm.maxnum.f32(float %tmp184, float %tmp189) %tmp191 = call float @llvm.maxnum.f32(float %tmp184, float %tmp189)
%tmp192 = call float @llvm.maxnum.f32(float %tmp185, float %tmp190) %tmp192 = call float @llvm.maxnum.f32(float %tmp185, float %tmp190)
%tmp193 = call float @llvm.maxnum.f32(float %tmp186, float undef) %tmp193 = call float @llvm.maxnum.f32(float %tmp186, float poison)
%tmp194 = call float @llvm.minnum.f32(float %tmp191, float %tmp192) %tmp194 = call float @llvm.minnum.f32(float %tmp191, float %tmp192)
%tmp195 = call float @llvm.minnum.f32(float %tmp194, float %tmp193) %tmp195 = call float @llvm.minnum.f32(float %tmp194, float %tmp193)
%.temp292.7 = select i1 undef, float %tmp162, float undef %.temp292.7 = select i1 undef, float %tmp162, float poison
%temp292.9 = select i1 false, float %tmp180, float %.temp292.7 %temp292.9 = select i1 false, float %tmp180, float %.temp292.7
%.temp292.9 = select i1 undef, float undef, float %temp292.9 %.temp292.9 = select i1 undef, float poison, float %temp292.9
%tmp196 = fcmp ogt float undef, 0.000000e+00 %tmp196 = fcmp ogt float undef, 0.000000e+00
%tmp197 = fcmp olt float undef, %tmp195 %tmp197 = fcmp olt float undef, %tmp195
%tmp198 = and i1 %tmp196, %tmp197 %tmp198 = and i1 %tmp196, %tmp197
%tmp199 = fcmp olt float undef, %.temp292.9 %tmp199 = fcmp olt float undef, %.temp292.9
%tmp200 = and i1 %tmp198, %tmp199 %tmp200 = and i1 %tmp198, %tmp199
%temp292.11 = select i1 %tmp200, float undef, float %.temp292.9 %temp292.11 = select i1 %tmp200, float poison, float %.temp292.9
%tid0 = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) %tid0 = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0)
%cmp0 = icmp eq i32 %tid0, 0 %cmp0 = icmp eq i32 %tid0, 0
br i1 %cmp0, label %IF2565, label %ELSE2566 br i1 %cmp0, label %IF2565, label %ELSE2566
@ -251,9 +251,9 @@ ENDIF2564: ; preds = %ENDIF2594, %ENDIF25
%temp18.1 = phi float [ %tmp218, %ENDIF2588 ], [ poison, %ENDIF2594 ] %temp18.1 = phi float [ %tmp218, %ENDIF2588 ], [ poison, %ENDIF2594 ]
%tmp202 = fsub float %tmp5, undef %tmp202 = fsub float %tmp5, undef
%tmp203 = fmul float %tmp202, undef %tmp203 = fmul float %tmp202, undef
%tmp204 = call float @llvm.maxnum.f32(float undef, float %tmp203) %tmp204 = call float @llvm.maxnum.f32(float poison, float %tmp203)
%tmp205 = call float @llvm.minnum.f32(float %tmp204, float undef) %tmp205 = call float @llvm.minnum.f32(float %tmp204, float poison)
%tmp206 = call float @llvm.minnum.f32(float %tmp205, float undef) %tmp206 = call float @llvm.minnum.f32(float %tmp205, float poison)
%tmp207 = fcmp ogt float undef, 0.000000e+00 %tmp207 = fcmp ogt float undef, 0.000000e+00
%tmp208 = fcmp olt float undef, 1.000000e+00 %tmp208 = fcmp olt float undef, 1.000000e+00
%tmp209 = and i1 %tmp207, %tmp208 %tmp209 = and i1 %tmp207, %tmp208
@ -386,8 +386,8 @@ ELSE2797: ; preds = %ENDIF2564
%tmp254 = call float @llvm.minnum.f32(float %tmp245, float %tmp251) %tmp254 = call float @llvm.minnum.f32(float %tmp245, float %tmp251)
%tmp255 = call float @llvm.maxnum.f32(float %tmp246, float %tmp252) %tmp255 = call float @llvm.maxnum.f32(float %tmp246, float %tmp252)
%tmp256 = call float @llvm.maxnum.f32(float %tmp253, float %tmp254) %tmp256 = call float @llvm.maxnum.f32(float %tmp253, float %tmp254)
%tmp257 = call float @llvm.maxnum.f32(float %tmp256, float undef) %tmp257 = call float @llvm.maxnum.f32(float %tmp256, float poison)
%tmp258 = call float @llvm.minnum.f32(float undef, float %tmp255) %tmp258 = call float @llvm.minnum.f32(float poison, float %tmp255)
%tmp259 = fcmp ogt float %tmp257, 0.000000e+00 %tmp259 = fcmp ogt float %tmp257, 0.000000e+00
%tmp260 = fcmp olt float %tmp257, 1.000000e+00 %tmp260 = fcmp olt float %tmp257, 1.000000e+00
%tmp261 = and i1 %tmp259, %tmp260 %tmp261 = and i1 %tmp259, %tmp260
@ -417,9 +417,9 @@ ELSE2803: ; preds = %ELSE2800
%tmp276 = call float @llvm.minnum.f32(float %tmp267, float %tmp273) %tmp276 = call float @llvm.minnum.f32(float %tmp267, float %tmp273)
%tmp277 = call float @llvm.maxnum.f32(float %tmp268, float %tmp274) %tmp277 = call float @llvm.maxnum.f32(float %tmp268, float %tmp274)
%tmp278 = call float @llvm.maxnum.f32(float %tmp269, float %tmp275) %tmp278 = call float @llvm.maxnum.f32(float %tmp269, float %tmp275)
%tmp279 = call float @llvm.maxnum.f32(float %tmp276, float undef) %tmp279 = call float @llvm.maxnum.f32(float %tmp276, float poison)
%tmp280 = call float @llvm.maxnum.f32(float %tmp279, float undef) %tmp280 = call float @llvm.maxnum.f32(float %tmp279, float poison)
%tmp281 = call float @llvm.minnum.f32(float undef, float %tmp277) %tmp281 = call float @llvm.minnum.f32(float poison, float %tmp277)
%tmp282 = call float @llvm.minnum.f32(float %tmp281, float %tmp278) %tmp282 = call float @llvm.minnum.f32(float %tmp281, float %tmp278)
%tmp283 = fcmp ogt float %tmp280, 0.000000e+00 %tmp283 = fcmp ogt float %tmp280, 0.000000e+00
%tmp284 = fcmp olt float %tmp280, 1.000000e+00 %tmp284 = fcmp olt float %tmp280, 1.000000e+00
@ -438,11 +438,11 @@ ELSE2806: ; preds = %ELSE2803
%tmp294 = fsub float %tmp29, undef %tmp294 = fsub float %tmp29, undef
%tmp295 = fmul float %tmp294, undef %tmp295 = fmul float %tmp294, undef
%tmp296 = call float @llvm.minnum.f32(float %tmp291, float %tmp295) %tmp296 = call float @llvm.minnum.f32(float %tmp291, float %tmp295)
%tmp297 = call float @llvm.minnum.f32(float %tmp292, float undef) %tmp297 = call float @llvm.minnum.f32(float %tmp292, float poison)
%tmp298 = call float @llvm.maxnum.f32(float %tmp293, float undef) %tmp298 = call float @llvm.maxnum.f32(float %tmp293, float poison)
%tmp299 = call float @llvm.maxnum.f32(float %tmp296, float %tmp297) %tmp299 = call float @llvm.maxnum.f32(float %tmp296, float %tmp297)
%tmp300 = call float @llvm.maxnum.f32(float %tmp299, float undef) %tmp300 = call float @llvm.maxnum.f32(float %tmp299, float poison)
%tmp301 = call float @llvm.minnum.f32(float undef, float %tmp298) %tmp301 = call float @llvm.minnum.f32(float poison, float %tmp298)
%tmp302 = fcmp ogt float %tmp300, 0.000000e+00 %tmp302 = fcmp ogt float %tmp300, 0.000000e+00
%tmp303 = fcmp olt float %tmp300, 1.000000e+00 %tmp303 = fcmp olt float %tmp300, 1.000000e+00
%tmp304 = and i1 %tmp302, %tmp303 %tmp304 = and i1 %tmp302, %tmp303

4
llvm/test/CodeGen/AMDGPU/simplifydemandedbits-recursion.ll
View File

@ -78,8 +78,8 @@ bb31: ; preds = %bb31, %bb26
%tmp32 = phi i32 [ %tmp9, %bb26 ], [ poison, %bb31 ] %tmp32 = phi i32 [ %tmp9, %bb26 ], [ poison, %bb31 ]
%tmp33 = getelementptr inbounds [462 x float], ptr addrspace(3) @0, i32 0, i32 %tmp32 %tmp33 = getelementptr inbounds [462 x float], ptr addrspace(3) @0, i32 0, i32 %tmp32
%tmp34 = load float, ptr addrspace(3) %tmp33, align 4 %tmp34 = load float, ptr addrspace(3) %tmp33, align 4
%tmp35 = tail call float @llvm.fmuladd.f32(float %tmp34, float undef, float undef) %tmp35 = tail call float @llvm.fmuladd.f32(float %tmp34, float poison, float poison)
%tmp36 = tail call float @llvm.fmuladd.f32(float undef, float undef, float %tmp35) %tmp36 = tail call float @llvm.fmuladd.f32(float poison, float poison, float %tmp35)
br i1 %c5, label %bb30, label %bb31 br i1 %c5, label %bb30, label %bb31
bb37: ; preds = %bb11 bb37: ; preds = %bb11

2
llvm/test/CodeGen/AMDGPU/skip-if-dead.ll
View File

@ -1899,7 +1899,7 @@ latch:
._crit_edge: ._crit_edge:
%tmp = phi i32 [ -1, %.entry ], [ %ctr.next, %latch ] %tmp = phi i32 [ -1, %.entry ], [ %ctr.next, %latch ]
%out = bitcast i32 %tmp to float %out = bitcast i32 %tmp to float
call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %out, float %out, float undef, float undef, i1 true, i1 true) call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %out, float %out, float poison, float poison, i1 true, i1 true)
ret void ret void
} }

4
llvm/test/CodeGen/AMDGPU/smrd.ll
View File

@ -385,7 +385,7 @@ main_body:
%r5 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %desc, i32 28, i32 0) %r5 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %desc, i32 28, i32 0)
%r6 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %desc, i32 32, i32 0) %r6 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %desc, i32 32, i32 0)
call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r1, float %r2, float %r3, float %r4, i1 true, i1 true) #0 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r1, float %r2, float %r3, float %r4, i1 true, i1 true) #0
call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r5, float %r6, float undef, float undef, i1 true, i1 true) #0 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r5, float %r6, float poison, float poison, i1 true, i1 true) #0
ret void ret void
} }
@ -462,7 +462,7 @@ main_body:
%r5 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %desc, i32 %a5, i32 0) %r5 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %desc, i32 %a5, i32 0)
%r6 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %desc, i32 %a6, i32 0) %r6 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %desc, i32 %a6, i32 0)
call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r1, float %r2, float %r3, float %r4, i1 true, i1 true) #0 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r1, float %r2, float %r3, float %r4, i1 true, i1 true) #0
call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r5, float %r6, float undef, float undef, i1 true, i1 true) #0 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r5, float %r6, float poison, float poison, i1 true, i1 true) #0
ret void ret void
} }

2
llvm/test/CodeGen/AMDGPU/split-smrd.ll
View File

@ -23,7 +23,7 @@ bb3: ; preds = %bb
%tmp8 = load <8 x i32>, ptr addrspace(4) %tmp7, align 32, !tbaa !0 %tmp8 = load <8 x i32>, ptr addrspace(4) %tmp7, align 32, !tbaa !0
%tmp9 = call <4 x float> @llvm.amdgcn.image.sample.2d.v4f32.f32(i32 15, float bitcast (i32 1061158912 to float), float bitcast (i32 1048576000 to float), <8 x i32> %tmp8, <4 x i32> poison, i1 0, i32 0, i32 0) %tmp9 = call <4 x float> @llvm.amdgcn.image.sample.2d.v4f32.f32(i32 15, float bitcast (i32 1061158912 to float), float bitcast (i32 1048576000 to float), <8 x i32> %tmp8, <4 x i32> poison, i1 0, i32 0, i32 0)
%tmp10 = extractelement <4 x float> %tmp9, i32 0 %tmp10 = extractelement <4 x float> %tmp9, i32 0
%tmp12 = call <2 x half> @llvm.amdgcn.cvt.pkrtz(float %tmp10, float undef) %tmp12 = call <2 x half> @llvm.amdgcn.cvt.pkrtz(float %tmp10, float poison)
call void @llvm.amdgcn.exp.compr.v2f16(i32 0, i32 15, <2 x half> %tmp12, <2 x half> undef, i1 true, i1 true) #0 call void @llvm.amdgcn.exp.compr.v2f16(i32 0, i32 15, <2 x half> %tmp12, <2 x half> undef, i1 true, i1 true) #0
ret void ret void
} }

2
llvm/test/CodeGen/AMDGPU/subreg-coalescer-crash.ll
View File

@ -65,7 +65,7 @@ bb7: ; preds = %bb6
br label %bb4 br label %bb4
bb9: ; preds = %bb2 bb9: ; preds = %bb2
%tmp10 = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 15, float undef, <8 x i32> poison, <4 x i32> poison, i1 0, i32 0, i32 0) %tmp10 = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 15, float poison, <8 x i32> poison, <4 x i32> poison, i1 0, i32 0, i32 0)
%tmp11 = extractelement <4 x float> %tmp10, i32 1 %tmp11 = extractelement <4 x float> %tmp10, i32 1
%tmp12 = extractelement <4 x float> %tmp10, i32 3 %tmp12 = extractelement <4 x float> %tmp10, i32 3
br label %bb14 br label %bb14

4
llvm/test/CodeGen/AMDGPU/undefined-subreg-liverange.ll
View File

@ -24,7 +24,7 @@ B1:
br label %B2 br label %B2
B2: B2:
%v0 = phi <4 x float> [ zeroinitializer, %B1 ], [ <float 0.0, float 0.0, float 0.0, float undef>, %B0 ] %v0 = phi <4 x float> [ zeroinitializer, %B1 ], [ <float 0.0, float 0.0, float 0.0, float poison>, %B0 ]
br i1 undef, label %B30.1, label %B30.2 br i1 undef, label %B30.1, label %B30.2
B30.1: B30.1:
@ -86,7 +86,7 @@ bb9: ; preds = %bb9, %bb
bb11: ; preds = %bb9 bb11: ; preds = %bb9
store <4 x i32> %tmp2, ptr addrspace(1) poison, align 16 store <4 x i32> %tmp2, ptr addrspace(1) poison, align 16
ret float undef ret float poison
} }
; FIXME: Should be able to remove the undef copies ; FIXME: Should be able to remove the undef copies

10
llvm/test/CodeGen/AMDGPU/unigine-liveness-crash.ll
View File

@ -17,20 +17,20 @@ main_body:
%j.f.i = bitcast i32 %j.i to float %j.f.i = bitcast i32 %j.i to float
%p1.i = call float @llvm.amdgcn.interp.p1(float %i.f.i, i32 3, i32 4, i32 %arg6) #2 %p1.i = call float @llvm.amdgcn.interp.p1(float %i.f.i, i32 3, i32 4, i32 %arg6) #2
%p2.i = call float @llvm.amdgcn.interp.p2(float %p1.i, float %j.f.i, i32 3, i32 4, i32 %arg6) #2 %p2.i = call float @llvm.amdgcn.interp.p2(float %p1.i, float %j.f.i, i32 3, i32 4, i32 %arg6) #2
%tmp23 = call <4 x float> @llvm.amdgcn.image.sample.2d.v4f32.f32(i32 15, float undef, float undef, <8 x i32> poison, <4 x i32> poison, i1 0, i32 0, i32 0) %tmp23 = call <4 x float> @llvm.amdgcn.image.sample.2d.v4f32.f32(i32 15, float poison, float poison, <8 x i32> poison, <4 x i32> poison, i1 0, i32 0, i32 0)
%tmp24 = extractelement <4 x float> %tmp23, i32 3 %tmp24 = extractelement <4 x float> %tmp23, i32 3
%tmp25 = fmul float %tmp24, %tmp24 %tmp25 = fmul float %tmp24, %tmp24
%tmp26 = fmul float %p2.i, %p2.i %tmp26 = fmul float %p2.i, %p2.i
%tmp27 = fadd float %tmp26, %tmp26 %tmp27 = fadd float %tmp26, %tmp26
%tmp32 = call <4 x float> @llvm.amdgcn.image.sample.c.2d.v4f32.f32(i32 15, float %tmp27, float 0.0, float undef, <8 x i32> poison, <4 x i32> poison, i1 0, i32 0, i32 0) %tmp32 = call <4 x float> @llvm.amdgcn.image.sample.c.2d.v4f32.f32(i32 15, float %tmp27, float 0.0, float poison, <8 x i32> poison, <4 x i32> poison, i1 0, i32 0, i32 0)
%tmp33 = extractelement <4 x float> %tmp32, i32 0 %tmp33 = extractelement <4 x float> %tmp32, i32 0
%tmp34 = fadd float %tmp33, %tmp33 %tmp34 = fadd float %tmp33, %tmp33
%tmp35 = fadd float %tmp34, %tmp34 %tmp35 = fadd float %tmp34, %tmp34
%tmp36 = fadd float %tmp35, %tmp35 %tmp36 = fadd float %tmp35, %tmp35
%tmp37 = fadd float %tmp36, %tmp36 %tmp37 = fadd float %tmp36, %tmp36
%tmp38 = fadd float %tmp37, %tmp37 %tmp38 = fadd float %tmp37, %tmp37
%tmp39 = call <4 x float> @llvm.amdgcn.image.sample.2d.v4f32.f32(i32 15, float undef, float undef, <8 x i32> poison, <4 x i32> poison, i1 0, i32 0, i32 0) %tmp39 = call <4 x float> @llvm.amdgcn.image.sample.2d.v4f32.f32(i32 15, float poison, float poison, <8 x i32> poison, <4 x i32> poison, i1 0, i32 0, i32 0)
%tmp40 = extractelement <4 x float> %tmp39, i32 0 %tmp40 = extractelement <4 x float> %tmp39, i32 0
%tmp41 = extractelement <4 x float> %tmp39, i32 1 %tmp41 = extractelement <4 x float> %tmp39, i32 1
%tmp42 = extractelement <4 x float> %tmp39, i32 2 %tmp42 = extractelement <4 x float> %tmp39, i32 2
@ -53,7 +53,7 @@ main_body:
%tmp58 = fadd float %tmp38, %tmp57 %tmp58 = fadd float %tmp38, %tmp57
%tmp59 = fadd float %tmp46, %tmp46 %tmp59 = fadd float %tmp46, %tmp46
%tmp60 = fadd float %tmp47, %tmp47 %tmp60 = fadd float %tmp47, %tmp47
%tmp65 = call <4 x float> @llvm.amdgcn.image.sample.c.2d.v4f32.f32(i32 15, float undef, float %tmp59, float %tmp60, <8 x i32> poison, <4 x i32> poison, i1 0, i32 0, i32 0) %tmp65 = call <4 x float> @llvm.amdgcn.image.sample.c.2d.v4f32.f32(i32 15, float poison, float %tmp59, float %tmp60, <8 x i32> poison, <4 x i32> poison, i1 0, i32 0, i32 0)
%tmp66 = extractelement <4 x float> %tmp65, i32 0 %tmp66 = extractelement <4 x float> %tmp65, i32 0
%tmp67 = fadd float %tmp58, %tmp66 %tmp67 = fadd float %tmp58, %tmp66
%tmp68 = fmul float %tmp67, 1.250000e-01 %tmp68 = fmul float %tmp67, 1.250000e-01
@ -91,7 +91,7 @@ IF29: ; preds = %LOOP
br label %ENDIF25 br label %ENDIF25
ENDIF28: ; preds = %LOOP ENDIF28: ; preds = %LOOP
%tmp87 = call <4 x float> @llvm.amdgcn.image.sample.c.2d.v4f32.f32(i32 15, float %tmp27, float undef, float undef, <8 x i32> poison, <4 x i32> poison, i1 0, i32 0, i32 0) %tmp87 = call <4 x float> @llvm.amdgcn.image.sample.c.2d.v4f32.f32(i32 15, float %tmp27, float poison, float poison, <8 x i32> poison, <4 x i32> poison, i1 0, i32 0, i32 0)
%tmp88 = extractelement <4 x float> %tmp87, i32 0 %tmp88 = extractelement <4 x float> %tmp87, i32 0
%tmp89 = fadd float %tmp88, %tmp88 %tmp89 = fadd float %tmp88, %tmp88
br label %LOOP br label %LOOP

2
llvm/test/CodeGen/AMDGPU/vgpr-descriptor-waterfall-loop-idom-update.ll
View File

@ -76,7 +76,7 @@ entry:
bb0: bb0:
%desc = load ptr addrspace(8), ptr %arg, align 8 %desc = load ptr addrspace(8), ptr %arg, align 8
tail call void @llvm.amdgcn.raw.ptr.buffer.store.f32(float undef, ptr addrspace(8) %desc, i32 undef, i32 0, i32 0) tail call void @llvm.amdgcn.raw.ptr.buffer.store.f32(float poison, ptr addrspace(8) %desc, i32 undef, i32 0, i32 0)
br label %bb0 br label %bb0
} }

2
llvm/test/CodeGen/AMDGPU/vgpr-liverange-ir.ll
View File

@ -654,7 +654,7 @@ if.then: ; preds = %entry
%4 = addrspacecast ptr %2 to ptr addrspace(4) %4 = addrspacecast ptr %2 to ptr addrspace(4)
%5 = load <8 x i32>, ptr addrspace(4) %4, align 32 %5 = load <8 x i32>, ptr addrspace(4) %4, align 32
%6 = load <4 x i32>, ptr addrspace(4) %add.ptr.i, align 16 %6 = load <4 x i32>, ptr addrspace(4) %add.ptr.i, align 16
%7 = tail call float @llvm.amdgcn.image.sample.2d.f32.f32(i32 1, float undef, float undef, <8 x i32> %5, <4 x i32> %6, i1 false, i32 0, i32 0) %7 = tail call float @llvm.amdgcn.image.sample.2d.f32.f32(i32 1, float poison, float poison, <8 x i32> %5, <4 x i32> %6, i1 false, i32 0, i32 0)
store float %7, ptr addrspace(1) poison, align 4 store float %7, ptr addrspace(1) poison, align 4
ret void ret void
} }

2
llvm/test/CodeGen/AMDGPU/wave32.ll
View File

@ -1511,7 +1511,7 @@ define amdgpu_kernel void @test_preserve_condition_undef_flag(float %arg, i32 %a
; GFX1064-NEXT: s_endpgm ; GFX1064-NEXT: s_endpgm
bb0: bb0:
%tmp = icmp sgt i32 %arg1, 4 %tmp = icmp sgt i32 %arg1, 4
%undef = call i1 @llvm.amdgcn.class.f32(float undef, i32 undef) %undef = call i1 @llvm.amdgcn.class.f32(float poison, i32 undef)
%tmp4 = select i1 %undef, float %arg, float 1.000000e+00 %tmp4 = select i1 %undef, float %arg, float 1.000000e+00
%tmp5 = fcmp ogt float %arg2, 0.000000e+00 %tmp5 = fcmp ogt float %arg2, 0.000000e+00
%tmp6 = fcmp olt float %arg2, 1.000000e+00 %tmp6 = fcmp olt float %arg2, 1.000000e+00

4
llvm/test/CodeGen/AMDGPU/wqm.ll
View File

@ -2112,7 +2112,7 @@ define amdgpu_ps <4 x float> @test_nonvoid_return() nounwind {
; GFX10-W32-NEXT: image_sample v[0:3], v0, s[0:7], s[0:3] dmask:0xf dim:SQ_RSRC_IMG_1D ; GFX10-W32-NEXT: image_sample v[0:3], v0, s[0:7], s[0:3] dmask:0xf dim:SQ_RSRC_IMG_1D
; GFX10-W32-NEXT: s_waitcnt vmcnt(0) ; GFX10-W32-NEXT: s_waitcnt vmcnt(0)
; GFX10-W32-NEXT: ; return to shader part epilog ; GFX10-W32-NEXT: ; return to shader part epilog
%tex = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 15, float undef, <8 x i32> poison, <4 x i32> poison, i1 false, i32 0, i32 0) #0 %tex = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 15, float poison, <8 x i32> poison, <4 x i32> poison, i1 false, i32 0, i32 0) #0
%tex0 = extractelement <4 x float> %tex, i32 0 %tex0 = extractelement <4 x float> %tex, i32 0
%dtex = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 15, float %tex0, <8 x i32> poison, <4 x i32> poison, i1 false, i32 0, i32 0) #0 %dtex = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 15, float %tex0, <8 x i32> poison, <4 x i32> poison, i1 false, i32 0, i32 0) #0
ret <4 x float> %dtex ret <4 x float> %dtex
@ -2155,7 +2155,7 @@ define amdgpu_ps <4 x float> @test_nonvoid_return_unreachable(i32 inreg %c) noun
; GFX10-W32-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-W32-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-W32-NEXT: .LBB38_3: ; GFX10-W32-NEXT: .LBB38_3:
entry: entry:
%tex = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 15, float undef, <8 x i32> poison, <4 x i32> poison, i1 false, i32 0, i32 0) #0 %tex = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 15, float poison, <8 x i32> poison, <4 x i32> poison, i1 false, i32 0, i32 0) #0
%tex0 = extractelement <4 x float> %tex, i32 0 %tex0 = extractelement <4 x float> %tex, i32 0
%dtex = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 15, float %tex0, <8 x i32> poison, <4 x i32> poison, i1 false, i32 0, i32 0) #0 %dtex = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 15, float %tex0, <8 x i32> poison, <4 x i32> poison, i1 false, i32 0, i32 0) #0
%cc = icmp sgt i32 %c, 0 %cc = icmp sgt i32 %c, 0

2
llvm/test/CodeGen/AMDGPU/xor3-i1-const.ll
View File

@ -13,7 +13,7 @@ define amdgpu_ps float @xor3_i1_const(float inreg %arg1, i32 inreg %arg2) {
; GCN-NEXT: ; return to shader part epilog ; GCN-NEXT: ; return to shader part epilog
main_body: main_body:
%tmp26 = fcmp nsz olt float %arg1, 0.000000e+00 %tmp26 = fcmp nsz olt float %arg1, 0.000000e+00
%tmp28 = call nsz float @llvm.amdgcn.interp.p2(float undef, float undef, i32 0, i32 0, i32 %arg2) %tmp28 = call nsz float @llvm.amdgcn.interp.p2(float poison, float poison, i32 0, i32 0, i32 %arg2)
%tmp29 = fcmp nsz olt float %arg1, 5.700000e+01 %tmp29 = fcmp nsz olt float %arg1, 5.700000e+01
%tmp31 = fcmp nsz olt float %tmp28, 0.000000e+00 %tmp31 = fcmp nsz olt float %tmp28, 0.000000e+00
%.demorgan = and i1 %tmp26, %tmp29 %.demorgan = and i1 %tmp26, %tmp29