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[LegalizeTypes] Don't promote operands to VP extends (#179475)

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This is part of the work to remove trivial VP intrinsics.

When promoting the result of a VP node, if we need to extend an operand
then we also extend it with a VP node.

We don't check if the VP node is legal though which will cause crashes
if the target doesn't support VP_ZEXT/VP_SEXT. This switches it to use a
regular non-VP node to extend instead.
This commit is contained in:
Luke Lau 2026-02-03 23:17:03 +08:00 committed by GitHub
parent d6211b112f
commit 030fc7d08e
No known key found for this signature in database
GPG Key ID: B5690EEEBB952194
27 changed files with 115 additions and 163 deletions
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80
llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
View File

@ -738,18 +738,15 @@ SDValue DAGTypeLegalizer::PromoteIntRes_CTLZ(SDNode *N) {
// Subtract off the extra leading bits in the bigger type.
SDValue ExtractLeadingBits = DAG.getConstant(
NVT.getScalarSizeInBits() - OVT.getScalarSizeInBits(), dl, NVT);
// Zero extend to the promoted type and do the count there.
SDValue Op = ZExtPromotedInteger(N->getOperand(0));
if (!N->isVPOpcode()) {
// Zero extend to the promoted type and do the count there.
SDValue Op = ZExtPromotedInteger(N->getOperand(0));
if (!N->isVPOpcode())
return DAG.getNode(ISD::SUB, dl, NVT,
DAG.getNode(N->getOpcode(), dl, NVT, Op),
ExtractLeadingBits);
}
SDValue Mask = N->getOperand(1);
SDValue EVL = N->getOperand(2);
// Zero extend to the promoted type and do the count there.
SDValue Op = VPZExtPromotedInteger(N->getOperand(0), Mask, EVL);
return DAG.getNode(ISD::VP_SUB, dl, NVT,
DAG.getNode(N->getOpcode(), dl, NVT, Op, Mask, EVL),
ExtractLeadingBits, Mask, EVL);
@ -806,14 +803,12 @@ SDValue DAGTypeLegalizer::PromoteIntRes_CTPOP_PARITY(SDNode *N) {
}
// Zero extend to the promoted type and do the count or parity there.
if (!N->isVPOpcode()) {
SDValue Op = ZExtPromotedInteger(N->getOperand(0));
SDValue Op = ZExtPromotedInteger(N->getOperand(0));
if (!N->isVPOpcode())
return DAG.getNode(N->getOpcode(), SDLoc(N), Op.getValueType(), Op);
}
SDValue Mask = N->getOperand(1);
SDValue EVL = N->getOperand(2);
SDValue Op = VPZExtPromotedInteger(N->getOperand(0), Mask, EVL);
return DAG.getNode(N->getOpcode(), SDLoc(N), Op.getValueType(), Op, Mask,
EVL);
}
@ -1483,17 +1478,13 @@ SDValue DAGTypeLegalizer::PromoteIntRes_FFREXP(SDNode *N) {
SDValue DAGTypeLegalizer::PromoteIntRes_SHL(SDNode *N) {
SDValue LHS = GetPromotedInteger(N->getOperand(0));
SDValue RHS = N->getOperand(1);
if (N->getOpcode() != ISD::VP_SHL) {
if (getTypeAction(RHS.getValueType()) == TargetLowering::TypePromoteInteger)
RHS = ZExtPromotedInteger(RHS);
if (getTypeAction(RHS.getValueType()) == TargetLowering::TypePromoteInteger)
RHS = ZExtPromotedInteger(RHS);
if (N->getOpcode() != ISD::VP_SHL)
return DAG.getNode(N->getOpcode(), SDLoc(N), LHS.getValueType(), LHS, RHS);
}
SDValue Mask = N->getOperand(2);
SDValue EVL = N->getOperand(3);
if (getTypeAction(RHS.getValueType()) == TargetLowering::TypePromoteInteger)
RHS = VPZExtPromotedInteger(RHS, Mask, EVL);
return DAG.getNode(N->getOpcode(), SDLoc(N), LHS.getValueType(), LHS, RHS,
Mask, EVL);
}
@ -1519,37 +1510,30 @@ SDValue DAGTypeLegalizer::PromoteIntRes_SimpleIntBinOp(SDNode *N) {
}
SDValue DAGTypeLegalizer::PromoteIntRes_SExtIntBinOp(SDNode *N) {
if (N->getNumOperands() == 2) {
// Sign extend the input.
SDValue LHS = SExtPromotedInteger(N->getOperand(0));
SDValue RHS = SExtPromotedInteger(N->getOperand(1));
// Sign extend the input.
SDValue LHS = SExtPromotedInteger(N->getOperand(0));
SDValue RHS = SExtPromotedInteger(N->getOperand(1));
if (N->getNumOperands() == 2)
return DAG.getNode(N->getOpcode(), SDLoc(N), LHS.getValueType(), LHS, RHS);
}
assert(N->getNumOperands() == 4 && "Unexpected number of operands!");
assert(N->isVPOpcode() && "Expected VP opcode");
SDValue Mask = N->getOperand(2);
SDValue EVL = N->getOperand(3);
// Sign extend the input.
SDValue LHS = VPSExtPromotedInteger(N->getOperand(0), Mask, EVL);
SDValue RHS = VPSExtPromotedInteger(N->getOperand(1), Mask, EVL);
return DAG.getNode(N->getOpcode(), SDLoc(N), LHS.getValueType(), LHS, RHS,
Mask, EVL);
}
SDValue DAGTypeLegalizer::PromoteIntRes_ZExtIntBinOp(SDNode *N) {
if (N->getNumOperands() == 2) {
// Zero extend the input.
SDValue LHS = ZExtPromotedInteger(N->getOperand(0));
SDValue RHS = ZExtPromotedInteger(N->getOperand(1));
// Zero extend the input.
SDValue LHS = ZExtPromotedInteger(N->getOperand(0));
SDValue RHS = ZExtPromotedInteger(N->getOperand(1));
if (N->getNumOperands() == 2)
return DAG.getNode(N->getOpcode(), SDLoc(N), LHS.getValueType(), LHS, RHS);
}
assert(N->getNumOperands() == 4 && "Unexpected number of operands!");
assert(N->isVPOpcode() && "Expected VP opcode");
// Zero extend the input.
SDValue Mask = N->getOperand(2);
SDValue EVL = N->getOperand(3);
SDValue LHS = VPZExtPromotedInteger(N->getOperand(0), Mask, EVL);
SDValue RHS = VPZExtPromotedInteger(N->getOperand(1), Mask, EVL);
return DAG.getNode(N->getOpcode(), SDLoc(N), LHS.getValueType(), LHS, RHS,
Mask, EVL);
}
@ -1567,41 +1551,31 @@ SDValue DAGTypeLegalizer::PromoteIntRes_UMINUMAX(SDNode *N) {
}
SDValue DAGTypeLegalizer::PromoteIntRes_SRA(SDNode *N) {
// The input value must be properly sign extended.
SDValue LHS = SExtPromotedInteger(N->getOperand(0));
SDValue RHS = N->getOperand(1);
if (N->getOpcode() != ISD::VP_SRA) {
// The input value must be properly sign extended.
SDValue LHS = SExtPromotedInteger(N->getOperand(0));
if (getTypeAction(RHS.getValueType()) == TargetLowering::TypePromoteInteger)
RHS = ZExtPromotedInteger(RHS);
if (getTypeAction(RHS.getValueType()) == TargetLowering::TypePromoteInteger)
RHS = ZExtPromotedInteger(RHS);
if (N->getOpcode() != ISD::VP_SRA)
return DAG.getNode(N->getOpcode(), SDLoc(N), LHS.getValueType(), LHS, RHS);
}
SDValue Mask = N->getOperand(2);
SDValue EVL = N->getOperand(3);
// The input value must be properly sign extended.
SDValue LHS = VPSExtPromotedInteger(N->getOperand(0), Mask, EVL);
if (getTypeAction(RHS.getValueType()) == TargetLowering::TypePromoteInteger)
RHS = VPZExtPromotedInteger(RHS, Mask, EVL);
return DAG.getNode(N->getOpcode(), SDLoc(N), LHS.getValueType(), LHS, RHS,
Mask, EVL);
}
SDValue DAGTypeLegalizer::PromoteIntRes_SRL(SDNode *N) {
SDValue RHS = N->getOperand(1);
if (N->getOpcode() != ISD::VP_SRL) {
// The input value must be properly zero extended.
SDValue LHS = ZExtPromotedInteger(N->getOperand(0));
if (getTypeAction(RHS.getValueType()) == TargetLowering::TypePromoteInteger)
RHS = ZExtPromotedInteger(RHS);
// The input value must be properly zero extended.
SDValue LHS = ZExtPromotedInteger(N->getOperand(0));
if (getTypeAction(RHS.getValueType()) == TargetLowering::TypePromoteInteger)
RHS = ZExtPromotedInteger(RHS);
if (N->getOpcode() != ISD::VP_SRL)
return DAG.getNode(N->getOpcode(), SDLoc(N), LHS.getValueType(), LHS, RHS);
}
SDValue Mask = N->getOperand(2);
SDValue EVL = N->getOperand(3);
// The input value must be properly zero extended.
SDValue LHS = VPZExtPromotedInteger(N->getOperand(0), Mask, EVL);
if (getTypeAction(RHS.getValueType()) == TargetLowering::TypePromoteInteger)
RHS = VPZExtPromotedInteger(RHS, Mask, EVL);
return DAG.getNode(N->getOpcode(), SDLoc(N), LHS.getValueType(), LHS, RHS,
Mask, EVL);
}
@ -1671,7 +1645,7 @@ SDValue DAGTypeLegalizer::PromoteIntRes_VPFunnelShift(SDNode *N) {
SDValue Mask = N->getOperand(3);
SDValue EVL = N->getOperand(4);
if (getTypeAction(Amt.getValueType()) == TargetLowering::TypePromoteInteger)
Amt = VPZExtPromotedInteger(Amt, Mask, EVL);
Amt = ZExtPromotedInteger(Amt);
EVT AmtVT = Amt.getValueType();
SDLoc DL(N);

21
llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
View File

@ -273,27 +273,6 @@ private:
return DAG.getZeroExtendInReg(Op, dl, OldVT);
}
/// Get a promoted operand and zero extend it to the final size.
SDValue VPSExtPromotedInteger(SDValue Op, SDValue Mask, SDValue EVL) {
EVT OldVT = Op.getValueType();
SDLoc dl(Op);
Op = GetPromotedInteger(Op);
// FIXME: Add VP_SIGN_EXTEND_INREG.
EVT VT = Op.getValueType();
unsigned BitsDiff = VT.getScalarSizeInBits() - OldVT.getScalarSizeInBits();
SDValue ShiftCst = DAG.getShiftAmountConstant(BitsDiff, VT, dl);
SDValue Shl = DAG.getNode(ISD::VP_SHL, dl, VT, Op, ShiftCst, Mask, EVL);
return DAG.getNode(ISD::VP_SRA, dl, VT, Shl, ShiftCst, Mask, EVL);
}
/// Get a promoted operand and zero extend it to the final size.
SDValue VPZExtPromotedInteger(SDValue Op, SDValue Mask, SDValue EVL) {
EVT OldVT = Op.getValueType();
SDLoc dl(Op);
Op = GetPromotedInteger(Op);
return DAG.getVPZeroExtendInReg(Op, Mask, EVL, dl, OldVT);
}
// Promote the given operand V (vector or scalar) according to N's specific
// reduction kind. N must be an integer VECREDUCE_* or VP_REDUCE_*. Returns
// the nominal extension opcode (ISD::(ANY|ZERO|SIGN)_EXTEND) and the

4
llvm/test/CodeGen/RISCV/rvv/ctlz-vp.ll
View File

@ -2504,7 +2504,7 @@ define <vscale x 1 x i9> @vp_ctlz_nxv1i9(<vscale x 1 x i9> %va, <vscale x 1 x i1
; CHECK: # %bb.0:
; CHECK-NEXT: li a1, 511
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; CHECK-NEXT: vand.vx v8, v8, a1, v0.t
; CHECK-NEXT: vand.vx v8, v8, a1
; CHECK-NEXT: li a0, 142
; CHECK-NEXT: vfwcvt.f.xu.v v9, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
@ -2521,7 +2521,7 @@ define <vscale x 1 x i9> @vp_ctlz_nxv1i9(<vscale x 1 x i9> %va, <vscale x 1 x i1
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: li a1, 511
; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; CHECK-ZVBB-NEXT: vand.vx v8, v8, a1, v0.t
; CHECK-ZVBB-NEXT: vand.vx v8, v8, a1
; CHECK-ZVBB-NEXT: vclz.v v8, v8, v0.t
; CHECK-ZVBB-NEXT: vadd.vi v8, v8, -7, v0.t
; CHECK-ZVBB-NEXT: ret

4
llvm/test/CodeGen/RISCV/rvv/ctpop-vp.ll
View File

@ -2388,7 +2388,7 @@ define <vscale x 1 x i9> @vp_ctpop_nxv1i9(<vscale x 1 x i9> %va, <vscale x 1 x i
; CHECK: # %bb.0:
; CHECK-NEXT: li a1, 511
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; CHECK-NEXT: vand.vx v8, v8, a1, v0.t
; CHECK-NEXT: vand.vx v8, v8, a1
; CHECK-NEXT: lui a0, 5
; CHECK-NEXT: addi a0, a0, 1365
; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t
@ -2414,7 +2414,7 @@ define <vscale x 1 x i9> @vp_ctpop_nxv1i9(<vscale x 1 x i9> %va, <vscale x 1 x i
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: li a1, 511
; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; CHECK-ZVBB-NEXT: vand.vx v8, v8, a1, v0.t
; CHECK-ZVBB-NEXT: vand.vx v8, v8, a1
; CHECK-ZVBB-NEXT: vcpop.v v8, v8, v0.t
; CHECK-ZVBB-NEXT: ret
%v = call <vscale x 1 x i9> @llvm.vp.ctpop.nxv1i9(<vscale x 1 x i9> %va, <vscale x 1 x i1> %m, i32 %evl)

9
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vdiv-vp.ll
View File

@ -7,11 +7,12 @@
define <8 x i7> @vdiv_vv_v8i7(<8 x i7> %va, <8 x i7> %b, <8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vdiv_vv_v8i7:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT: vadd.vv v9, v9, v9
; CHECK-NEXT: vadd.vv v8, v8, v8
; CHECK-NEXT: vsra.vi v9, v9, 1
; CHECK-NEXT: vsra.vi v8, v8, 1
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
; CHECK-NEXT: vsll.vi v9, v9, 1, v0.t
; CHECK-NEXT: vsra.vi v9, v9, 1, v0.t
; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
; CHECK-NEXT: vsra.vi v8, v8, 1, v0.t
; CHECK-NEXT: vdiv.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
%v = call <8 x i7> @llvm.vp.sdiv.v8i7(<8 x i7> %va, <8 x i7> %b, <8 x i1> %m, i32 %evl)

5
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vdivu-vp.ll
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@ -8,9 +8,10 @@ define <8 x i7> @vdivu_vv_v8i7(<8 x i7> %va, <8 x i7> %b, <8 x i1> %m, i32 zeroe
; CHECK-LABEL: vdivu_vv_v8i7:
; CHECK: # %bb.0:
; CHECK-NEXT: li a1, 127
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT: vand.vx v9, v9, a1
; CHECK-NEXT: vand.vx v8, v8, a1
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
; CHECK-NEXT: vand.vx v9, v9, a1, v0.t
; CHECK-NEXT: vand.vx v8, v8, a1, v0.t
; CHECK-NEXT: vdivu.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
%v = call <8 x i7> @llvm.vp.udiv.v8i7(<8 x i7> %va, <8 x i7> %b, <8 x i1> %m, i32 %evl)

9
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmax-vp.ll
View File

@ -7,11 +7,12 @@
define <8 x i7> @vmax_vv_v8i7(<8 x i7> %va, <8 x i7> %b, <8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vmax_vv_v8i7:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT: vadd.vv v9, v9, v9
; CHECK-NEXT: vadd.vv v8, v8, v8
; CHECK-NEXT: vsra.vi v9, v9, 1
; CHECK-NEXT: vsra.vi v8, v8, 1
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
; CHECK-NEXT: vsll.vi v9, v9, 1, v0.t
; CHECK-NEXT: vsra.vi v9, v9, 1, v0.t
; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
; CHECK-NEXT: vsra.vi v8, v8, 1, v0.t
; CHECK-NEXT: vmax.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
%v = call <8 x i7> @llvm.vp.smax.v8i7(<8 x i7> %va, <8 x i7> %b, <8 x i1> %m, i32 %evl)

5
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmaxu-vp.ll
View File

@ -8,9 +8,10 @@ define <8 x i7> @vmaxu_vv_v8i7(<8 x i7> %va, <8 x i7> %b, <8 x i1> %m, i32 zeroe
; CHECK-LABEL: vmaxu_vv_v8i7:
; CHECK: # %bb.0:
; CHECK-NEXT: li a1, 127
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT: vand.vx v9, v9, a1
; CHECK-NEXT: vand.vx v8, v8, a1
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
; CHECK-NEXT: vand.vx v9, v9, a1, v0.t
; CHECK-NEXT: vand.vx v8, v8, a1, v0.t
; CHECK-NEXT: vmaxu.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
%v = call <8 x i7> @llvm.vp.umax.v8i7(<8 x i7> %va, <8 x i7> %b, <8 x i1> %m, i32 %evl)

9
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmin-vp.ll
View File

@ -7,11 +7,12 @@
define <8 x i7> @vmin_vv_v8i7(<8 x i7> %va, <8 x i7> %b, <8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vmin_vv_v8i7:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT: vadd.vv v9, v9, v9
; CHECK-NEXT: vadd.vv v8, v8, v8
; CHECK-NEXT: vsra.vi v9, v9, 1
; CHECK-NEXT: vsra.vi v8, v8, 1
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
; CHECK-NEXT: vsll.vi v9, v9, 1, v0.t
; CHECK-NEXT: vsra.vi v9, v9, 1, v0.t
; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
; CHECK-NEXT: vsra.vi v8, v8, 1, v0.t
; CHECK-NEXT: vmin.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
%v = call <8 x i7> @llvm.vp.smin.v8i7(<8 x i7> %va, <8 x i7> %b, <8 x i1> %m, i32 %evl)

5
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vminu-vp.ll
View File

@ -8,9 +8,10 @@ define <8 x i7> @vminu_vv_v8i7(<8 x i7> %va, <8 x i7> %b, <8 x i1> %m, i32 zeroe
; CHECK-LABEL: vminu_vv_v8i7:
; CHECK: # %bb.0:
; CHECK-NEXT: li a1, 127
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT: vand.vx v9, v9, a1
; CHECK-NEXT: vand.vx v8, v8, a1
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
; CHECK-NEXT: vand.vx v9, v9, a1, v0.t
; CHECK-NEXT: vand.vx v8, v8, a1, v0.t
; CHECK-NEXT: vminu.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
%v = call <8 x i7> @llvm.vp.umin.v8i7(<8 x i7> %va, <8 x i7> %b, <8 x i1> %m, i32 %evl)

9
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrem-vp.ll
View File

@ -7,11 +7,12 @@
define <8 x i7> @vrem_vv_v8i7(<8 x i7> %va, <8 x i7> %b, <8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vrem_vv_v8i7:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT: vadd.vv v9, v9, v9
; CHECK-NEXT: vadd.vv v8, v8, v8
; CHECK-NEXT: vsra.vi v9, v9, 1
; CHECK-NEXT: vsra.vi v8, v8, 1
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
; CHECK-NEXT: vsll.vi v9, v9, 1, v0.t
; CHECK-NEXT: vsra.vi v9, v9, 1, v0.t
; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
; CHECK-NEXT: vsra.vi v8, v8, 1, v0.t
; CHECK-NEXT: vrem.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
%v = call <8 x i7> @llvm.vp.srem.v8i7(<8 x i7> %va, <8 x i7> %b, <8 x i1> %m, i32 %evl)

5
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vremu-vp.ll
View File

@ -8,9 +8,10 @@ define <8 x i7> @vremu_vv_v8i7(<8 x i7> %va, <8 x i7> %b, <8 x i1> %m, i32 zeroe
; CHECK-LABEL: vremu_vv_v8i7:
; CHECK: # %bb.0:
; CHECK-NEXT: li a1, 127
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT: vand.vx v9, v9, a1
; CHECK-NEXT: vand.vx v8, v8, a1
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
; CHECK-NEXT: vand.vx v9, v9, a1, v0.t
; CHECK-NEXT: vand.vx v8, v8, a1, v0.t
; CHECK-NEXT: vremu.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
%v = call <8 x i7> @llvm.vp.urem.v8i7(<8 x i7> %va, <8 x i7> %b, <8 x i1> %m, i32 %evl)

3
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vshl-vp.ll
View File

@ -8,8 +8,9 @@ define <8 x i7> @vsll_vv_v8i7(<8 x i7> %va, <8 x i7> %b, <8 x i1> %m, i32 zeroex
; CHECK-LABEL: vsll_vv_v8i7:
; CHECK: # %bb.0:
; CHECK-NEXT: li a1, 127
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT: vand.vx v9, v9, a1
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
; CHECK-NEXT: vand.vx v9, v9, a1, v0.t
; CHECK-NEXT: vsll.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
%v = call <8 x i7> @llvm.vp.shl.v8i7(<8 x i7> %va, <8 x i7> %b, <8 x i1> %m, i32 %evl)

7
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsra-vp.ll
View File

@ -8,10 +8,11 @@ define <8 x i7> @vsra_vv_v8i7(<8 x i7> %va, <8 x i7> %b, <8 x i1> %m, i32 zeroex
; CHECK-LABEL: vsra_vv_v8i7:
; CHECK: # %bb.0:
; CHECK-NEXT: li a1, 127
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT: vadd.vv v8, v8, v8
; CHECK-NEXT: vand.vx v9, v9, a1
; CHECK-NEXT: vsra.vi v8, v8, 1
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
; CHECK-NEXT: vand.vx v9, v9, a1, v0.t
; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
; CHECK-NEXT: vsra.vi v8, v8, 1, v0.t
; CHECK-NEXT: vsra.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
%v = call <8 x i7> @llvm.vp.ashr.v8i7(<8 x i7> %va, <8 x i7> %b, <8 x i1> %m, i32 %evl)

5
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsrl-vp.ll
View File

@ -8,9 +8,10 @@ define <8 x i7> @vsrl_vv_v8i7(<8 x i7> %va, <8 x i7> %b, <8 x i1> %m, i32 zeroex
; CHECK-LABEL: vsrl_vv_v8i7:
; CHECK: # %bb.0:
; CHECK-NEXT: li a1, 127
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT: vand.vx v9, v9, a1
; CHECK-NEXT: vand.vx v8, v8, a1
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
; CHECK-NEXT: vand.vx v9, v9, a1, v0.t
; CHECK-NEXT: vand.vx v8, v8, a1, v0.t
; CHECK-NEXT: vsrl.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
%v = call <8 x i7> @llvm.vp.lshr.v8i7(<8 x i7> %va, <8 x i7> %b, <8 x i1> %m, i32 %evl)

34
llvm/test/CodeGen/RISCV/rvv/fshr-fshl-vp.ll
View File

@ -1128,16 +1128,16 @@ define <vscale x 1 x i9> @fshr_v1i9(<vscale x 1 x i9> %a, <vscale x 1 x i9> %b,
; CHECK: # %bb.0:
; CHECK-NEXT: li a1, 511
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; CHECK-NEXT: vand.vx v10, v10, a1, v0.t
; CHECK-NEXT: vsll.vi v9, v9, 7, v0.t
; CHECK-NEXT: vand.vx v10, v10, a1
; CHECK-NEXT: li a0, 9
; CHECK-NEXT: vremu.vx v10, v10, a0, v0.t
; CHECK-NEXT: vadd.vi v10, v10, 7, v0.t
; CHECK-NEXT: vand.vi v11, v10, 15, v0.t
; CHECK-NEXT: vsll.vi v9, v9, 7, v0.t
; CHECK-NEXT: vsrl.vv v9, v9, v11, v0.t
; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
; CHECK-NEXT: vnot.v v10, v10, v0.t
; CHECK-NEXT: vand.vi v10, v10, 15, v0.t
; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
; CHECK-NEXT: vsll.vv v8, v8, v10, v0.t
; CHECK-NEXT: vor.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
@ -1150,16 +1150,16 @@ define <vscale x 1 x i9> @fshl_v1i9(<vscale x 1 x i9> %a, <vscale x 1 x i9> %b,
; CHECK: # %bb.0:
; CHECK-NEXT: li a1, 511
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; CHECK-NEXT: vand.vx v10, v10, a1, v0.t
; CHECK-NEXT: li a0, 9
; CHECK-NEXT: vremu.vx v10, v10, a0, v0.t
; CHECK-NEXT: vand.vi v11, v10, 15, v0.t
; CHECK-NEXT: vsll.vv v8, v8, v11, v0.t
; CHECK-NEXT: vnot.v v10, v10, v0.t
; CHECK-NEXT: vand.vi v10, v10, 15, v0.t
; CHECK-NEXT: vsll.vi v9, v9, 7, v0.t
; CHECK-NEXT: vand.vx v10, v10, a1
; CHECK-NEXT: li a0, 9
; CHECK-NEXT: vsrl.vi v9, v9, 1, v0.t
; CHECK-NEXT: vsrl.vv v9, v9, v10, v0.t
; CHECK-NEXT: vremu.vx v10, v10, a0, v0.t
; CHECK-NEXT: vnot.v v11, v10, v0.t
; CHECK-NEXT: vand.vi v11, v11, 15, v0.t
; CHECK-NEXT: vsrl.vv v9, v9, v11, v0.t
; CHECK-NEXT: vand.vi v10, v10, 15, v0.t
; CHECK-NEXT: vsll.vv v8, v8, v10, v0.t
; CHECK-NEXT: vor.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
%res = call <vscale x 1 x i9> @llvm.vp.fshl.nxv1i9(<vscale x 1 x i9> %a, <vscale x 1 x i9> %b, <vscale x 1 x i9> %c, <vscale x 1 x i1> %m, i32 %evl)
@ -1170,13 +1170,13 @@ define <vscale x 1 x i8> @fshr_v1i4(<vscale x 1 x i8> %a, <vscale x 1 x i8> %b,
; CHECK-LABEL: fshr_v1i4:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
; CHECK-NEXT: vand.vi v10, v10, 15, v0.t
; CHECK-NEXT: vand.vi v10, v10, 15
; CHECK-NEXT: li a0, 4
; CHECK-NEXT: vremu.vx v10, v10, a0, v0.t
; CHECK-NEXT: vand.vi v9, v9, 15, v0.t
; CHECK-NEXT: vsll.vi v8, v8, 4, v0.t
; CHECK-NEXT: vor.vv v8, v8, v9, v0.t
; CHECK-NEXT: vremu.vx v9, v10, a0, v0.t
; CHECK-NEXT: vsrl.vv v8, v8, v9, v0.t
; CHECK-NEXT: vsrl.vv v8, v8, v10, v0.t
; CHECK-NEXT: vand.vi v8, v8, 15, v0.t
; CHECK-NEXT: ret
%trunca = call <vscale x 1 x i4> @llvm.vp.trunc.nxv1i4.nxv1i8(<vscale x 1 x i8> %a, <vscale x 1 x i1> %m, i32 zeroext %evl)
@ -1191,13 +1191,13 @@ define <vscale x 1 x i8> @fshl_v1i4(<vscale x 1 x i8> %a, <vscale x 1 x i8> %b,
; CHECK-LABEL: fshl_v1i4:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
; CHECK-NEXT: vand.vi v10, v10, 15, v0.t
; CHECK-NEXT: vand.vi v10, v10, 15
; CHECK-NEXT: li a0, 4
; CHECK-NEXT: vremu.vx v10, v10, a0, v0.t
; CHECK-NEXT: vand.vi v9, v9, 15, v0.t
; CHECK-NEXT: vsll.vi v8, v8, 4, v0.t
; CHECK-NEXT: vor.vv v8, v8, v9, v0.t
; CHECK-NEXT: vremu.vx v9, v10, a0, v0.t
; CHECK-NEXT: vsll.vv v8, v8, v9, v0.t
; CHECK-NEXT: vsll.vv v8, v8, v10, v0.t
; CHECK-NEXT: vsrl.vi v8, v8, 4, v0.t
; CHECK-NEXT: vand.vi v8, v8, 15, v0.t
; CHECK-NEXT: ret

9
llvm/test/CodeGen/RISCV/rvv/vdiv-vp.ll
View File

@ -8,12 +8,9 @@ define <vscale x 8 x i7> @vdiv_vx_nxv8i7(<vscale x 8 x i7> %a, i7 signext %b, <v
; CHECK-LABEL: vdiv_vx_nxv8i7:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma
; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vsra.vi v8, v8, 1, v0.t
; CHECK-NEXT: vsll.vi v9, v9, 1, v0.t
; CHECK-NEXT: vsra.vi v9, v9, 1, v0.t
; CHECK-NEXT: vdiv.vv v8, v8, v9, v0.t
; CHECK-NEXT: vadd.vv v8, v8, v8
; CHECK-NEXT: vsra.vi v8, v8, 1
; CHECK-NEXT: vdiv.vx v8, v8, a0, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 8 x i7> poison, i7 %b, i32 0
%vb = shufflevector <vscale x 8 x i7> %elt.head, <vscale x 8 x i7> poison, <vscale x 8 x i32> zeroinitializer

4
llvm/test/CodeGen/RISCV/rvv/vdivu-vp.ll
View File

@ -10,8 +10,8 @@ define <vscale x 8 x i7> @vdivu_vx_nxv8i7(<vscale x 8 x i7> %a, i7 signext %b, <
; CHECK-NEXT: li a2, 127
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma
; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vand.vx v8, v8, a2, v0.t
; CHECK-NEXT: vand.vx v9, v9, a2, v0.t
; CHECK-NEXT: vand.vx v8, v8, a2
; CHECK-NEXT: vand.vx v9, v9, a2
; CHECK-NEXT: vdivu.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 8 x i7> poison, i7 %b, i32 0

9
llvm/test/CodeGen/RISCV/rvv/vmax-vp.ll
View File

@ -8,12 +8,9 @@ define <vscale x 8 x i7> @vmax_vx_nxv8i7(<vscale x 8 x i7> %a, i7 signext %b, <v
; CHECK-LABEL: vmax_vx_nxv8i7:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma
; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vsra.vi v8, v8, 1, v0.t
; CHECK-NEXT: vsll.vi v9, v9, 1, v0.t
; CHECK-NEXT: vsra.vi v9, v9, 1, v0.t
; CHECK-NEXT: vmax.vv v8, v8, v9, v0.t
; CHECK-NEXT: vadd.vv v8, v8, v8
; CHECK-NEXT: vsra.vi v8, v8, 1
; CHECK-NEXT: vmax.vx v8, v8, a0, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 8 x i7> poison, i7 %b, i32 0
%vb = shufflevector <vscale x 8 x i7> %elt.head, <vscale x 8 x i7> poison, <vscale x 8 x i32> zeroinitializer

4
llvm/test/CodeGen/RISCV/rvv/vmaxu-vp.ll
View File

@ -10,8 +10,8 @@ define <vscale x 8 x i7> @vmaxu_vx_nxv8i7(<vscale x 8 x i7> %a, i7 signext %b, <
; CHECK-NEXT: li a2, 127
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma
; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vand.vx v8, v8, a2, v0.t
; CHECK-NEXT: vand.vx v9, v9, a2, v0.t
; CHECK-NEXT: vand.vx v8, v8, a2
; CHECK-NEXT: vand.vx v9, v9, a2
; CHECK-NEXT: vmaxu.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 8 x i7> poison, i7 %b, i32 0

9
llvm/test/CodeGen/RISCV/rvv/vmin-vp.ll
View File

@ -8,12 +8,9 @@ define <vscale x 8 x i7> @vmin_vx_nxv8i7(<vscale x 8 x i7> %a, i7 signext %b, <v
; CHECK-LABEL: vmin_vx_nxv8i7:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma
; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vsra.vi v8, v8, 1, v0.t
; CHECK-NEXT: vsll.vi v9, v9, 1, v0.t
; CHECK-NEXT: vsra.vi v9, v9, 1, v0.t
; CHECK-NEXT: vmin.vv v8, v8, v9, v0.t
; CHECK-NEXT: vadd.vv v8, v8, v8
; CHECK-NEXT: vsra.vi v8, v8, 1
; CHECK-NEXT: vmin.vx v8, v8, a0, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 8 x i7> poison, i7 %b, i32 0
%vb = shufflevector <vscale x 8 x i7> %elt.head, <vscale x 8 x i7> poison, <vscale x 8 x i32> zeroinitializer

4
llvm/test/CodeGen/RISCV/rvv/vminu-vp.ll
View File

@ -10,8 +10,8 @@ define <vscale x 8 x i7> @vminu_vx_nxv8i7(<vscale x 8 x i7> %a, i7 signext %b, <
; CHECK-NEXT: li a2, 127
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma
; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vand.vx v8, v8, a2, v0.t
; CHECK-NEXT: vand.vx v9, v9, a2, v0.t
; CHECK-NEXT: vand.vx v8, v8, a2
; CHECK-NEXT: vand.vx v9, v9, a2
; CHECK-NEXT: vminu.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 8 x i7> poison, i7 %b, i32 0

9
llvm/test/CodeGen/RISCV/rvv/vrem-vp.ll
View File

@ -8,12 +8,9 @@ define <vscale x 8 x i7> @vrem_vx_nxv8i7(<vscale x 8 x i7> %a, i7 signext %b, <v
; CHECK-LABEL: vrem_vx_nxv8i7:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma
; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vsra.vi v8, v8, 1, v0.t
; CHECK-NEXT: vsll.vi v9, v9, 1, v0.t
; CHECK-NEXT: vsra.vi v9, v9, 1, v0.t
; CHECK-NEXT: vrem.vv v8, v8, v9, v0.t
; CHECK-NEXT: vadd.vv v8, v8, v8
; CHECK-NEXT: vsra.vi v8, v8, 1
; CHECK-NEXT: vrem.vx v8, v8, a0, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 8 x i7> poison, i7 %b, i32 0
%vb = shufflevector <vscale x 8 x i7> %elt.head, <vscale x 8 x i7> poison, <vscale x 8 x i32> zeroinitializer

4
llvm/test/CodeGen/RISCV/rvv/vremu-vp.ll
View File

@ -10,8 +10,8 @@ define <vscale x 8 x i7> @vremu_vx_nxv8i7(<vscale x 8 x i7> %a, i7 signext %b, <
; CHECK-NEXT: li a2, 127
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma
; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vand.vx v8, v8, a2, v0.t
; CHECK-NEXT: vand.vx v9, v9, a2, v0.t
; CHECK-NEXT: vand.vx v8, v8, a2
; CHECK-NEXT: vand.vx v9, v9, a2
; CHECK-NEXT: vremu.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 8 x i7> poison, i7 %b, i32 0

2
llvm/test/CodeGen/RISCV/rvv/vshl-vp.ll
View File

@ -10,7 +10,7 @@ define <vscale x 8 x i7> @vsll_vx_nxv8i7(<vscale x 8 x i7> %a, i7 signext %b, <v
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma
; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: li a0, 127
; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
; CHECK-NEXT: vand.vx v9, v9, a0
; CHECK-NEXT: vsll.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 8 x i7> poison, i7 %b, i32 0

6
llvm/test/CodeGen/RISCV/rvv/vsra-vp.ll
View File

@ -8,11 +8,11 @@ define <vscale x 8 x i7> @vsra_vx_nxv8i7(<vscale x 8 x i7> %a, i7 signext %b, <v
; CHECK-LABEL: vsra_vx_nxv8i7:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma
; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
; CHECK-NEXT: vadd.vv v8, v8, v8
; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: li a0, 127
; CHECK-NEXT: vsra.vi v8, v8, 1, v0.t
; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
; CHECK-NEXT: vsra.vi v8, v8, 1
; CHECK-NEXT: vand.vx v9, v9, a0
; CHECK-NEXT: vsra.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 8 x i7> poison, i7 %b, i32 0

4
llvm/test/CodeGen/RISCV/rvv/vsrl-vp.ll
View File

@ -10,8 +10,8 @@ define <vscale x 8 x i7> @vsrl_vx_nxv8i7(<vscale x 8 x i7> %a, i7 signext %b, <v
; CHECK-NEXT: li a2, 127
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma
; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vand.vx v8, v8, a2, v0.t
; CHECK-NEXT: vand.vx v9, v9, a2, v0.t
; CHECK-NEXT: vand.vx v8, v8, a2
; CHECK-NEXT: vand.vx v9, v9, a2
; CHECK-NEXT: vsrl.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 8 x i7> poison, i7 %b, i32 0