From 032b54f8e87f4fa380f2e83c8fbcd9b14d50f4e0 Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Tue, 18 Jun 2019 18:08:30 +0000 Subject: [PATCH] [TargetLowering] SimplifyDemandedBits - Merge ZERO_EXTEND+ZERO_EXTEND_VECTOR_INREG handling Other than adding consistent demanded elts handling which was a trivial addition, the other differences in functionality will be added in later patches. llvm-svn: 363713 --- .../CodeGen/SelectionDAG/TargetLowering.cpp | 40 ++++++++----------- 1 file changed, 16 insertions(+), 24 deletions(-) diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp index 5745ff4d2b7c..f8dbeb44fa04 100644 --- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp @@ -1372,35 +1372,27 @@ bool TargetLowering::SimplifyDemandedBits( KnownHi.One.zext(BitWidth).shl(HalfBitWidth); break; } - case ISD::ZERO_EXTEND: { - SDValue Src = Op.getOperand(0); - unsigned InBits = Src.getScalarValueSizeInBits(); - - // If none of the top bits are demanded, convert this into an any_extend. - if (DemandedBits.getActiveBits() <= InBits) - return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND, dl, VT, Src)); - - APInt InDemandedBits = DemandedBits.trunc(InBits); - if (SimplifyDemandedBits(Src, InDemandedBits, Known, TLO, Depth + 1)) - return true; - assert(!Known.hasConflict() && "Bits known to be one AND zero?"); - assert(Known.getBitWidth() == InBits && "Src width has changed?"); - Known = Known.zext(BitWidth, true /* ExtendedBitsAreKnownZero */); - break; - } + case ISD::ZERO_EXTEND: case ISD::ZERO_EXTEND_VECTOR_INREG: { - // TODO - merge this with ZERO_EXTEND above? SDValue Src = Op.getOperand(0); EVT SrcVT = Src.getValueType(); unsigned InBits = SrcVT.getScalarSizeInBits(); - unsigned InElts = SrcVT.getVectorNumElements(); + unsigned InElts = SrcVT.isVector() ? SrcVT.getVectorNumElements() : 1; + bool IsVecInReg = Op.getOpcode() == ISD::ZERO_EXTEND_VECTOR_INREG; - // If we only need the non-extended bits of the bottom element - // then we can just bitcast to the result. - if (DemandedBits.getActiveBits() <= InBits && DemandedElts == 1 && - VT.getSizeInBits() == SrcVT.getSizeInBits() && - TLO.DAG.getDataLayout().isLittleEndian()) - return TLO.CombineTo(Op, TLO.DAG.getBitcast(VT, Src)); + // If none of the top bits are demanded, convert this into an any_extend. + // TODO: Add ZERO_EXTEND_VECTOR_INREG - ANY_EXTEND_VECTOR_INREG fold. + if (DemandedBits.getActiveBits() <= InBits) { + // If we only need the non-extended bits of the bottom element + // then we can just bitcast to the result. + if (IsVecInReg && DemandedElts == 1 && + VT.getSizeInBits() == SrcVT.getSizeInBits() && + TLO.DAG.getDataLayout().isLittleEndian()) + return TLO.CombineTo(Op, TLO.DAG.getBitcast(VT, Src)); + + if (!IsVecInReg) + return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND, dl, VT, Src)); + } APInt InDemandedBits = DemandedBits.trunc(InBits); APInt InDemandedElts = DemandedElts.zextOrSelf(InElts);