[CodeGen] Consider imm offsets when sorting framerefs (#171012)
LocalStackSlotAllocation pass disallows negative offsets with respect to a base register. The pass ends up introducing a new register for such frame references. This patch helps LocalStackSlotAlloca to additionally consider the immediate offset of an instruction, when sorting frame refs - hence, avoiding negative offsets and maximizing reuse of the existing registers.
This commit is contained in:
Anshil Gandhi
GitHub
parent
51f6c58793
commit
03ad3d2e8f
@ -51,6 +51,7 @@ namespace {
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class FrameRef {
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MachineBasicBlock::iterator MI; // Instr referencing the frame
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int64_t LocalOffset; // Local offset of the frame idx referenced
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int64_t InstrOffset; // Offset of the instruction from the frame index
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int FrameIdx; // The frame index
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// Order reference instruction appears in program. Used to ensure
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@ -59,16 +60,20 @@ namespace {
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unsigned Order;
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public:
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FrameRef(MachineInstr *I, int64_t Offset, int Idx, unsigned Ord) :
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MI(I), LocalOffset(Offset), FrameIdx(Idx), Order(Ord) {}
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FrameRef(MachineInstr *I, int64_t Offset, int64_t InstrOffset, int Idx,
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unsigned Ord)
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: MI(I), LocalOffset(Offset), InstrOffset(InstrOffset), FrameIdx(Idx),
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Order(Ord) {}
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bool operator<(const FrameRef &RHS) const {
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return std::tie(LocalOffset, FrameIdx, Order) <
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std::tie(RHS.LocalOffset, RHS.FrameIdx, RHS.Order);
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return std::tuple(LocalOffset + InstrOffset, FrameIdx, Order) <
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std::tuple(RHS.LocalOffset + RHS.InstrOffset, RHS.FrameIdx,
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RHS.Order);
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}
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MachineBasicBlock::iterator getMachineInstr() const { return MI; }
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int64_t getLocalOffset() const { return LocalOffset; }
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int64_t getInstrOffset() const { return InstrOffset; }
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int getFrameIndex() const { return FrameIdx; }
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};
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@ -335,20 +340,27 @@ bool LocalStackSlotImpl::insertFrameReferenceRegisters(MachineFunction &Fn) {
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// than that, but the increased register pressure makes that a
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// tricky thing to balance. Investigate if re-materializing these
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// becomes an issue.
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for (const MachineOperand &MO : MI.operands()) {
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for (unsigned OpIdx = 0, OpEnd = MI.getNumOperands(); OpIdx != OpEnd;
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++OpIdx) {
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const MachineOperand &MO = MI.getOperand(OpIdx);
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// Consider replacing all frame index operands that reference
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// an object allocated in the local block.
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if (MO.isFI()) {
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// Don't try this with values not in the local block.
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if (!MFI.isObjectPreAllocated(MO.getIndex()))
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break;
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int Idx = MO.getIndex();
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int64_t LocalOffset = LocalOffsets[Idx];
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if (!TRI->needsFrameBaseReg(&MI, LocalOffset))
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break;
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FrameReferenceInsns.push_back(FrameRef(&MI, LocalOffset, Idx, Order++));
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if (!MO.isFI())
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continue;
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int FrameIdx = MO.getIndex();
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// Don't try this with values not in the local block.
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if (!MFI.isObjectPreAllocated(FrameIdx))
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break;
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}
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int64_t LocalOffset = LocalOffsets[FrameIdx];
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if (!TRI->needsFrameBaseReg(&MI, LocalOffset))
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break;
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int64_t InstrOffset = TRI->getFrameIndexInstrOffset(&MI, OpIdx);
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FrameReferenceInsns.emplace_back(&MI, LocalOffset, InstrOffset,
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FrameIdx, Order++);
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break;
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}
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}
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}
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@ -61,13 +61,11 @@ define amdgpu_kernel void @issue155902(i64 %arg, i64 %arg1, i64 %arg2, i64 %arg3
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; GFX950-NEXT: s_nop 0
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; GFX950-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x188
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; GFX950-NEXT: v_mov_b64_e32 v[0:1], 0
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; GFX950-NEXT: v_mov_b32_e32 v3, 0x4008
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; GFX950-NEXT: buffer_wbl2 sc0 sc1
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; GFX950-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
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; GFX950-NEXT: scratch_store_dwordx2 v3, v[0:1], off sc0 sc1
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; GFX950-NEXT: scratch_store_dwordx2 off, v[0:1], s33 offset:8
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; GFX950-NEXT: scratch_store_dwordx2 off, v[0:1], s33
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; GFX950-NEXT: v_mov_b64_e32 v[0:1], 0x384
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; GFX950-NEXT: scratch_store_dwordx2 off, v[0:1], s33 offset:16
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; GFX950-NEXT: s_waitcnt lgkmcnt(0)
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; GFX950-NEXT: v_mov_b64_e32 v[0:1], s[0:1]
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; GFX950-NEXT: v_readlane_b32 s0, v2, 0
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; GFX950-NEXT: s_nop 4
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@ -295,8 +293,7 @@ define amdgpu_kernel void @issue155902_fp(i64 %arg, i64 %arg1, i64 %arg2, i64 %a
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; GFX950-NEXT: s_nop 0
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; GFX950-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x188
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; GFX950-NEXT: v_mov_b64_e32 v[0:1], 0
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; GFX950-NEXT: s_add_i32 s1, s33, 0x4008
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; GFX950-NEXT: scratch_store_dwordx2 off, v[0:1], s1 offset:8
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; GFX950-NEXT: scratch_store_dwordx2 off, v[0:1], s0 offset:8
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; GFX950-NEXT: scratch_store_dwordx2 off, v[0:1], s0
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; GFX950-NEXT: v_mov_b64_e32 v[0:1], 0x384
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; GFX950-NEXT: scratch_store_dwordx2 off, v[0:1], s0 offset:16
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@ -49,15 +49,15 @@ machineFunctionInfo:
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body: |
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bb.0:
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; GFX10-LABEL: name: local_stack_alloc__v_add_u32_e64__literal_offsets_commute
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; GFX10: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 256
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; GFX10: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 100
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; GFX10-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
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; GFX10-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 killed [[S_MOV_B32_]], [[V_MOV_B32_e32_]], 0, implicit $exec
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; GFX10-NEXT: [[V_ADD_U32_e64_1:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 156, [[V_ADD_U32_e64_]], 0, implicit $exec
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; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_1]]
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; GFX10-NEXT: [[V_ADD_U32_e64_2:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 412, [[V_ADD_U32_e64_]], 0, implicit $exec
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; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_2]]
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; GFX10-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[V_ADD_U32_e64_]]
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; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[COPY]]
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; GFX10-NEXT: [[V_ADD_U32_e64_1:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 256, [[V_ADD_U32_e64_]], 0, implicit $exec
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; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_1]]
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; GFX10-NEXT: [[V_ADD_U32_e64_2:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[V_ADD_U32_e64_]], -156, 0, implicit $exec
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; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_2]]
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; GFX10-NEXT: SI_RETURN
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;
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; GFX12-LABEL: name: local_stack_alloc__v_add_u32_e64__literal_offsets_commute
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@ -294,12 +294,13 @@ define amdgpu_kernel void @local_stack_offset_uses_sp_flat(ptr addrspace(1) %out
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; FLATSCR-NEXT: s_add_u32 flat_scratch_lo, s8, s13
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; FLATSCR-NEXT: s_addc_u32 flat_scratch_hi, s9, 0
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; FLATSCR-NEXT: v_mov_b32_e32 v0, 0
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; FLATSCR-NEXT: s_mov_b32 s0, 0
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; FLATSCR-NEXT: scratch_store_dword off, v0, s0 offset:1024
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; FLATSCR-NEXT: s_movk_i32 s0, 0x2000
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; FLATSCR-NEXT: scratch_store_dword off, v0, s0
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; FLATSCR-NEXT: s_waitcnt vmcnt(0)
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; FLATSCR-NEXT: s_mov_b32 s0, 0
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; FLATSCR-NEXT: .LBB2_1: ; %loadstoreloop
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; FLATSCR-NEXT: ; =>This Inner Loop Header: Depth=1
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; FLATSCR-NEXT: s_add_i32 s1, s0, 0x2000
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; FLATSCR-NEXT: s_add_i32 s1, s0, 0x4000
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; FLATSCR-NEXT: s_add_i32 s0, s0, 1
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; FLATSCR-NEXT: s_cmpk_lt_u32 s0, 0x2120
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; FLATSCR-NEXT: scratch_store_byte off, v0, s1
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@ -307,12 +308,12 @@ define amdgpu_kernel void @local_stack_offset_uses_sp_flat(ptr addrspace(1) %out
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; FLATSCR-NEXT: s_cbranch_scc1 .LBB2_1
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; FLATSCR-NEXT: ; %bb.2: ; %split
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; FLATSCR-NEXT: s_movk_i32 s0, 0x1000
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; FLATSCR-NEXT: s_addk_i32 s0, 0x2000
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; FLATSCR-NEXT: s_addk_i32 s0, 0x4000
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; FLATSCR-NEXT: scratch_load_dwordx2 v[8:9], off, s0 offset:720 glc
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; FLATSCR-NEXT: s_waitcnt vmcnt(0)
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; FLATSCR-NEXT: scratch_load_dwordx4 v[0:3], off, s0 offset:704 glc
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; FLATSCR-NEXT: s_waitcnt vmcnt(0)
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; FLATSCR-NEXT: s_movk_i32 s0, 0x2000
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; FLATSCR-NEXT: s_movk_i32 s0, 0x4000
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; FLATSCR-NEXT: scratch_load_dwordx2 v[10:11], off, s0 offset:16 glc
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; FLATSCR-NEXT: s_waitcnt vmcnt(0)
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; FLATSCR-NEXT: scratch_load_dwordx4 v[4:7], off, s0 glc
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@ -13,7 +13,7 @@ body: |
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; CHECK-LABEL: name: issue155902
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; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xexec_hi = S_MOV_B32 %stack.1
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; CHECK-NEXT: [[V_MOV_B:%[0-9]+]]:vreg_64_align2 = V_MOV_B64_PSEUDO 0, implicit $exec
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; CHECK-NEXT: SCRATCH_STORE_DWORDX2_SADDR [[V_MOV_B]], %stack.1, 8, 0, implicit $exec, implicit $flat_scr
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; CHECK-NEXT: SCRATCH_STORE_DWORDX2_SADDR [[V_MOV_B]], [[S_MOV_B32_]], 8, 0, implicit $exec, implicit $flat_scr
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; CHECK-NEXT: SCRATCH_STORE_DWORDX2_SADDR [[V_MOV_B]], [[S_MOV_B32_]], 0, 0, implicit $exec, implicit $flat_scr
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; CHECK-NEXT: [[V_MOV_B1:%[0-9]+]]:vreg_64_align2 = V_MOV_B64_PSEUDO 900, implicit $exec
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; CHECK-NEXT: SCRATCH_STORE_DWORDX2_SADDR killed [[V_MOV_B1]], [[S_MOV_B32_]], 16, 0, implicit $exec, implicit $flat_scr
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@ -150,8 +150,7 @@ define dso_local void @required_fp(i32 %0, i32 %1) {
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; FP-NEXT: subs r1, r3, r1
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; FP-NEXT: mov sp, r1
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; FP-NEXT: movs r1, #0
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; FP-NEXT: str r1, [r6, #4]
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; FP-NEXT: str r0, [r2]
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; FP-NEXT: stm r2!, {r0, r1}
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; FP-NEXT: subs r6, r7, #7
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; FP-NEXT: subs r6, #1
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; FP-NEXT: mov sp, r6
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@ -184,8 +183,7 @@ define dso_local void @required_fp(i32 %0, i32 %1) {
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; FP-AAPCS-NEXT: subs r1, r3, r1
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; FP-AAPCS-NEXT: mov sp, r1
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; FP-AAPCS-NEXT: movs r1, #0
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; FP-AAPCS-NEXT: str r1, [r6, #4]
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; FP-AAPCS-NEXT: str r0, [r2]
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; FP-AAPCS-NEXT: stm r2!, {r0, r1}
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; FP-AAPCS-NEXT: mov r6, r11
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; FP-AAPCS-NEXT: subs r6, #8
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; FP-AAPCS-NEXT: mov sp, r6
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@ -216,8 +214,7 @@ define dso_local void @required_fp(i32 %0, i32 %1) {
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; NOFP-NEXT: subs r1, r3, r1
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; NOFP-NEXT: mov sp, r1
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; NOFP-NEXT: movs r1, #0
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; NOFP-NEXT: str r1, [r6, #4]
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; NOFP-NEXT: str r0, [r2]
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; NOFP-NEXT: stm r2!, {r0, r1}
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; NOFP-NEXT: subs r6, r7, #7
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; NOFP-NEXT: subs r6, #1
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; NOFP-NEXT: mov sp, r6
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@ -250,8 +247,7 @@ define dso_local void @required_fp(i32 %0, i32 %1) {
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; NOFP-AAPCS-NEXT: subs r1, r3, r1
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; NOFP-AAPCS-NEXT: mov sp, r1
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; NOFP-AAPCS-NEXT: movs r1, #0
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; NOFP-AAPCS-NEXT: str r1, [r6, #4]
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; NOFP-AAPCS-NEXT: str r0, [r2]
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; NOFP-AAPCS-NEXT: stm r2!, {r0, r1}
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; NOFP-AAPCS-NEXT: mov r6, r11
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; NOFP-AAPCS-NEXT: subs r6, #8
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; NOFP-AAPCS-NEXT: mov sp, r6
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