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[RISCV] Reorder atomic pseudo instructions and isel patterns. NFC (#154835)

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Instead of interleaving the pseudo definitions and their patterns,
define all the pseudos together and all the patterns together.

Add IsRV32 predicate to the patterns.
This commit is contained in:
Craig Topper 2025-08-21 14:22:02 -07:00 committed by GitHub
parent c704dabe88
commit 04a271adf8
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GPG Key ID: B5690EEEBB952194
1 changed files with 20 additions and 17 deletions
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37
llvm/lib/Target/RISCV/RISCVInstrInfoA.td
View File

@ -304,39 +304,42 @@ def : Pat<(XLenVT (atomic_load_nand_i32_acq_rel GPR:$addr, GPR:$incr)),
def : Pat<(XLenVT (atomic_load_nand_i32_seq_cst GPR:$addr, GPR:$incr)),
(PseudoAtomicLoadNand32 GPR:$addr, GPR:$incr, 7)>;
let Size = 28 in
def PseudoMaskedAtomicSwap32 : PseudoMaskedAMO;
let Size = 28 in {
def PseudoMaskedAtomicSwap32 : PseudoMaskedAMO;
def PseudoMaskedAtomicLoadAdd32 : PseudoMaskedAMO;
def PseudoMaskedAtomicLoadSub32 : PseudoMaskedAMO;
}
let Size = 32 in {
def PseudoMaskedAtomicLoadNand32 : PseudoMaskedAMO;
}
let Size = 44 in {
def PseudoMaskedAtomicLoadMax32 : PseudoMaskedAMOMinMax;
def PseudoMaskedAtomicLoadMin32 : PseudoMaskedAMOMinMax;
}
let Size = 36 in {
def PseudoMaskedAtomicLoadUMax32 : PseudoMaskedAMOUMinUMax;
def PseudoMaskedAtomicLoadUMin32 : PseudoMaskedAMOUMinUMax;
}
} // Predicates = [HasStdExtA]
let Predicates = [HasStdExtA, IsRV32] in {
def : PseudoMaskedAMOPat<int_riscv_masked_atomicrmw_xchg_i32,
PseudoMaskedAtomicSwap32>;
let Size = 28 in
def PseudoMaskedAtomicLoadAdd32 : PseudoMaskedAMO;
def : PseudoMaskedAMOPat<int_riscv_masked_atomicrmw_add_i32,
PseudoMaskedAtomicLoadAdd32>;
let Size = 28 in
def PseudoMaskedAtomicLoadSub32 : PseudoMaskedAMO;
def : PseudoMaskedAMOPat<int_riscv_masked_atomicrmw_sub_i32,
PseudoMaskedAtomicLoadSub32>;
let Size = 32 in
def PseudoMaskedAtomicLoadNand32 : PseudoMaskedAMO;
def : PseudoMaskedAMOPat<int_riscv_masked_atomicrmw_nand_i32,
PseudoMaskedAtomicLoadNand32>;
let Size = 44 in
def PseudoMaskedAtomicLoadMax32 : PseudoMaskedAMOMinMax;
def : PseudoMaskedAMOMinMaxPat<int_riscv_masked_atomicrmw_max_i32,
PseudoMaskedAtomicLoadMax32>;
let Size = 44 in
def PseudoMaskedAtomicLoadMin32 : PseudoMaskedAMOMinMax;
def : PseudoMaskedAMOMinMaxPat<int_riscv_masked_atomicrmw_min_i32,
PseudoMaskedAtomicLoadMin32>;
let Size = 36 in
def PseudoMaskedAtomicLoadUMax32 : PseudoMaskedAMOUMinUMax;
def : PseudoMaskedAMOPat<int_riscv_masked_atomicrmw_umax_i32,
PseudoMaskedAtomicLoadUMax32>;
let Size = 36 in
def PseudoMaskedAtomicLoadUMin32 : PseudoMaskedAMOUMinUMax;
def : PseudoMaskedAMOPat<int_riscv_masked_atomicrmw_umin_i32,
PseudoMaskedAtomicLoadUMin32>;
} // Predicates = [HasStdExtA]
} // Predicates = [HasStdExtA, IsRV32]
let Predicates = [HasStdExtA, IsRV64] in {