[X86][NFC] Remove VEX_W1X after 80dbf60
This commit is contained in:
Shengchen Kan
parent
80dbf601d1
commit
04a7ec610e
@ -448,7 +448,7 @@ multiclass vinsert_for_type<ValueType EltVT32, int Opcode128,
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X86VectorVTInfo< 2, EltVT64, VR128X>,
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X86VectorVTInfo< 4, EltVT64, VR256X>,
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null_frag, vinsert128_insert, sched>,
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VEX_W1X, EVEX_V256;
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EVEX_V256, REX_W;
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// Even with DQI we'd like to only use these instructions for masking.
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let Predicates = [HasDQI] in {
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@ -750,7 +750,7 @@ multiclass vextract_for_type<ValueType EltVT32, int Opcode128,
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X86VectorVTInfo< 4, EltVT64, VR256X>,
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X86VectorVTInfo< 2, EltVT64, VR128X>,
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null_frag, vextract128_extract, SchedRR, SchedMR>,
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VEX_W1X, EVEX_V256, EVEX_CD8<64, CD8VT2>;
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EVEX_V256, EVEX_CD8<64, CD8VT2>, REX_W;
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// Even with DQI we'd like to only use these instructions for masking.
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let Predicates = [HasDQI] in {
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@ -1161,7 +1161,7 @@ multiclass avx512_fp_broadcast_ss<bits<8> opc, string OpcodeStr,
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defm VBROADCASTSS : avx512_fp_broadcast_ss<0x18, "vbroadcastss",
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avx512vl_f32_info>;
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defm VBROADCASTSD : avx512_fp_broadcast_sd<0x19, "vbroadcastsd",
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avx512vl_f64_info>, VEX_W1X;
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avx512vl_f64_info>, REX_W;
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multiclass avx512_int_broadcast_reg<bits<8> opc, SchedWrite SchedRR,
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X86VectorVTInfo _, SDPatternOperator OpNode,
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@ -1267,7 +1267,7 @@ defm VPBROADCASTW : avx512_int_broadcast_rm_vl<0x79, "vpbroadcastw",
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defm VPBROADCASTD : avx512_int_broadcast_rm_vl<0x58, "vpbroadcastd",
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avx512vl_i32_info, HasAVX512, 1>;
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defm VPBROADCASTQ : avx512_int_broadcast_rm_vl<0x59, "vpbroadcastq",
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avx512vl_i64_info, HasAVX512, 1>, VEX_W1X;
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avx512vl_i64_info, HasAVX512, 1>, REX_W;
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multiclass avx512_subvec_broadcast_rm<bits<8> opc, string OpcodeStr,
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SDPatternOperator OpNode,
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@ -1460,11 +1460,11 @@ let Predicates = [HasBF16, HasVLX] in
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let Predicates = [HasVLX, HasDQI] in {
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defm VBROADCASTI64X2Z128 : avx512_subvec_broadcast_rm_dq<0x5a, "vbroadcasti64x2",
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X86SubVBroadcastld128, v4i64x_info, v2i64x_info>, VEX_W1X,
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EVEX_V256, EVEX_CD8<64, CD8VT2>;
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X86SubVBroadcastld128, v4i64x_info, v2i64x_info>,
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EVEX_V256, EVEX_CD8<64, CD8VT2>, REX_W;
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defm VBROADCASTF64X2Z128 : avx512_subvec_broadcast_rm_dq<0x1a, "vbroadcastf64x2",
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X86SubVBroadcastld128, v4f64x_info, v2f64x_info>, VEX_W1X,
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EVEX_V256, EVEX_CD8<64, CD8VT2>;
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X86SubVBroadcastld128, v4f64x_info, v2f64x_info>,
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EVEX_V256, EVEX_CD8<64, CD8VT2>, REX_W;
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// Patterns for selects of bitcasted operations.
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def : Pat<(vselect_mask VK4WM:$mask,
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@ -6396,7 +6396,7 @@ defm VPERMILPS : avx512_permil<"vpermilps", 0x04, 0x0C, avx512vl_f32_info,
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avx512vl_i32_info>;
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let ExeDomain = SSEPackedDouble in
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defm VPERMILPD : avx512_permil<"vpermilpd", 0x05, 0x0D, avx512vl_f64_info,
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avx512vl_i64_info>, VEX_W1X;
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avx512vl_i64_info>, REX_W;
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//===----------------------------------------------------------------------===//
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// AVX-512 - VPSHUFD, VPSHUFLW, VPSHUFHW
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@ -247,8 +247,6 @@ class X86Inst<bits<8> opcod, Format f, ImmType i, dag outs, dag ins,
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bit hasREPPrefix = 0; // Does this inst have a REP prefix?
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bits<2> OpEncBits = OpEnc.Value;
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bit IgnoresW = 0; // Does this inst ignore REX_W field?
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bit EVEX_W1_VEX_W0 = 0; // This EVEX inst with VEX.W==1 can become a VEX
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// instruction with VEX.W == 0.
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bit hasVEX_4V = 0; // Does this inst require the VEX.VVVV field?
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bit hasVEX_L = 0; // Does this inst use large (256-bit) registers?
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bit ignoresVEX_L = 0; // Does this instruction ignore the L-bit
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@ -43,8 +43,6 @@ class XOP { Encoding OpEnc = EncXOP; }
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class VEX { Encoding OpEnc = EncVEX; }
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class EVEX { Encoding OpEnc = EncEVEX; }
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class WIG { bit IgnoresW = 1; }
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// Special version of REX_W that can be changed to VEX.W==0 for EVEX2VEX.
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class VEX_W1X { bit hasREX_W = 1; bit EVEX_W1_VEX_W0 = 1; }
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class VEX_L { bit hasVEX_L = 1; }
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class VEX_LIG { bit ignoresVEX_L = 1; }
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class VVVV { bit hasVEX_4V = 1; }
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@ -95,34 +95,23 @@ static inline uint64_t getValueFromBitsInit(const BitsInit *B) {
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return Value;
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}
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// Function object - Operator() returns true if the given VEX instruction
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// matches the EVEX instruction of this object.
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class IsMatch {
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const CodeGenInstruction *EVEXInst;
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const CodeGenInstruction *OldInst;
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public:
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IsMatch(const CodeGenInstruction *EVEXInst) : EVEXInst(EVEXInst) {}
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IsMatch(const CodeGenInstruction *OldInst) : OldInst(OldInst) {}
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bool operator()(const CodeGenInstruction *VEXInst) {
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RecognizableInstrBase VEXRI(*VEXInst);
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RecognizableInstrBase EVEXRI(*EVEXInst);
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bool VEX_W = VEXRI.HasREX_W;
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bool EVEX_W = EVEXRI.HasREX_W;
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bool VEX_WIG = VEXRI.IgnoresW;
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bool EVEX_WIG = EVEXRI.IgnoresW;
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bool EVEX_W1_VEX_W0 = EVEXInst->TheDef->getValueAsBit("EVEX_W1_VEX_W0");
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bool operator()(const CodeGenInstruction *NewInst) {
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RecognizableInstrBase NewRI(*NewInst);
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RecognizableInstrBase OldRI(*OldInst);
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if (VEXRI.IsCodeGenOnly != EVEXRI.IsCodeGenOnly ||
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// VEX/EVEX fields
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VEXRI.OpPrefix != EVEXRI.OpPrefix || VEXRI.OpMap != EVEXRI.OpMap ||
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VEXRI.HasVEX_4V != EVEXRI.HasVEX_4V ||
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VEXRI.HasVEX_L != EVEXRI.HasVEX_L ||
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// Match is allowed if either is VEX_WIG, or they match, or EVEX
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// is VEX_W1X and VEX is VEX_W0.
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(!(VEX_WIG || (!EVEX_WIG && EVEX_W == VEX_W) ||
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(EVEX_W1_VEX_W0 && EVEX_W && !VEX_W))) ||
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// Instruction's format
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VEXRI.Form != EVEXRI.Form)
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// Return false if any of the following fields of does not match.
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if (std::make_tuple(OldRI.IsCodeGenOnly, OldRI.OpMap, NewRI.OpPrefix,
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OldRI.HasVEX_4V, OldRI.HasVEX_L, OldRI.HasREX_W,
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OldRI.Form) !=
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std::make_tuple(NewRI.IsCodeGenOnly, NewRI.OpMap, OldRI.OpPrefix,
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NewRI.HasVEX_4V, NewRI.HasVEX_L, NewRI.HasREX_W,
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NewRI.Form))
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return false;
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// This is needed for instructions with intrinsic version (_Int).
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@ -131,9 +120,9 @@ public:
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// Also for instructions that their EVEX version was upgraded to work with
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// k-registers. For example VPCMPEQBrm (xmm output register) and
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// VPCMPEQBZ128rm (k register output register).
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for (unsigned i = 0, e = EVEXInst->Operands.size(); i < e; i++) {
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Record *OpRec1 = EVEXInst->Operands[i].Rec;
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Record *OpRec2 = VEXInst->Operands[i].Rec;
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for (unsigned i = 0, e = OldInst->Operands.size(); i < e; i++) {
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Record *OpRec1 = OldInst->Operands[i].Rec;
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Record *OpRec2 = NewInst->Operands[i].Rec;
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if (OpRec1 == OpRec2)
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continue;
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@ -374,8 +374,7 @@ public:
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RegRI.HasEVEX_L2, RegRI.HasEVEX_NF,
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RegRec->getValueAsBit("hasEVEX_RC"),
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RegRec->getValueAsBit("hasLockPrefix"),
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RegRec->getValueAsBit("hasNoTrackPrefix"),
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RegRec->getValueAsBit("EVEX_W1_VEX_W0")) !=
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RegRec->getValueAsBit("hasNoTrackPrefix")) !=
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std::make_tuple(MemRI.Encoding, MemRI.Opcode, MemRI.OpPrefix,
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MemRI.OpMap, MemRI.OpSize, MemRI.AdSize, MemRI.HasREX_W,
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MemRI.HasVEX_4V, MemRI.HasVEX_L, MemRI.IgnoresVEX_L,
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@ -383,8 +382,7 @@ public:
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MemRI.HasEVEX_L2, MemRI.HasEVEX_NF,
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MemRec->getValueAsBit("hasEVEX_RC"),
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MemRec->getValueAsBit("hasLockPrefix"),
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MemRec->getValueAsBit("hasNoTrackPrefix"),
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MemRec->getValueAsBit("EVEX_W1_VEX_W0")))
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MemRec->getValueAsBit("hasNoTrackPrefix")))
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return false;
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// Make sure the sizes of the operands of both instructions suit each other.
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@ -85,4 +85,247 @@ ENTRY(VSHUFI32X4Z256rmi, VPERM2I128rm)
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ENTRY(VSHUFI32X4Z256rri, VPERM2I128rr)
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ENTRY(VSHUFI64X2Z256rmi, VPERM2I128rm)
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ENTRY(VSHUFI64X2Z256rri, VPERM2I128rr)
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// W bit does not match
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ENTRY(VADDPDZ128rm, VADDPDrm)
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ENTRY(VADDPDZ128rr, VADDPDrr)
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ENTRY(VADDSDZrm, VADDSDrm)
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ENTRY(VADDSDZrm_Int, VADDSDrm_Int)
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ENTRY(VADDSDZrr, VADDSDrr)
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ENTRY(VADDSDZrr_Int, VADDSDrr_Int)
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ENTRY(VANDNPDZ128rm, VANDNPDrm)
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ENTRY(VANDNPDZ128rr, VANDNPDrr)
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ENTRY(VANDPDZ128rm, VANDPDrm)
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ENTRY(VANDPDZ128rr, VANDPDrr)
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ENTRY(VCOMISDZrm, VCOMISDrm)
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ENTRY(VCOMISDZrm_Int, VCOMISDrm_Int)
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ENTRY(VCOMISDZrr, VCOMISDrr)
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ENTRY(VCOMISDZrr_Int, VCOMISDrr_Int)
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ENTRY(VCVTPD2DQZ128rm, VCVTPD2DQrm)
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ENTRY(VCVTPD2DQZ128rr, VCVTPD2DQrr)
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ENTRY(VCVTPD2PSZ128rm, VCVTPD2PSrm)
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ENTRY(VCVTPD2PSZ128rr, VCVTPD2PSrr)
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ENTRY(VCVTSD2SSZrm, VCVTSD2SSrm)
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ENTRY(VCVTSD2SSZrm_Int, VCVTSD2SSrm_Int)
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ENTRY(VCVTSD2SSZrr, VCVTSD2SSrr)
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ENTRY(VCVTSD2SSZrr_Int, VCVTSD2SSrr_Int)
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ENTRY(VCVTTPD2DQZ128rm, VCVTTPD2DQrm)
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ENTRY(VCVTTPD2DQZ128rr, VCVTTPD2DQrr)
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ENTRY(VDIVPDZ128rm, VDIVPDrm)
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ENTRY(VDIVPDZ128rr, VDIVPDrr)
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ENTRY(VDIVSDZrm, VDIVSDrm)
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ENTRY(VDIVSDZrm_Int, VDIVSDrm_Int)
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ENTRY(VDIVSDZrr, VDIVSDrr)
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ENTRY(VDIVSDZrr_Int, VDIVSDrr_Int)
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ENTRY(VMAXCPDZ128rm, VMAXCPDrm)
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ENTRY(VMAXCPDZ128rr, VMAXCPDrr)
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ENTRY(VMAXCSDZrm, VMAXCSDrm)
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ENTRY(VMAXCSDZrr, VMAXCSDrr)
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ENTRY(VMAXPDZ128rm, VMAXPDrm)
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ENTRY(VMAXPDZ128rr, VMAXPDrr)
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ENTRY(VMAXSDZrm_Int, VMAXSDrm_Int)
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ENTRY(VMAXSDZrr_Int, VMAXSDrr_Int)
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ENTRY(VMINCPDZ128rm, VMINCPDrm)
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ENTRY(VMINCPDZ128rr, VMINCPDrr)
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ENTRY(VMINCSDZrm, VMINCSDrm)
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ENTRY(VMINCSDZrr, VMINCSDrr)
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ENTRY(VMINPDZ128rm, VMINPDrm)
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ENTRY(VMINPDZ128rr, VMINPDrr)
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ENTRY(VMINSDZrm_Int, VMINSDrm_Int)
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ENTRY(VMINSDZrr_Int, VMINSDrr_Int)
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ENTRY(VMOVAPDZ128mr, VMOVAPDmr)
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ENTRY(VMOVAPDZ128rm, VMOVAPDrm)
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ENTRY(VMOVAPDZ128rr, VMOVAPDrr)
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ENTRY(VMOVDDUPZ128rm, VMOVDDUPrm)
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ENTRY(VMOVDDUPZ128rr, VMOVDDUPrr)
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ENTRY(VMOVDQA64Z128mr, VMOVDQAmr)
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ENTRY(VMOVDQA64Z128rm, VMOVDQArm)
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ENTRY(VMOVDQA64Z128rr, VMOVDQArr)
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ENTRY(VMOVDQU64Z128mr, VMOVDQUmr)
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ENTRY(VMOVDQU64Z128rm, VMOVDQUrm)
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ENTRY(VMOVDQU64Z128rr, VMOVDQUrr)
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ENTRY(VMOVHPDZ128mr, VMOVHPDmr)
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ENTRY(VMOVHPDZ128rm, VMOVHPDrm)
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ENTRY(VMOVLPDZ128mr, VMOVLPDmr)
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ENTRY(VMOVLPDZ128rm, VMOVLPDrm)
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ENTRY(VMOVNTPDZ128mr, VMOVNTPDmr)
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ENTRY(VMOVPQI2QIZmr, VMOVPQI2QImr)
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ENTRY(VMOVPQI2QIZrr, VMOVPQI2QIrr)
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ENTRY(VMOVQI2PQIZrm, VMOVQI2PQIrm)
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ENTRY(VMOVSDZmr, VMOVSDmr)
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ENTRY(VMOVSDZrm, VMOVSDrm)
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ENTRY(VMOVSDZrm_alt, VMOVSDrm_alt)
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ENTRY(VMOVSDZrr, VMOVSDrr)
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ENTRY(VMOVUPDZ128mr, VMOVUPDmr)
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ENTRY(VMOVUPDZ128rm, VMOVUPDrm)
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ENTRY(VMOVUPDZ128rr, VMOVUPDrr)
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ENTRY(VMOVZPQILo2PQIZrr, VMOVZPQILo2PQIrr)
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ENTRY(VMULPDZ128rm, VMULPDrm)
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ENTRY(VMULPDZ128rr, VMULPDrr)
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ENTRY(VMULSDZrm, VMULSDrm)
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ENTRY(VMULSDZrm_Int, VMULSDrm_Int)
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ENTRY(VMULSDZrr, VMULSDrr)
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ENTRY(VMULSDZrr_Int, VMULSDrr_Int)
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ENTRY(VORPDZ128rm, VORPDrm)
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ENTRY(VORPDZ128rr, VORPDrr)
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ENTRY(VPADDQZ128rm, VPADDQrm)
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ENTRY(VPADDQZ128rr, VPADDQrr)
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ENTRY(VPANDNQZ128rm, VPANDNrm)
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ENTRY(VPANDNQZ128rr, VPANDNrr)
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ENTRY(VPANDQZ128rm, VPANDrm)
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ENTRY(VPANDQZ128rr, VPANDrr)
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ENTRY(VPERMILPDZ128mi, VPERMILPDmi)
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ENTRY(VPERMILPDZ128ri, VPERMILPDri)
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ENTRY(VPERMILPDZ128rm, VPERMILPDrm)
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ENTRY(VPERMILPDZ128rr, VPERMILPDrr)
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ENTRY(VPMULDQZ128rm, VPMULDQrm)
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ENTRY(VPMULDQZ128rr, VPMULDQrr)
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ENTRY(VPMULUDQZ128rm, VPMULUDQrm)
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ENTRY(VPMULUDQZ128rr, VPMULUDQrr)
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ENTRY(VPORQZ128rm, VPORrm)
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ENTRY(VPORQZ128rr, VPORrr)
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ENTRY(VPSLLQZ128ri, VPSLLQri)
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ENTRY(VPSLLQZ128rm, VPSLLQrm)
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ENTRY(VPSLLQZ128rr, VPSLLQrr)
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ENTRY(VPSRLQZ128ri, VPSRLQri)
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ENTRY(VPSRLQZ128rm, VPSRLQrm)
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ENTRY(VPSRLQZ128rr, VPSRLQrr)
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ENTRY(VPSUBQZ128rm, VPSUBQrm)
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ENTRY(VPSUBQZ128rr, VPSUBQrr)
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ENTRY(VPUNPCKHQDQZ128rm, VPUNPCKHQDQrm)
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ENTRY(VPUNPCKHQDQZ128rr, VPUNPCKHQDQrr)
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ENTRY(VPUNPCKLQDQZ128rm, VPUNPCKLQDQrm)
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ENTRY(VPUNPCKLQDQZ128rr, VPUNPCKLQDQrr)
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ENTRY(VPXORQZ128rm, VPXORrm)
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ENTRY(VPXORQZ128rr, VPXORrr)
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ENTRY(VRNDSCALEPDZ128rmi, VROUNDPDm)
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ENTRY(VRNDSCALEPDZ128rri, VROUNDPDr)
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ENTRY(VRNDSCALESDZm, VROUNDSDm)
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ENTRY(VRNDSCALESDZm_Int, VROUNDSDm_Int)
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ENTRY(VRNDSCALESDZr, VROUNDSDr)
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ENTRY(VRNDSCALESDZr_Int, VROUNDSDr_Int)
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ENTRY(VSHUFPDZ128rmi, VSHUFPDrmi)
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ENTRY(VSHUFPDZ128rri, VSHUFPDrri)
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ENTRY(VSQRTPDZ128m, VSQRTPDm)
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ENTRY(VSQRTPDZ128r, VSQRTPDr)
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ENTRY(VSQRTSDZm, VSQRTSDm)
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ENTRY(VSQRTSDZm_Int, VSQRTSDm_Int)
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ENTRY(VSQRTSDZr, VSQRTSDr)
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ENTRY(VSQRTSDZr_Int, VSQRTSDr_Int)
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ENTRY(VSUBPDZ128rm, VSUBPDrm)
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ENTRY(VSUBPDZ128rr, VSUBPDrr)
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ENTRY(VSUBSDZrm, VSUBSDrm)
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ENTRY(VSUBSDZrm_Int, VSUBSDrm_Int)
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ENTRY(VSUBSDZrr, VSUBSDrr)
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ENTRY(VSUBSDZrr_Int, VSUBSDrr_Int)
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ENTRY(VUCOMISDZrm, VUCOMISDrm)
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ENTRY(VUCOMISDZrm_Int, VUCOMISDrm_Int)
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ENTRY(VUCOMISDZrr, VUCOMISDrr)
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ENTRY(VUCOMISDZrr_Int, VUCOMISDrr_Int)
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ENTRY(VUNPCKHPDZ128rm, VUNPCKHPDrm)
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ENTRY(VUNPCKHPDZ128rr, VUNPCKHPDrr)
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ENTRY(VUNPCKLPDZ128rm, VUNPCKLPDrm)
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ENTRY(VUNPCKLPDZ128rr, VUNPCKLPDrr)
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ENTRY(VXORPDZ128rm, VXORPDrm)
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ENTRY(VXORPDZ128rr, VXORPDrr)
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ENTRY(VADDPDZ256rm, VADDPDYrm)
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ENTRY(VADDPDZ256rr, VADDPDYrr)
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ENTRY(VANDNPDZ256rm, VANDNPDYrm)
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ENTRY(VANDNPDZ256rr, VANDNPDYrr)
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ENTRY(VANDPDZ256rm, VANDPDYrm)
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ENTRY(VANDPDZ256rr, VANDPDYrr)
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ENTRY(VCVTPD2DQZ256rm, VCVTPD2DQYrm)
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ENTRY(VCVTPD2DQZ256rr, VCVTPD2DQYrr)
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ENTRY(VCVTPD2PSZ256rm, VCVTPD2PSYrm)
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ENTRY(VCVTPD2PSZ256rr, VCVTPD2PSYrr)
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||||
ENTRY(VCVTTPD2DQZ256rm, VCVTTPD2DQYrm)
|
||||
ENTRY(VCVTTPD2DQZ256rr, VCVTTPD2DQYrr)
|
||||
ENTRY(VDIVPDZ256rm, VDIVPDYrm)
|
||||
ENTRY(VDIVPDZ256rr, VDIVPDYrr)
|
||||
ENTRY(VEXTRACTF64x2Z256mr, VEXTRACTF128mr)
|
||||
ENTRY(VEXTRACTF64x2Z256rr, VEXTRACTF128rr)
|
||||
ENTRY(VEXTRACTI64x2Z256mr, VEXTRACTI128mr)
|
||||
ENTRY(VEXTRACTI64x2Z256rr, VEXTRACTI128rr)
|
||||
ENTRY(VINSERTF64x2Z256rm, VINSERTF128rm)
|
||||
ENTRY(VINSERTF64x2Z256rr, VINSERTF128rr)
|
||||
ENTRY(VINSERTI64x2Z256rm, VINSERTI128rm)
|
||||
ENTRY(VINSERTI64x2Z256rr, VINSERTI128rr)
|
||||
ENTRY(VMAXCPDZ256rm, VMAXCPDYrm)
|
||||
ENTRY(VMAXCPDZ256rr, VMAXCPDYrr)
|
||||
ENTRY(VMAXPDZ256rm, VMAXPDYrm)
|
||||
ENTRY(VMAXPDZ256rr, VMAXPDYrr)
|
||||
ENTRY(VMINCPDZ256rm, VMINCPDYrm)
|
||||
ENTRY(VMINCPDZ256rr, VMINCPDYrr)
|
||||
ENTRY(VMINPDZ256rm, VMINPDYrm)
|
||||
ENTRY(VMINPDZ256rr, VMINPDYrr)
|
||||
ENTRY(VMOVAPDZ256mr, VMOVAPDYmr)
|
||||
ENTRY(VMOVAPDZ256rm, VMOVAPDYrm)
|
||||
ENTRY(VMOVAPDZ256rr, VMOVAPDYrr)
|
||||
ENTRY(VMOVDDUPZ256rm, VMOVDDUPYrm)
|
||||
ENTRY(VMOVDDUPZ256rr, VMOVDDUPYrr)
|
||||
ENTRY(VMOVDQA64Z256mr, VMOVDQAYmr)
|
||||
ENTRY(VMOVDQA64Z256rm, VMOVDQAYrm)
|
||||
ENTRY(VMOVDQA64Z256rr, VMOVDQAYrr)
|
||||
ENTRY(VMOVDQU64Z256mr, VMOVDQUYmr)
|
||||
ENTRY(VMOVDQU64Z256rm, VMOVDQUYrm)
|
||||
ENTRY(VMOVDQU64Z256rr, VMOVDQUYrr)
|
||||
ENTRY(VMOVNTPDZ256mr, VMOVNTPDYmr)
|
||||
ENTRY(VMOVUPDZ256mr, VMOVUPDYmr)
|
||||
ENTRY(VMOVUPDZ256rm, VMOVUPDYrm)
|
||||
ENTRY(VMOVUPDZ256rr, VMOVUPDYrr)
|
||||
ENTRY(VMULPDZ256rm, VMULPDYrm)
|
||||
ENTRY(VMULPDZ256rr, VMULPDYrr)
|
||||
ENTRY(VORPDZ256rm, VORPDYrm)
|
||||
ENTRY(VORPDZ256rr, VORPDYrr)
|
||||
ENTRY(VPADDQZ256rm, VPADDQYrm)
|
||||
ENTRY(VPADDQZ256rr, VPADDQYrr)
|
||||
ENTRY(VPANDNQZ256rm, VPANDNYrm)
|
||||
ENTRY(VPANDNQZ256rr, VPANDNYrr)
|
||||
ENTRY(VPANDQZ256rm, VPANDYrm)
|
||||
ENTRY(VPANDQZ256rr, VPANDYrr)
|
||||
ENTRY(VPERMILPDZ256mi, VPERMILPDYmi)
|
||||
ENTRY(VPERMILPDZ256ri, VPERMILPDYri)
|
||||
ENTRY(VPERMILPDZ256rm, VPERMILPDYrm)
|
||||
ENTRY(VPERMILPDZ256rr, VPERMILPDYrr)
|
||||
ENTRY(VPMULDQZ256rm, VPMULDQYrm)
|
||||
ENTRY(VPMULDQZ256rr, VPMULDQYrr)
|
||||
ENTRY(VPMULUDQZ256rm, VPMULUDQYrm)
|
||||
ENTRY(VPMULUDQZ256rr, VPMULUDQYrr)
|
||||
ENTRY(VPORQZ256rm, VPORYrm)
|
||||
ENTRY(VPORQZ256rr, VPORYrr)
|
||||
ENTRY(VPSLLQZ256ri, VPSLLQYri)
|
||||
ENTRY(VPSLLQZ256rm, VPSLLQYrm)
|
||||
ENTRY(VPSLLQZ256rr, VPSLLQYrr)
|
||||
ENTRY(VPSRLQZ256ri, VPSRLQYri)
|
||||
ENTRY(VPSRLQZ256rm, VPSRLQYrm)
|
||||
ENTRY(VPSRLQZ256rr, VPSRLQYrr)
|
||||
ENTRY(VPSUBQZ256rm, VPSUBQYrm)
|
||||
ENTRY(VPSUBQZ256rr, VPSUBQYrr)
|
||||
ENTRY(VPUNPCKHQDQZ256rm, VPUNPCKHQDQYrm)
|
||||
ENTRY(VPUNPCKHQDQZ256rr, VPUNPCKHQDQYrr)
|
||||
ENTRY(VPUNPCKLQDQZ256rm, VPUNPCKLQDQYrm)
|
||||
ENTRY(VPUNPCKLQDQZ256rr, VPUNPCKLQDQYrr)
|
||||
ENTRY(VPXORQZ256rm, VPXORYrm)
|
||||
ENTRY(VPXORQZ256rr, VPXORYrr)
|
||||
ENTRY(VRNDSCALEPDZ256rmi, VROUNDPDYm)
|
||||
ENTRY(VRNDSCALEPDZ256rri, VROUNDPDYr)
|
||||
ENTRY(VSHUFPDZ256rmi, VSHUFPDYrmi)
|
||||
ENTRY(VSHUFPDZ256rri, VSHUFPDYrri)
|
||||
ENTRY(VSQRTPDZ256m, VSQRTPDYm)
|
||||
ENTRY(VSQRTPDZ256r, VSQRTPDYr)
|
||||
ENTRY(VSUBPDZ256rm, VSUBPDYrm)
|
||||
ENTRY(VSUBPDZ256rr, VSUBPDYrr)
|
||||
ENTRY(VUNPCKHPDZ256rm, VUNPCKHPDYrm)
|
||||
ENTRY(VUNPCKHPDZ256rr, VUNPCKHPDYrr)
|
||||
ENTRY(VUNPCKLPDZ256rm, VUNPCKLPDYrm)
|
||||
ENTRY(VUNPCKLPDZ256rr, VUNPCKLPDYrr)
|
||||
ENTRY(VXORPDZ256rm, VXORPDYrm)
|
||||
ENTRY(VXORPDZ256rr, VXORPDYrr)
|
||||
ENTRY(VPBROADCASTQZ128rm, VPBROADCASTQrm)
|
||||
ENTRY(VPBROADCASTQZ128rr, VPBROADCASTQrr)
|
||||
ENTRY(VBROADCASTF64X2Z128rm, VBROADCASTF128rm)
|
||||
ENTRY(VBROADCASTI64X2Z128rm, VBROADCASTI128rm)
|
||||
ENTRY(VBROADCASTSDZ256rm, VBROADCASTSDYrm)
|
||||
ENTRY(VBROADCASTSDZ256rr, VBROADCASTSDYrr)
|
||||
ENTRY(VPBROADCASTQZ256rm, VPBROADCASTQYrm)
|
||||
ENTRY(VPBROADCASTQZ256rr, VPBROADCASTQYrr)
|
||||
#undef ENTRY
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user