From 052d37dc7cedac9b12f0ee84191070c244e4a19f Mon Sep 17 00:00:00 2001 From: Shengchen Kan Date: Wed, 16 Mar 2022 13:01:26 +0800 Subject: [PATCH] [NFC][X86] Rename some variables and functions about target features This is preparation for D121768. The member's name should align w/ the interface for trival target feature. --- llvm/lib/Target/X86/X86.td | 16 +++---- llvm/lib/Target/X86/X86FixupLEAs.cpp | 2 +- llvm/lib/Target/X86/X86ISelLowering.cpp | 2 +- llvm/lib/Target/X86/X86InstrInfo.td | 4 +- llvm/lib/Target/X86/X86Subtarget.cpp | 8 ++-- llvm/lib/Target/X86/X86Subtarget.h | 59 +++++++++++-------------- 6 files changed, 42 insertions(+), 49 deletions(-) diff --git a/llvm/lib/Target/X86/X86.td b/llvm/lib/Target/X86/X86.td index 2a23e99715f0..f9e9021d0d92 100644 --- a/llvm/lib/Target/X86/X86.td +++ b/llvm/lib/Target/X86/X86.td @@ -19,11 +19,11 @@ include "llvm/Target/Target.td" // X86 Subtarget state // -def Mode64Bit : SubtargetFeature<"64bit-mode", "In64BitMode", "true", +def Mode64Bit : SubtargetFeature<"64bit-mode", "Is64Bit", "true", "64-bit mode (x86_64)">; -def Mode32Bit : SubtargetFeature<"32bit-mode", "In32BitMode", "true", +def Mode32Bit : SubtargetFeature<"32bit-mode", "Is32Bit", "true", "32-bit mode (80386)">; -def Mode16Bit : SubtargetFeature<"16bit-mode", "In16BitMode", "true", +def Mode16Bit : SubtargetFeature<"16bit-mode", "Is16Bit", "true", "16-bit mode (i8086)">; //===----------------------------------------------------------------------===// @@ -119,7 +119,7 @@ def FeatureFMA : SubtargetFeature<"fma", "HasFMA", "true", def FeatureF16C : SubtargetFeature<"f16c", "HasF16C", "true", "Support 16-bit floating point conversion instructions", [FeatureAVX]>; -def FeatureAVX512 : SubtargetFeature<"avx512f", "X86SSELevel", "AVX512F", +def FeatureAVX512 : SubtargetFeature<"avx512f", "X86SSELevel", "AVX512", "Enable AVX-512 instructions", [FeatureAVX2, FeatureFMA, FeatureF16C]>; def FeatureERI : SubtargetFeature<"avx512er", "HasERI", "true", @@ -396,11 +396,11 @@ def TuningSlowPMADDWD : SubtargetFeature<"slow-pmaddwd", "IsPMADDWDSlow", // FIXME: This should not apply to CPUs that do not have SSE. def TuningSlowUAMem16 : SubtargetFeature<"slow-unaligned-mem-16", - "IsUAMem16Slow", "true", + "IsUnalignedMem16Slow", "true", "Slow unaligned 16-byte memory access">; def TuningSlowUAMem32 : SubtargetFeature<"slow-unaligned-mem-32", - "IsUAMem32Slow", "true", + "IsUnalignedMem32Slow", "true", "Slow unaligned 32-byte memory access">; def TuningLEAForSP : SubtargetFeature<"lea-sp", "UseLeaForSP", "true", @@ -425,7 +425,7 @@ def TuningSlowTwoMemOps : SubtargetFeature<"slow-two-mem-ops", "SlowTwoMemOps", "true", "Two memory operand instructions are slow">; -def TuningLEAUsesAG : SubtargetFeature<"lea-uses-ag", "LEAUsesAG", "true", +def TuningLEAUsesAG : SubtargetFeature<"lea-uses-ag", "LeaUsesAG", "true", "LEA instruction needs inputs at AG stage">; def TuningSlowLEA : SubtargetFeature<"slow-lea", "SlowLEA", "true", @@ -592,7 +592,7 @@ def FeatureUseAA : SubtargetFeature<"use-aa", "UseAA", "true", //===----------------------------------------------------------------------===// // Bonnell -def ProcIntelAtom : SubtargetFeature<"", "X86ProcFamily", "IntelAtom", "">; +def ProcIntelAtom : SubtargetFeature<"", "IsAtom", "true", "Is Intel Atom processor">; //===----------------------------------------------------------------------===// // Register File Description diff --git a/llvm/lib/Target/X86/X86FixupLEAs.cpp b/llvm/lib/Target/X86/X86FixupLEAs.cpp index c31bc92faf7f..b01145809ac6 100644 --- a/llvm/lib/Target/X86/X86FixupLEAs.cpp +++ b/llvm/lib/Target/X86/X86FixupLEAs.cpp @@ -229,7 +229,7 @@ bool FixupLEAPass::runOnMachineFunction(MachineFunction &MF) { const X86Subtarget &ST = MF.getSubtarget(); bool IsSlowLEA = ST.slowLEA(); bool IsSlow3OpsLEA = ST.slow3OpsLEA(); - bool LEAUsesAG = ST.LEAusesAG(); + bool LEAUsesAG = ST.leaUsesAG(); bool OptIncDec = !ST.slowIncDec() || MF.getFunction().hasOptSize(); bool UseLEAForSP = ST.useLeaForSP(); diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 42a73cd7d839..a6e4b79b98cf 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -497,7 +497,7 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM, setOperationAction(ISD::SRL_PARTS, VT, Custom); } - if (Subtarget.hasSSEPrefetch() || Subtarget.has3DNow()) + if (Subtarget.hasSSEPrefetch() || Subtarget.hasThreeDNow()) setOperationAction(ISD::PREFETCH , MVT::Other, Legal); setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom); diff --git a/llvm/lib/Target/X86/X86InstrInfo.td b/llvm/lib/Target/X86/X86InstrInfo.td index 6ac5fb6a99db..02e10988f57f 100644 --- a/llvm/lib/Target/X86/X86InstrInfo.td +++ b/llvm/lib/Target/X86/X86InstrInfo.td @@ -879,8 +879,8 @@ def HasCMov : Predicate<"Subtarget->hasCMov()">; def NoCMov : Predicate<"!Subtarget->hasCMov()">; def HasMMX : Predicate<"Subtarget->hasMMX()">; -def Has3DNow : Predicate<"Subtarget->has3DNow()">; -def Has3DNowA : Predicate<"Subtarget->has3DNowA()">; +def Has3DNow : Predicate<"Subtarget->hasThreeDNow()">; +def Has3DNowA : Predicate<"Subtarget->hasThreeDNowA()">; def HasSSE1 : Predicate<"Subtarget->hasSSE1()">; def UseSSE1 : Predicate<"Subtarget->hasSSE1() && !Subtarget->hasAVX()">; def HasSSE2 : Predicate<"Subtarget->hasSSE2()">; diff --git a/llvm/lib/Target/X86/X86Subtarget.cpp b/llvm/lib/Target/X86/X86Subtarget.cpp index ffc736b2a193..bdb85bb5e92b 100644 --- a/llvm/lib/Target/X86/X86Subtarget.cpp +++ b/llvm/lib/Target/X86/X86Subtarget.cpp @@ -249,7 +249,7 @@ bool X86Subtarget::isLegalToCallImmediateAddr() const { // FIXME: I386 PE/COFF supports PC relative calls using IMAGE_REL_I386_REL32 // but WinCOFFObjectWriter::RecordRelocation cannot emit them. Once it does, // the following check for Win32 should be removed. - if (In64BitMode || isTargetWin32()) + if (Is64Bit || isTargetWin32()) return false; return isTargetELF() || TM.getRelocationModel() == Reloc::Static; } @@ -276,12 +276,12 @@ void X86Subtarget::initSubtargetFeatures(StringRef CPU, StringRef TuneCPU, // introduced with Intel's Nehalem/Silvermont and AMD's Family10h // micro-architectures respectively. if (hasSSE42() || hasSSE4A()) - IsUAMem16Slow = false; + IsUnalignedMem16Slow = false; LLVM_DEBUG(dbgs() << "Subtarget features: SSELevel " << X86SSELevel << ", 3DNowLevel " << X863DNowLevel << ", 64bit " << HasX86_64 << "\n"); - if (In64BitMode && !HasX86_64) + if (Is64Bit && !HasX86_64) report_fatal_error("64-bit code requested on a subtarget that doesn't " "support it!"); @@ -291,7 +291,7 @@ void X86Subtarget::initSubtargetFeatures(StringRef CPU, StringRef TuneCPU, if (StackAlignOverride) stackAlignment = *StackAlignOverride; else if (isTargetDarwin() || isTargetLinux() || isTargetKFreeBSD() || - isTargetNaCl() || In64BitMode) + isTargetNaCl() || Is64Bit) stackAlignment = Align(16); // Consume the vector width attribute or apply any target specific limit. diff --git a/llvm/lib/Target/X86/X86Subtarget.h b/llvm/lib/Target/X86/X86Subtarget.h index 3cd097d0bfb6..d5f2597164df 100644 --- a/llvm/lib/Target/X86/X86Subtarget.h +++ b/llvm/lib/Target/X86/X86Subtarget.h @@ -50,24 +50,14 @@ enum class Style { } // end namespace PICStyles class X86Subtarget final : public X86GenSubtargetInfo { - // NOTE: Do not add anything new to this list. Coarse, CPU name based flags - // are not a good idea. We should be migrating away from these. - enum X86ProcFamilyEnum { - Others, - IntelAtom - }; - enum X86SSEEnum { - NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F + NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512 }; enum X863DNowEnum { NoThreeDNow, MMX, ThreeDNow, ThreeDNowA }; - /// X86 processor family: Intel Atom, and others - X86ProcFamilyEnum X86ProcFamily = Others; - /// Which PIC style to use PICStyles::Style PICStyle; @@ -79,6 +69,9 @@ class X86Subtarget final : public X86GenSubtargetInfo { /// MMX, 3DNow, 3DNow Athlon, or none supported. X863DNowEnum X863DNowLevel = NoThreeDNow; + /// Is this a Intel Atom processor? + bool IsAtom = false; + /// True if the processor supports X87 instructions. bool HasX87 = false; @@ -223,10 +216,10 @@ class X86Subtarget final : public X86GenSubtargetInfo { bool IsPMADDWDSlow = false; /// True if unaligned memory accesses of 16-bytes are slow. - bool IsUAMem16Slow = false; + bool IsUnalignedMem16Slow = false; /// True if unaligned memory accesses of 32-bytes are slow. - bool IsUAMem32Slow = false; + bool IsUnalignedMem32Slow = false; /// True if SSE operations can have unaligned memory operands. /// This may require setting a configuration bit in the processor. @@ -322,7 +315,7 @@ class X86Subtarget final : public X86GenSubtargetInfo { /// True if the LEA instruction inputs have to be ready at address generation /// (AG) time. - bool LEAUsesAG = false; + bool LeaUsesAG = false; /// True if the LEA instruction with certain arguments is slow bool SlowLEA = false; @@ -539,13 +532,13 @@ private: unsigned RequiredVectorWidth; /// True if compiling for 64-bit, false for 16-bit or 32-bit. - bool In64BitMode = false; + bool Is64Bit = false; /// True if compiling for 32-bit, false for 16-bit or 64-bit. - bool In32BitMode = false; + bool Is32Bit = false; /// True if compiling for 16-bit, false for 32-bit or 64-bit. - bool In16BitMode = false; + bool Is16Bit = false; X86SelectionDAGInfo TSInfo; // Ordering here is important. X86InstrInfo initializes X86RegisterInfo which @@ -614,25 +607,25 @@ private: public: /// Is this x86_64? (disregarding specific ABI / programming model) bool is64Bit() const { - return In64BitMode; + return Is64Bit; } bool is32Bit() const { - return In32BitMode; + return Is32Bit; } bool is16Bit() const { - return In16BitMode; + return Is16Bit; } /// Is this x86_64 with the ILP32 programming model (x32 ABI)? bool isTarget64BitILP32() const { - return In64BitMode && (TargetTriple.isX32() || TargetTriple.isOSNaCl()); + return Is64Bit && (TargetTriple.isX32() || TargetTriple.isOSNaCl()); } /// Is this x86_64 with the LP64 programming model (standard AMD64, no x32)? bool isTarget64BitLP64() const { - return In64BitMode && (!TargetTriple.isX32() && !TargetTriple.isOSNaCl()); + return Is64Bit && (!TargetTriple.isX32() && !TargetTriple.isOSNaCl()); } PICStyles::Style getPICStyle() const { return PICStyle; } @@ -652,12 +645,12 @@ public: bool hasSSE42() const { return X86SSELevel >= SSE42; } bool hasAVX() const { return X86SSELevel >= AVX; } bool hasAVX2() const { return X86SSELevel >= AVX2; } - bool hasAVX512() const { return X86SSELevel >= AVX512F; } + bool hasAVX512() const { return X86SSELevel >= AVX512; } bool hasInt256() const { return hasAVX2(); } bool hasSSE4A() const { return HasSSE4A; } bool hasMMX() const { return X863DNowLevel >= MMX; } - bool has3DNow() const { return X863DNowLevel >= ThreeDNow; } - bool has3DNowA() const { return X863DNowLevel >= ThreeDNowA; } + bool hasThreeDNow() const { return X863DNowLevel >= ThreeDNow; } + bool hasThreeDNowA() const { return X863DNowLevel >= ThreeDNowA; } bool hasPOPCNT() const { return HasPOPCNT; } bool hasAES() const { return HasAES; } bool hasVAES() const { return HasVAES; } @@ -697,13 +690,13 @@ public: // its own CPUID bit as part of deprecating 3DNow. Intel eventually added // it and KNL has another that prefetches to L2 cache. We assume the // L1 version exists if the L2 version does. - return has3DNow() || hasPRFCHW() || hasPREFETCHWT1(); + return hasThreeDNow() || hasPRFCHW() || hasPREFETCHWT1(); } bool hasSSEPrefetch() const { // We implicitly enable these when we have a write prefix supporting cache // level OR if we have prfchw, but don't already have a read prefetch from // 3dnow. - return hasSSE1() || (hasPRFCHW() && !has3DNow()) || hasPREFETCHWT1(); + return hasSSE1() || (hasPRFCHW() && !hasThreeDNow()) || hasPREFETCHWT1(); } bool hasRDSEED() const { return HasRDSEED; } bool hasLAHFSAHF() const { return HasLAHFSAHF64 || !is64Bit(); } @@ -716,8 +709,8 @@ public: bool isSHLDSlow() const { return IsSHLDSlow; } bool isPMULLDSlow() const { return IsPMULLDSlow; } bool isPMADDWDSlow() const { return IsPMADDWDSlow; } - bool isUnalignedMem16Slow() const { return IsUAMem16Slow; } - bool isUnalignedMem32Slow() const { return IsUAMem32Slow; } + bool isUnalignedMem16Slow() const { return IsUnalignedMem16Slow; } + bool isUnalignedMem32Slow() const { return IsUnalignedMem32Slow; } bool hasSSEUnalignedMem() const { return HasSSEUnalignedMem; } bool hasCmpxchg16b() const { return HasCmpxchg16b && is64Bit(); } bool useLeaForSP() const { return UseLeaForSP; } @@ -749,7 +742,7 @@ public: bool hasSlowDivide64() const { return HasSlowDivide64; } bool padShortFunctions() const { return PadShortFunctions; } bool slowTwoMemOps() const { return SlowTwoMemOps; } - bool LEAusesAG() const { return LEAUsesAG; } + bool leaUsesAG() const { return LeaUsesAG; } bool slowLEA() const { return SlowLEA; } bool slow3OpsLEA() const { return Slow3OpsLEA; } bool slowIncDec() const { return SlowIncDec; } @@ -840,7 +833,7 @@ public: bool isXRaySupported() const override { return is64Bit(); } /// TODO: to be removed later and replaced with suitable properties - bool isAtom() const { return X86ProcFamily == IntelAtom; } + bool isAtom() const { return IsAtom; } bool useSoftFloat() const { return UseSoftFloat; } bool useAA() const override { return UseAA; } @@ -895,9 +888,9 @@ public: bool isOSWindows() const { return TargetTriple.isOSWindows(); } - bool isTargetWin64() const { return In64BitMode && isOSWindows(); } + bool isTargetWin64() const { return Is64Bit && isOSWindows(); } - bool isTargetWin32() const { return !In64BitMode && isOSWindows(); } + bool isTargetWin32() const { return !Is64Bit && isOSWindows(); } bool isPICStyleGOT() const { return PICStyle == PICStyles::Style::GOT; } bool isPICStyleRIPRel() const { return PICStyle == PICStyles::Style::RIPRel; }