[BOLT][AArch64] Support FEAT_CMPBR branch instructions. (#174972)
The Armv9.6-A compare-and-branch instructions use a short range 9-bit immediate value. They do not have a corresponding relocation type in the ABI. For now we only support them in compact code model, with diagnostics added in the LongJmp pass to ensure this condition. Some interesting edge cases we cover: - function splitting works when target is within or beyond the 1KB range of those instructions, - but doesn't work beyond the 128MB limit of the compact code model - branch inversion works with block reordering so long as the immediate value adjustments remain in bounds
This commit is contained in:
Alexandros Lamprineas
GitHub
parent
ab7a6e6b4e
commit
0584699c11
@ -1747,6 +1747,12 @@ public:
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return false;
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}
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/// AArch64 uses this to perform diagnostics in the LongJmp pass.
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virtual bool isShortRangeBranch(const MCInst &Inst) const {
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llvm_unreachable("not implemented");
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return false;
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}
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/// Receives a list of MCInst of the basic block to analyze and interpret the
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/// terminators of this basic block. TBB must be initialized with the original
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/// fall-through for this BB.
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@ -73,6 +73,13 @@ static BinaryBasicBlock *getBBAtHotColdSplitPoint(BinaryFunction &Func) {
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}
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static bool mayNeedStub(const BinaryContext &BC, const MCInst &Inst) {
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if (BC.isAArch64() && BC.MIB->isShortRangeBranch(Inst) &&
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!opts::CompactCodeModel) {
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BC.errs() << "BOLT-ERROR: short range branch not supported"
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<< " outside compact code model\n";
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BC.printInstruction(BC.errs(), Inst);
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exit(1);
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}
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return (BC.MIB->isBranch(Inst) || BC.MIB->isCall(Inst)) &&
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!BC.MIB->isIndirectBranch(Inst) && !BC.MIB->isIndirectCall(Inst);
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}
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@ -716,6 +716,55 @@ public:
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return Insts;
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}
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bool isCompAndBranch(const MCInst &Inst) const {
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const unsigned Opcode = Inst.getOpcode();
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switch (Opcode) {
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// Compare register with immediate and branch.
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case AArch64::CBGTWri:
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case AArch64::CBGTXri:
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case AArch64::CBLTWri:
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case AArch64::CBLTXri:
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case AArch64::CBHIWri:
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case AArch64::CBHIXri:
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case AArch64::CBLOWri:
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case AArch64::CBLOXri:
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case AArch64::CBEQWri:
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case AArch64::CBEQXri:
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case AArch64::CBNEWri:
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case AArch64::CBNEXri:
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// Compare registers and branch.
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case AArch64::CBGTWrr:
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case AArch64::CBGTXrr:
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case AArch64::CBGEWrr:
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case AArch64::CBGEXrr:
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case AArch64::CBHIWrr:
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case AArch64::CBHIXrr:
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case AArch64::CBHSWrr:
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case AArch64::CBHSXrr:
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case AArch64::CBEQWrr:
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case AArch64::CBEQXrr:
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case AArch64::CBNEWrr:
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case AArch64::CBNEXrr:
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// Compare bytes and branch.
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case AArch64::CBBGTWrr:
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case AArch64::CBBGEWrr:
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case AArch64::CBBHIWrr:
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case AArch64::CBBHSWrr:
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case AArch64::CBBEQWrr:
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case AArch64::CBBNEWrr:
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// Compare halfwords and branch.
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case AArch64::CBHGTWrr:
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case AArch64::CBHGEWrr:
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case AArch64::CBHHIWrr:
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case AArch64::CBHHSWrr:
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case AArch64::CBHEQWrr:
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case AArch64::CBHNEWrr:
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return true;
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default:
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return false;
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}
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}
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bool isTB(const MCInst &Inst) const {
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return (Inst.getOpcode() == AArch64::TBNZW ||
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Inst.getOpcode() == AArch64::TBNZX ||
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@ -1260,7 +1309,7 @@ public:
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if (isConditionalBranch(Inst) || isADR(Inst) || isADRP(Inst) ||
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isMOVW(Inst))
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OpNum = 1;
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if (isTB(Inst) || isAddXri(Inst))
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if (isTB(Inst) || isAddXri(Inst) || isCompAndBranch(Inst))
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OpNum = 2;
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}
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@ -1329,7 +1378,7 @@ public:
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++OI;
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}
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if (isTB(Inst)) {
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if (isTB(Inst) || isCompAndBranch(Inst)) {
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assert(MCPlus::getNumPrimeOperands(Inst) >= 3 &&
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"Invalid number of operands");
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OI = Inst.begin() + 2;
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@ -1798,6 +1847,7 @@ public:
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}
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unsigned getInvertedBranchOpcode(unsigned Opcode) const {
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// clang-format off
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switch (Opcode) {
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default:
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llvm_unreachable("Failed to invert branch opcode");
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@ -1810,7 +1860,48 @@ public:
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case AArch64::CBZX: return AArch64::CBNZX;
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case AArch64::CBNZW: return AArch64::CBZW;
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case AArch64::CBNZX: return AArch64::CBZX;
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// Compare register with immediate and branch.
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case AArch64::CBGTWri: return AArch64::CBLTWri; // +1
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case AArch64::CBGTXri: return AArch64::CBLTXri; // +1
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case AArch64::CBLTWri: return AArch64::CBGTWri; // -1
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case AArch64::CBLTXri: return AArch64::CBGTXri; // -1
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case AArch64::CBHIWri: return AArch64::CBLOWri; // +1
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case AArch64::CBHIXri: return AArch64::CBLOXri; // +1
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case AArch64::CBLOWri: return AArch64::CBHIWri; // -1
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case AArch64::CBLOXri: return AArch64::CBHIXri; // -1
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case AArch64::CBEQWri: return AArch64::CBNEWri;
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case AArch64::CBEQXri: return AArch64::CBNEXri;
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case AArch64::CBNEWri: return AArch64::CBEQWri;
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case AArch64::CBNEXri: return AArch64::CBEQXri;
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// Compare registers and branch.
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case AArch64::CBGTWrr: return AArch64::CBGEWrr; // swap
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case AArch64::CBGTXrr: return AArch64::CBGEXrr; // swap
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case AArch64::CBGEWrr: return AArch64::CBGTWrr; // swap
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case AArch64::CBGEXrr: return AArch64::CBGTXrr; // swap
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case AArch64::CBHIWrr: return AArch64::CBHSWrr; // swap
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case AArch64::CBHIXrr: return AArch64::CBHSXrr; // swap
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case AArch64::CBHSWrr: return AArch64::CBHIWrr; // swap
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case AArch64::CBHSXrr: return AArch64::CBHIXrr; // swap
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case AArch64::CBEQWrr: return AArch64::CBNEWrr;
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case AArch64::CBEQXrr: return AArch64::CBNEXrr;
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case AArch64::CBNEWrr: return AArch64::CBEQWrr;
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case AArch64::CBNEXrr: return AArch64::CBEQXrr;
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// Compare bytes and branch.
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case AArch64::CBBGTWrr: return AArch64::CBBGEWrr; // swap
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case AArch64::CBBGEWrr: return AArch64::CBBGTWrr; // swap
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case AArch64::CBBHIWrr: return AArch64::CBBHSWrr; // swap
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case AArch64::CBBHSWrr: return AArch64::CBBHIWrr; // swap
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case AArch64::CBBEQWrr: return AArch64::CBBNEWrr;
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case AArch64::CBBNEWrr: return AArch64::CBBEQWrr;
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// Compare halfwords and branch.
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case AArch64::CBHGTWrr: return AArch64::CBHGEWrr; // swap
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case AArch64::CBHGEWrr: return AArch64::CBHGTWrr; // swap
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case AArch64::CBHHIWrr: return AArch64::CBHHSWrr; // swap
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case AArch64::CBHHSWrr: return AArch64::CBHHIWrr; // swap
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case AArch64::CBHEQWrr: return AArch64::CBHNEWrr;
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case AArch64::CBHNEWrr: return AArch64::CBHEQWrr;
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}
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// clang-format on
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}
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unsigned getCondCode(const MCInst &Inst) const override {
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@ -1830,11 +1921,89 @@ public:
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}
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}
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bool needsRegSwap(unsigned Opcode) const {
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switch (Opcode) {
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default:
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return false;
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// Compare registers and branch.
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case AArch64::CBGTWrr:
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case AArch64::CBGTXrr:
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case AArch64::CBGEWrr:
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case AArch64::CBGEXrr:
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case AArch64::CBHIWrr:
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case AArch64::CBHIXrr:
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case AArch64::CBHSWrr:
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case AArch64::CBHSXrr:
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// Compare bytes and branch.
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case AArch64::CBBGTWrr:
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case AArch64::CBBGEWrr:
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case AArch64::CBBHIWrr:
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case AArch64::CBBHSWrr:
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// Compare halfwords and branch.
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case AArch64::CBHGTWrr:
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case AArch64::CBHGEWrr:
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case AArch64::CBHHIWrr:
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case AArch64::CBHHSWrr:
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return true;
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}
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}
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bool needsImmDec(unsigned Opcode) const {
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switch (Opcode) {
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default:
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return false;
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case AArch64::CBGTWri:
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case AArch64::CBGTXri:
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case AArch64::CBHIWri:
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case AArch64::CBHIXri:
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return true;
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}
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}
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bool needsImmInc(unsigned Opcode) const {
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switch (Opcode) {
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default:
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return false;
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case AArch64::CBLTWri:
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case AArch64::CBLTXri:
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case AArch64::CBLOWri:
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case AArch64::CBLOXri:
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return true;
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}
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}
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bool isReversibleBranch(const MCInst &Inst) const override {
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if (isCompAndBranch(Inst)) {
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unsigned InvertedOpcode = getInvertedBranchOpcode(Inst.getOpcode());
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if (needsImmDec(InvertedOpcode) && Inst.getOperand(1).getImm() == 0)
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return false;
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if (needsImmInc(InvertedOpcode) && Inst.getOperand(1).getImm() == 63)
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return false;
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}
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return MCPlusBuilder::isReversibleBranch(Inst);
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}
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void reverseBranchCondition(MCInst &Inst, const MCSymbol *TBB,
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MCContext *Ctx) const override {
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if (isTB(Inst) || isCB(Inst)) {
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Inst.setOpcode(getInvertedBranchOpcode(Inst.getOpcode()));
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if (!isReversibleBranch(Inst)) {
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errs() << "BOLT-ERROR: Cannot reverse branch " << Inst << "\n";
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exit(1);
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}
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if (isTB(Inst) || isCB(Inst) || isCompAndBranch(Inst)) {
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unsigned InvertedOpcode = getInvertedBranchOpcode(Inst.getOpcode());
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Inst.setOpcode(InvertedOpcode);
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assert(Inst.getOpcode() != 0 && "Invalid branch instruction");
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// The FEAT_CMPBR compare-and-branch instructions cannot encode all
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// the possible condition codes, therefore we either have to adjust
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// the immediate value by +-1, or to swap the register operands
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// when reversing the branch condition.
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if (needsRegSwap(InvertedOpcode))
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std::swap(Inst.getOperand(0), Inst.getOperand(1));
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else if (needsImmDec(InvertedOpcode))
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Inst.getOperand(1).setImm(Inst.getOperand(1).getImm() - 1);
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else if (needsImmInc(InvertedOpcode))
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Inst.getOperand(1).setImm(Inst.getOperand(1).getImm() + 1);
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} else if (Inst.getOpcode() == AArch64::Bcc) {
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Inst.getOperand(0).setImm(AArch64CC::getInvertedCondCode(
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static_cast<AArch64CC::CondCode>(Inst.getOperand(0).getImm())));
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@ -1849,18 +2018,16 @@ public:
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}
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int getPCRelEncodingSize(const MCInst &Inst) const override {
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if (isCompAndBranch(Inst))
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return 11;
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if (isTB(Inst))
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return 16;
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if (isCB(Inst))
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return 21;
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switch (Inst.getOpcode()) {
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default:
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llvm_unreachable("Failed to get pcrel encoding size");
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return 0;
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case AArch64::TBZW: return 16;
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case AArch64::TBZX: return 16;
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case AArch64::TBNZW: return 16;
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case AArch64::TBNZX: return 16;
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case AArch64::CBZW: return 21;
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case AArch64::CBZX: return 21;
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case AArch64::CBNZW: return 21;
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case AArch64::CBNZX: return 21;
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case AArch64::B: return 28;
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case AArch64::BL: return 28;
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case AArch64::Bcc: return 21;
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@ -2242,6 +2409,10 @@ public:
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convertJmpToTailCall(Inst);
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}
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bool isShortRangeBranch(const MCInst &Inst) const override {
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return isCompAndBranch(Inst);
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}
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bool analyzeBranch(InstructionIterator Begin, InstructionIterator End,
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const MCSymbol *&TBB, const MCSymbol *&FBB,
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MCInst *&CondBranch,
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108
bolt/test/AArch64/compare-and-branch-inversion.S
Normal file
108
bolt/test/AArch64/compare-and-branch-inversion.S
Normal file
@ -0,0 +1,108 @@
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# This test checks that branch inversion works when reordering blocks which
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# contain short range conditional branches. Handles edge cases, like when
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# the immediate value is the upper or lower allowed value in which case the
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# transformation bails.
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# REQUIRES: system-linux, asserts
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# RUN: %clang %cflags -march=armv9-a+cmpbr -Wl,-q %s -o %t
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# RUN: link_fdata --no-lbr %s %t %t.fdata
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# RUN: llvm-bolt -v=1 %t -o %t.bolt --data %t.fdata --reorder-blocks=ext-tsp --compact-code-model \
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# RUN: | FileCheck %s --check-prefix=BOLT-INFO
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# RUN: llvm-objdump -d %t.bolt | FileCheck %s
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# CHECK: Disassembly of section .text:
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.globl immediate_increment
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.type immediate_increment, %function
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immediate_increment:
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.entry0:
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# FDATA: 1 immediate_increment #.entry0# 10
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cbgt x0, #0, .exit0
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.cold0:
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# FDATA: 1 immediate_increment #.cold0# 1
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mov x0, #1
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ret
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.exit0:
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# FDATA: 1 immediate_increment #.exit0# 10
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mov x0, #2
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ret
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# CHECK: <immediate_increment>:
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# CHECK-NEXT: {{.*}} cblt x0, #0x1, 0x[[ADDR0:[0-9a-f]+]] <{{.*}}>
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# CHECK-NEXT: {{.*}} mov x0, #0x2 // =2
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# CHECK-NEXT: {{.*}} ret
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# CHECK-NEXT: [[ADDR0]]: {{.*}} mov x0, #0x1 // =1
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# CHECK-NEXT: {{.*}} ret
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.globl immediate_decrement
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.type immediate_decrement, %function
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immediate_decrement:
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.entry1:
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# FDATA: 1 immediate_decrement #.entry1# 10
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cblo x0, #1, .exit1
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.cold1:
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# FDATA: 1 immediate_decrement #.cold1# 1
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mov x0, #1
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ret
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.exit1:
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# FDATA: 1 immediate_decrement #.exit1# 10
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mov x0, #2
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ret
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# CHECK: <immediate_decrement>:
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# CHECK-NEXT: {{.*}} cbhi x0, #0x0, 0x[[ADDR1:[0-9a-f]+]] <{{.*}}>
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# CHECK-NEXT: {{.*}} mov x0, #0x2 // =2
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# CHECK-NEXT: {{.*}} ret
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# CHECK-NEXT: [[ADDR1]]: {{.*}} mov x0, #0x1 // =1
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# CHECK-NEXT: {{.*}} ret
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.globl register_swap
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.type register_swap, %function
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register_swap:
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.entry2:
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# FDATA: 1 register_swap #.entry2# 10
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cbge x0, x1, .exit2
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.cold2:
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# FDATA: 1 register_swap #.cold2# 1
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mov x0, #1
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ret
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.exit2:
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# FDATA: 1 register_swap #.exit2# 10
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mov x0, #2
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ret
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# CHECK: <register_swap>:
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# CHECK-NEXT: {{.*}} cbgt x1, x0, 0x[[ADDR2:[0-9a-f]+]] <{{.*}}>
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# CHECK-NEXT: {{.*}} mov x0, #0x2 // =2
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# CHECK-NEXT: {{.*}} ret
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# CHECK-NEXT: [[ADDR2]]: {{.*}} mov x0, #0x1 // =1
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# CHECK-NEXT: {{.*}} ret
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.globl irreversible
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.type irreversible, %function
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irreversible:
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.entry3:
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# FDATA: 1 irreversible #.entry3# 10
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cbgt x0, #63, .exit3
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.cold3:
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# FDATA: 1 irreversible #.cold3# 1
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mov x0, #1
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ret
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.exit3:
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# FDATA: 1 irreversible #.exit3# 10
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mov x0, #2
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ret
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# BOLT-INFO: unable to swap successors in irreversible
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# CHECK: <irreversible>:
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# CHECK-NEXT: {{.*}} cbgt x0, #0x3f, 0x[[ADDR3:[0-9a-f]+]] <{{.*}}>
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# CHECK-NEXT: {{.*}} b 0x[[ADDR4:[0-9a-f]+]] <{{.*}}>
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# CHECK-NEXT: [[ADDR3]]: {{.*}} mov x0, #0x2 // =2
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# CHECK-NEXT: {{.*}} ret
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# CHECK-NEXT: [[ADDR4]]: {{.*}} mov x0, #0x1 // =1
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# CHECK-NEXT: {{.*}} ret
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## Force relocation mode.
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.reloc 0, R_AARCH64_NONE
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49
bolt/test/AArch64/compare-and-branch-reorder-blocks.S
Normal file
49
bolt/test/AArch64/compare-and-branch-reorder-blocks.S
Normal file
@ -0,0 +1,49 @@
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# This test checks that reordering blocks which contain short range
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# conditional branches may break if the target goes out of range.
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# REQUIRES: system-linux, asserts
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# RUN: %clang %cflags -march=armv9-a+cmpbr -Wl,-q %s -o %t -DNUM_NOPS=0
|
||||
# RUN: link_fdata --no-lbr %s %t %t.fdata
|
||||
# RUN: llvm-bolt %t -o %t.bolt --data %t.fdata --reorder-blocks=ext-tsp --compact-code-model
|
||||
# RUN: llvm-objdump -d %t.bolt | FileCheck %s
|
||||
|
||||
# RUN: %clang %cflags -march=armv9-a+cmpbr -Wl,-q %s -o %t -DNUM_NOPS=256
|
||||
# RUN: link_fdata --no-lbr %s %t %t.fdata
|
||||
# RUN: not llvm-bolt %t -o %t.bolt --data %t.fdata --reorder-blocks=ext-tsp --compact-code-model --keep-nops 2>&1 \
|
||||
# RUN: | FileCheck %s --check-prefix=FIXUP_OUT_OF_RANGE
|
||||
|
||||
.globl reorder_blocks
|
||||
.type reorder_blocks, %function
|
||||
reorder_blocks:
|
||||
.entry:
|
||||
# FDATA: 1 reorder_blocks #.entry# 10
|
||||
cbgt x0, #0, .cold_exit
|
||||
.fall_through:
|
||||
# FDATA: 1 reorder_blocks #.fall_through# 10
|
||||
b .hot_exit
|
||||
.cold_exit:
|
||||
# FDATA: 1 reorder_blocks #.cold_exit# 1
|
||||
mov x0, #1
|
||||
ret
|
||||
.hot_exit:
|
||||
# FDATA: 1 reorder_blocks #.hot_exit# 10
|
||||
.rept NUM_NOPS
|
||||
nop
|
||||
.endr
|
||||
mov x0, #2
|
||||
ret
|
||||
|
||||
## Force relocation mode.
|
||||
.reloc 0, R_AARCH64_NONE
|
||||
|
||||
# CHECK: Disassembly of section .text:
|
||||
|
||||
# CHECK: <reorder_blocks>:
|
||||
# CHECK-NEXT: {{.*}} cbgt x0, #0x0, 0x[[ADDR:[0-9a-f]+]] <{{.*}}>
|
||||
# CHECK-NEXT: {{.*}} mov x0, #0x2 // =2
|
||||
# CHECK-NEXT: {{.*}} ret
|
||||
# CHECK-NEXT: [[ADDR]]: {{.*}} mov x0, #0x1 // =1
|
||||
# CHECK-NEXT: {{.*}} ret
|
||||
|
||||
# FIXUP_OUT_OF_RANGE: error: fixup value out of range
|
||||
62
bolt/test/AArch64/compare-and-branch-split-functions.S
Normal file
62
bolt/test/AArch64/compare-and-branch-split-functions.S
Normal file
@ -0,0 +1,62 @@
|
||||
# This test checks that splitting functions which contain short range
|
||||
# conditional branches works in compact code model without relying on
|
||||
# relocations.
|
||||
|
||||
# REQUIRES: system-linux, asserts
|
||||
|
||||
# RUN: %clang %cflags -march=armv9-a+cmpbr -Wl,-q %s -o %t -DNUM_NOPS=0 -DRESERVE_SPACE=0
|
||||
# RUN: link_fdata --no-lbr %s %t %t.fdata
|
||||
# RUN: llvm-bolt %t -o %t.bolt --data %t.fdata -split-functions --compact-code-model
|
||||
# RUN: llvm-objdump -d %t.bolt | FileCheck %s
|
||||
|
||||
# RUN: %clang %cflags -march=armv9-a+cmpbr -Wl,-q %s -o %t -DNUM_NOPS=256 -DRESERVE_SPACE=0
|
||||
# RUN: link_fdata --no-lbr %s %t %t.fdata
|
||||
# RUN: llvm-bolt %t -o %t.bolt --data %t.fdata -split-functions --compact-code-model --keep-nops
|
||||
# RUN: llvm-objdump -d %t.bolt | FileCheck %s
|
||||
|
||||
# RUN: %clang %cflags -march=armv9-a+cmpbr -Wl,-q %s -o %t -DNUM_NOPS=0 -DRESERVE_SPACE=1
|
||||
# RUN: link_fdata --no-lbr %s %t %t.fdata
|
||||
# RUN: not llvm-bolt %t -o %t.bolt --data %t.fdata -split-functions --compact-code-model 2>&1 \
|
||||
# RUN: | FileCheck %s --check-prefix=BEYOND-128MB
|
||||
|
||||
.globl foo
|
||||
.type foo, %function
|
||||
foo:
|
||||
.entry_foo:
|
||||
# FDATA: 1 foo #.entry_foo# 10
|
||||
cbgt x0, #0, .Lcold_foo
|
||||
mov x0, #1
|
||||
.Lcold_foo:
|
||||
ret
|
||||
|
||||
.globl large_function
|
||||
.type large_function, %function
|
||||
large_function:
|
||||
.entry_large_function:
|
||||
# FDATA: 1 large_function #.entry_large_function# 10
|
||||
.rept NUM_NOPS
|
||||
nop
|
||||
.endr
|
||||
ret
|
||||
|
||||
.if RESERVE_SPACE
|
||||
.space 0x8000000
|
||||
.endif
|
||||
|
||||
## Force relocation mode.
|
||||
.reloc 0, R_AARCH64_NONE
|
||||
|
||||
# CHECK: Disassembly of section .text:
|
||||
|
||||
# CHECK: <foo>:
|
||||
# CHECK-NEXT: {{.*}} cbgt x0, #0x0, 0x[[ADDR0:[0-9a-f]+]] <{{.*}}>
|
||||
# CHECK-NEXT: {{.*}} b 0x[[ADDR1:[0-9a-f]+]] <{{.*}}>
|
||||
# CHECK-NEXT: [[ADDR0]]: {{.*}} b 0x[[ADDR2:[0-9a-f]+]] <{{.*}}>
|
||||
|
||||
# CHECK: Disassembly of section .text.cold:
|
||||
|
||||
# CHECK: <foo.cold.0>:
|
||||
# CHECK-NEXT: [[ADDR1]]: {{.*}} mov x0, #0x1 // =1
|
||||
# CHECK-NEXT: [[ADDR2]]: {{.*}} ret
|
||||
|
||||
# BEYOND-128MB: BOLT-ERROR: JITLink failed: In graph in-memory object file, section .text: relocation target {{0x[0-9a-f]+}} (<anonymous symbol>) is out of range of Branch26PCRel fixup at address {{0x[0-9a-f]+}}
|
||||
48
bolt/test/AArch64/compare-and-branch-unsupported.S
Normal file
48
bolt/test/AArch64/compare-and-branch-unsupported.S
Normal file
@ -0,0 +1,48 @@
|
||||
# This test checks that splitting functions which contain short range
|
||||
# conditional branches does not work outside compact code model.
|
||||
|
||||
# REQUIRES: system-linux, asserts
|
||||
|
||||
# RUN: %clang %cflags -march=armv9-a+cmpbr -Wl,-q %s -o %t -DNUM_NOPS=0 -DRESERVE_SPACE=0
|
||||
# RUN: link_fdata --no-lbr %s %t %t.fdata
|
||||
# RUN: not llvm-bolt %t -o %t.bolt --data %t.fdata -split-functions 2>&1 \
|
||||
# RUN: | FileCheck %s
|
||||
|
||||
# RUN: %clang %cflags -march=armv9-a+cmpbr -Wl,-q %s -o %t -DNUM_NOPS=256 -DRESERVE_SPACE=0
|
||||
# RUN: link_fdata --no-lbr %s %t %t.fdata
|
||||
# RUN: not llvm-bolt %t -o %t.bolt --data %t.fdata -split-functions --keep-nops 2>&1 \
|
||||
# RUN: | FileCheck %s
|
||||
|
||||
# RUN: %clang %cflags -march=armv9-a+cmpbr -Wl,-q %s -o %t -DNUM_NOPS=0 -DRESERVE_SPACE=1
|
||||
# RUN: link_fdata --no-lbr %s %t %t.fdata
|
||||
# RUN: not llvm-bolt %t -o %t.bolt --data %t.fdata -split-functions 2>&1 \
|
||||
# RUN: | FileCheck %s
|
||||
|
||||
.globl foo
|
||||
.type foo, %function
|
||||
foo:
|
||||
.entry_foo:
|
||||
# FDATA: 1 foo #.entry_foo# 10
|
||||
cbgt x0, #0, .Lcold_foo
|
||||
mov x0, #1
|
||||
.Lcold_foo:
|
||||
ret
|
||||
|
||||
.globl large_function
|
||||
.type large_function, %function
|
||||
large_function:
|
||||
.entry_large_function:
|
||||
# FDATA: 1 large_function #.entry_large_function# 10
|
||||
.rept NUM_NOPS
|
||||
nop
|
||||
.endr
|
||||
ret
|
||||
|
||||
.if RESERVE_SPACE
|
||||
.space 0x8000000
|
||||
.endif
|
||||
|
||||
## Force relocation mode.
|
||||
.reloc 0, R_AARCH64_NONE
|
||||
|
||||
# CHECK: BOLT-ERROR: short range branch not supported outside compact code model
|
||||
Loading…
x
Reference in New Issue
Block a user