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[RISCV] Use correct register class for Z[df]inx inline asm (#71872)

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Allocate a register of the correct register class for inline asm
constraint "r" when used for FP values with -Zfinx/-Zdinx.

---------

Co-authored-by: Nemanja Ivanovic <nemanja@synopsys.com>
This commit is contained in:
Nemanja Ivanovic 2023-11-17 16:17:48 +01:00 committed by GitHub
parent 06effaf43e
commit 0765f6451f
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2 changed files with 64 additions and 0 deletions
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6
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
View File

@ -18305,6 +18305,12 @@ RISCVTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
// TODO: Support fixed vectors up to XLen for P extension?
if (VT.isVector())
break;
if (VT == MVT::f16 && Subtarget.hasStdExtZhinxOrZhinxmin())
return std::make_pair(0U, &RISCV::GPRF16RegClass);
if (VT == MVT::f32 && Subtarget.hasStdExtZfinx())
return std::make_pair(0U, &RISCV::GPRF32RegClass);
if (VT == MVT::f64 && Subtarget.hasStdExtZdinx() && !Subtarget.is64Bit())
return std::make_pair(0U, &RISCV::GPRPF64RegClass);
return std::make_pair(0U, &RISCV::GPRNoX0RegClass);
case 'f':
if (Subtarget.hasStdExtZfhOrZfhmin() && VT == MVT::f16)

58
llvm/test/CodeGen/RISCV/zdinx-asm-constraint.ll Normal file
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@ -0,0 +1,58 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
; RUN: llc -mtriple=riscv32 -mattr=+zdinx -verify-machineinstrs < %s \
; RUN: -target-abi=ilp32 -mattr=+zhinx | FileCheck %s
define dso_local void @zdinx_asm(ptr nocapture noundef writeonly %a, double noundef %b, double noundef %c) nounwind {
; CHECK-LABEL: zdinx_asm:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 8(sp)
; CHECK-NEXT: sw a2, 12(sp)
; CHECK-NEXT: lw a6, 8(sp)
; CHECK-NEXT: lw a7, 12(sp)
; CHECK-NEXT: sw a3, 8(sp)
; CHECK-NEXT: sw a4, 12(sp)
; CHECK-NEXT: lw a2, 8(sp)
; CHECK-NEXT: lw a3, 12(sp)
; CHECK-NEXT: #APP
; CHECK-NEXT: fsgnjx.d a2, a6, a2
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: sw a2, 8(a0)
; CHECK-NEXT: sw a3, 12(a0)
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
%arrayidx = getelementptr inbounds double, ptr %a, i32 1
%0 = tail call double asm "fsgnjx.d $0, $1, $2", "=r,r,r"(double %b, double %c)
store double %0, ptr %arrayidx, align 8
ret void
}
define dso_local void @zfinx_asm(ptr nocapture noundef writeonly %a, float noundef %b, float noundef %c) nounwind {
; CHECK-LABEL: zfinx_asm:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: #APP
; CHECK-NEXT: fsgnjx.s a1, a1, a2
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: sw a1, 4(a0)
; CHECK-NEXT: ret
entry:
%arrayidx = getelementptr inbounds float, ptr %a, i32 1
%0 = tail call float asm "fsgnjx.s $0, $1, $2", "=r,r,r"(float %b, float %c)
store float %0, ptr %arrayidx, align 8
ret void
}
define dso_local void @zhinx_asm(ptr nocapture noundef writeonly %a, half noundef %b, half noundef %c) nounwind {
; CHECK-LABEL: zhinx_asm:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: #APP
; CHECK-NEXT: fsgnjx.h a1, a1, a2
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: sh a1, 2(a0)
; CHECK-NEXT: ret
entry:
%arrayidx = getelementptr inbounds half, ptr %a, i32 1
%0 = tail call half asm "fsgnjx.h $0, $1, $2", "=r,r,r"(half %b, half %c)
store half %0, ptr %arrayidx, align 8
ret void
}