[OpenMP] Emit aggregate kernel prototypes and remove libffi dependency (#186261)
Summary: This PR changes the handling of the emitted kernels when targeting a CPU to be a pointer struct. The old handling emitted a standard function prototype, this necessitated a target specific ABI to call it because the signature differed with the number of arguments. Instead, this PR emits a void pointer to a naturally aligned struct, this is what APIs like `pthreads` assert. This allows us to remove all the complexity around launching host kernels and just pass the argument list.
This commit is contained in:
Joseph Huber
GitHub
parent
60db764b90
commit
07896d44a3
@ -6372,11 +6372,13 @@ void CGOpenMPRuntime::emitTargetOutlinedFunctionHelper(
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CodeGenFunction CGF(CGM, true);
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llvm::OpenMPIRBuilder::FunctionGenCallback &&GenerateOutlinedFunction =
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[&CGF, &D, &CodeGen](StringRef EntryFnName) {
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[&CGF, &D, &CodeGen, this](StringRef EntryFnName) {
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const CapturedStmt &CS = *D.getCapturedStmt(OMPD_target);
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CGOpenMPTargetRegionInfo CGInfo(CS, CodeGen, EntryFnName);
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CodeGenFunction::CGCapturedStmtRAII CapInfoRAII(CGF, &CGInfo);
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if (CGM.getLangOpts().OpenMPIsTargetDevice && !isGPU())
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return CGF.GenerateOpenMPCapturedStmtFunctionAggregate(CS, D);
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return CGF.GenerateOpenMPCapturedStmtFunction(CS, D);
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};
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@ -695,6 +695,112 @@ static llvm::Function *emitOutlinedFunctionPrologue(
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return F;
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}
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static llvm::Function *emitOutlinedFunctionPrologueAggregate(
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CodeGenFunction &CGF, FunctionArgList &Args,
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llvm::MapVector<const Decl *, std::pair<const VarDecl *, Address>>
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&LocalAddrs,
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llvm::DenseMap<const Decl *, std::pair<const Expr *, llvm::Value *>>
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&VLASizes,
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llvm::Value *&CXXThisValue, llvm::Value *&ContextV, const CapturedStmt &CS,
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SourceLocation Loc, StringRef FunctionName) {
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const CapturedDecl *CD = CS.getCapturedDecl();
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const RecordDecl *RD = CS.getCapturedRecordDecl();
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CXXThisValue = nullptr;
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CodeGenModule &CGM = CGF.CGM;
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ASTContext &Ctx = CGM.getContext();
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Args.push_back(CD->getContextParam());
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const CGFunctionInfo &FuncInfo =
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CGM.getTypes().arrangeBuiltinFunctionDeclaration(Ctx.VoidTy, Args);
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llvm::FunctionType *FuncLLVMTy = CGM.getTypes().GetFunctionType(FuncInfo);
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auto *F =
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llvm::Function::Create(FuncLLVMTy, llvm::GlobalValue::InternalLinkage,
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FunctionName, &CGM.getModule());
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CGM.SetInternalFunctionAttributes(CD, F, FuncInfo);
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if (CD->isNothrow())
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F->setDoesNotThrow();
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F->setDoesNotRecurse();
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CGF.StartFunction(CD, Ctx.VoidTy, F, FuncInfo, Args, Loc, Loc);
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Address ContextAddr = CGF.GetAddrOfLocalVar(CD->getContextParam());
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ContextV = CGF.Builder.CreateLoad(ContextAddr);
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// The runtime passes arguments as a flat array of promoted intptr_t values.
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llvm::Type *IntPtrTy = CGF.IntPtrTy;
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llvm::Type *PtrTy = CGF.Builder.getPtrTy();
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llvm::Align PtrAlign = CGM.getDataLayout().getPointerABIAlignment(0);
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CharUnits SlotAlign = CharUnits::fromQuantity(PtrAlign.value());
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for (auto [FD, C, FieldIdx] :
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llvm::zip(RD->fields(), CS.captures(),
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llvm::seq<unsigned>(RD->getNumFields()))) {
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llvm::Value *Slot =
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CGF.Builder.CreateConstInBoundsGEP1_32(IntPtrTy, ContextV, FieldIdx);
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// Generate the appropriate load from the GEP into the __context struct.
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// This includes all of the user arguments as well as the implicit kernel
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// argument pointer.
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if (C.capturesVariableByCopy() && FD->getType()->isAnyPointerType()) {
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const VarDecl *CurVD = C.getCapturedVar();
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Slot->setName(CurVD->getName());
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Address SlotAddr(Slot, PtrTy, SlotAlign);
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LocalAddrs.insert({FD, {CurVD, SlotAddr}});
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} else if (FD->hasCapturedVLAType()) {
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// VLA size is stored as intptr_t directly in the slot.
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Address SlotAddr(Slot, CGF.ConvertTypeForMem(FD->getType()), SlotAlign);
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LValue ArgLVal =
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CGF.MakeAddrLValue(SlotAddr, FD->getType(), AlignmentSource::Decl);
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llvm::Value *ExprArg = CGF.EmitLoadOfScalar(ArgLVal, C.getLocation());
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const VariableArrayType *VAT = FD->getCapturedVLAType();
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VLASizes.try_emplace(FD, VAT->getSizeExpr(), ExprArg);
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} else if (C.capturesVariable()) {
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const VarDecl *Var = C.getCapturedVar();
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QualType VarTy = Var->getType();
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if (VarTy->isVariablyModifiedType() && VarTy->isPointerType()) {
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Slot->setName(Var->getName() + ".addr");
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Address SlotAddr(Slot, PtrTy, SlotAlign);
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LocalAddrs.insert({FD, {Var, SlotAddr}});
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} else {
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llvm::Value *VarAddr = CGF.Builder.CreateAlignedLoad(
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PtrTy, Slot, PtrAlign, Var->getName());
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LocalAddrs.insert({FD,
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{Var, Address(VarAddr, CGF.ConvertTypeForMem(VarTy),
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Ctx.getDeclAlign(Var))}});
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}
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} else if (C.capturesVariableByCopy()) {
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assert(!FD->getType()->isAnyPointerType() &&
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"Not expecting a captured pointer.");
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const VarDecl *Var = C.getCapturedVar();
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QualType FieldTy = FD->getType();
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// Scalar values are promoted and stored directly in the slot.
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Address SlotAddr(Slot, CGF.ConvertTypeForMem(FieldTy), SlotAlign);
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Address CopyAddr =
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CGF.CreateMemTemp(FieldTy, Ctx.getDeclAlign(FD), Var->getName());
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LValue SrcLVal =
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CGF.MakeAddrLValue(SlotAddr, FieldTy, AlignmentSource::Decl);
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LValue CopyLVal =
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CGF.MakeAddrLValue(CopyAddr, FieldTy, AlignmentSource::Decl);
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RValue ArgRVal = CGF.EmitLoadOfLValue(SrcLVal, C.getLocation());
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CGF.EmitStoreThroughLValue(ArgRVal, CopyLVal);
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LocalAddrs.insert({FD, {Var, CopyAddr}});
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} else {
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assert(C.capturesThis() && "Default case expected to be CXX 'this'");
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CXXThisValue =
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CGF.Builder.CreateAlignedLoad(PtrTy, Slot, PtrAlign, "this");
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Address SlotAddr(Slot, PtrTy, SlotAlign);
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LocalAddrs.insert({FD, {nullptr, SlotAddr}});
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}
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}
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return F;
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}
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llvm::Function *CodeGenFunction::GenerateOpenMPCapturedStmtFunction(
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const CapturedStmt &S, const OMPExecutableDirective &D) {
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SourceLocation Loc = D.getBeginLoc();
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@ -789,6 +895,124 @@ llvm::Function *CodeGenFunction::GenerateOpenMPCapturedStmtFunction(
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return WrapperF;
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}
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llvm::Function *CodeGenFunction::GenerateOpenMPCapturedStmtFunctionAggregate(
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const CapturedStmt &S, const OMPExecutableDirective &D) {
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SourceLocation Loc = D.getBeginLoc();
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assert(
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CapturedStmtInfo &&
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"CapturedStmtInfo should be set when generating the captured function");
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const CapturedDecl *CD = S.getCapturedDecl();
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const RecordDecl *RD = S.getCapturedRecordDecl();
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StringRef FunctionName = CapturedStmtInfo->getHelperName();
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bool NeedWrapperFunction =
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getDebugInfo() && CGM.getCodeGenOpts().hasReducedDebugInfo();
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CodeGenFunction WrapperCGF(CGM, /*suppressNewContext=*/true);
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llvm::Function *WrapperF = nullptr;
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llvm::Value *WrapperContextV = nullptr;
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if (NeedWrapperFunction) {
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WrapperCGF.CapturedStmtInfo = CapturedStmtInfo;
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FunctionArgList WrapperArgs;
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llvm::MapVector<const Decl *, std::pair<const VarDecl *, Address>>
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WrapperLocalAddrs;
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llvm::DenseMap<const Decl *, std::pair<const Expr *, llvm::Value *>>
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WrapperVLASizes;
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WrapperF = emitOutlinedFunctionPrologueAggregate(
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WrapperCGF, WrapperArgs, WrapperLocalAddrs, WrapperVLASizes,
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WrapperCGF.CXXThisValue, WrapperContextV, S, Loc, FunctionName);
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}
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FunctionArgList Args;
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llvm::MapVector<const Decl *, std::pair<const VarDecl *, Address>> LocalAddrs;
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llvm::DenseMap<const Decl *, std::pair<const Expr *, llvm::Value *>> VLASizes;
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llvm::Function *F;
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if (NeedWrapperFunction) {
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SmallString<256> Buffer;
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llvm::raw_svector_ostream Out(Buffer);
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Out << FunctionName << "_debug__";
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FunctionOptions FO(&S, /*UIntPtrCastRequired=*/false,
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/*RegisterCastedArgsOnly=*/false, Out.str(), Loc,
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/*IsDeviceKernel=*/false);
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F = emitOutlinedFunctionPrologue(*this, Args, LocalAddrs, VLASizes,
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CXXThisValue, FO);
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} else {
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llvm::Value *ContextV = nullptr;
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F = emitOutlinedFunctionPrologueAggregate(*this, Args, LocalAddrs, VLASizes,
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CXXThisValue, ContextV, S, Loc,
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FunctionName);
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const RecordDecl *RD = S.getCapturedRecordDecl();
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unsigned FieldIdx = RD->getNumFields();
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for (unsigned I = 0; I < CD->getNumParams(); ++I) {
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const ImplicitParamDecl *Param = CD->getParam(I);
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if (Param == CD->getContextParam())
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continue;
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llvm::Value *ParamAddr = Builder.CreateConstInBoundsGEP1_32(
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IntPtrTy, ContextV, FieldIdx, Twine(Param->getName()) + ".addr");
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llvm::Value *ParamVal = Builder.CreateAlignedLoad(
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Builder.getPtrTy(), ParamAddr,
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CGM.getDataLayout().getPointerABIAlignment(0), Param->getName());
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Address ParamLocalAddr =
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CreateMemTemp(Param->getType(), Param->getName());
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Builder.CreateStore(ParamVal, ParamLocalAddr);
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LocalAddrs.insert({Param, {Param, ParamLocalAddr}});
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++FieldIdx;
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}
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}
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CodeGenFunction::OMPPrivateScope LocalScope(*this);
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for (const auto &LocalAddrPair : LocalAddrs) {
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if (LocalAddrPair.second.first)
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LocalScope.addPrivate(LocalAddrPair.second.first,
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LocalAddrPair.second.second);
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}
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(void)LocalScope.Privatize();
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for (const auto &VLASizePair : VLASizes)
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VLASizeMap[VLASizePair.second.first] = VLASizePair.second.second;
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PGO->assignRegionCounters(GlobalDecl(CD), F);
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CapturedStmtInfo->EmitBody(*this, CD->getBody());
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(void)LocalScope.ForceCleanup();
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FinishFunction(CD->getBodyRBrace());
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if (!NeedWrapperFunction)
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return F;
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// Reverse the order.
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WrapperF->removeFromParent();
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F->getParent()->getFunctionList().insertAfter(F->getIterator(), WrapperF);
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llvm::Align PtrAlign = CGM.getDataLayout().getPointerABIAlignment(0);
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llvm::SmallVector<llvm::Value *, 16> CallArgs;
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assert(CD->getContextParamPosition() == 0 &&
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"Expected context param at position 0 for target regions");
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assert(RD->getNumFields() + 1 == F->getNumOperands() &&
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"Argument count mismatch");
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for (auto [FD, InnerParam, SlotIdx] : llvm::zip(
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RD->fields(), F->args(), llvm::seq<unsigned>(RD->getNumFields()))) {
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llvm::Value *Slot = WrapperCGF.Builder.CreateConstInBoundsGEP1_32(
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WrapperCGF.IntPtrTy, WrapperContextV, SlotIdx);
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llvm::Value *Val = WrapperCGF.Builder.CreateAlignedLoad(
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InnerParam.getType(), Slot, PtrAlign, InnerParam.getName());
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CallArgs.push_back(Val);
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}
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// Handle the load from the implicit dyn_ptr at the end of the __context.
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unsigned SlotIdx = RD->getNumFields();
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auto InnerParam = F->arg_begin() + SlotIdx;
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llvm::Value *Slot = WrapperCGF.Builder.CreateConstInBoundsGEP1_32(
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WrapperCGF.IntPtrTy, WrapperContextV, SlotIdx);
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llvm::Value *Val = WrapperCGF.Builder.CreateAlignedLoad(
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InnerParam->getType(), Slot, PtrAlign, InnerParam->getName());
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CallArgs.push_back(Val);
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CGM.getOpenMPRuntime().emitOutlinedFunctionCall(WrapperCGF, Loc, F, CallArgs);
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WrapperCGF.FinishFunction();
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return WrapperF;
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}
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//===----------------------------------------------------------------------===//
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// OpenMP Directive Emission
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//===----------------------------------------------------------------------===//
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@ -3756,6 +3756,9 @@ public:
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llvm::Function *
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GenerateOpenMPCapturedStmtFunction(const CapturedStmt &S,
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const OMPExecutableDirective &D);
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llvm::Function *
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GenerateOpenMPCapturedStmtFunctionAggregate(const CapturedStmt &S,
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const OMPExecutableDirective &D);
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void GenerateOpenMPCapturedVars(const CapturedStmt &S,
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SmallVectorImpl<llvm::Value *> &CapturedVars);
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void emitOMPSimpleStore(LValue LVal, RValue RVal, QualType RValTy,
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@ -150,7 +150,7 @@ int bar() { return 1 + foo() + bar() + baz1() + baz2(); }
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int maini1() {
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int a;
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static long aa = 32 + bbb + ccc + fff + ggg;
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// CHECK-DAG: define weak_odr protected void @__omp_offloading_{{.*}}maini1{{.*}}_l[[@LINE+1]](ptr noundef nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) %{{.*}}, i64 {{.*}}, i64 {{.*}}, ptr {{.*}})
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// CHECK-DAG: define weak_odr protected void @__omp_offloading_{{.*}}maini1{{.*}}_l[[@LINE+1]](ptr noalias noundef %__context)
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#pragma omp target map(tofrom \
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: a, b)
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{
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@ -163,7 +163,7 @@ int maini1() {
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int baz3() { return 2 + baz2(); }
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int baz2() {
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// CHECK-DAG: define weak_odr protected void @__omp_offloading_{{.*}}baz2{{.*}}_l[[@LINE+1]](i64 {{.*}}, ptr {{.*}})
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// CHECK-DAG: define weak_odr protected void @__omp_offloading_{{.*}}baz2{{.*}}_l[[@LINE+1]](ptr noalias noundef %__context)
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#pragma omp target parallel
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++c;
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return 2 + baz3();
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@ -175,7 +175,7 @@ static __typeof(create) __t_create __attribute__((__weakref__("__create")));
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int baz5() {
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bool a;
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// CHECK-DAG: define weak_odr protected void @__omp_offloading_{{.*}}baz5{{.*}}_l[[@LINE+1]](i64 {{.*}}, ptr {{.*}})
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// CHECK-DAG: define weak_odr protected void @__omp_offloading_{{.*}}baz5{{.*}}_l[[@LINE+1]](ptr noalias noundef %__context)
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#pragma omp target
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a = __extension__(void *) & __t_create != 0;
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return a;
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@ -241,8 +241,8 @@ int main() {
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return 0;
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}
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// CHECK-DAG: define {{.*}}void @__omp_offloading_{{.*}}virtual_foo{{.*}}_l[[@LINE-25]](ptr {{.*}})
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// CHECK-DAG: define {{.*}}void @__omp_offloading_{{.*}}emitted{{.*}}_l[[@LINE-11]](ptr {{.*}})
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// CHECK-DAG: define {{.*}}void @__omp_offloading_{{.*}}virtual_foo{{.*}}_l[[@LINE-25]](ptr noalias noundef %__context)
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// CHECK-DAG: define {{.*}}void @__omp_offloading_{{.*}}emitted{{.*}}_l[[@LINE-11]](ptr noalias noundef %__context)
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template <typename T>
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struct TTT {
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@ -252,7 +252,7 @@ struct TTT {
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}
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};
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// CHECK-DAG: define {{.*}}void @__omp_offloading_{{.*}}emitted{{.*}}_l[[@LINE-5]](ptr {{.*}})
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// CHECK-DAG: define {{.*}}void @__omp_offloading_{{.*}}emitted{{.*}}_l[[@LINE-5]](ptr noalias noundef %__context)
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// CHECK-DAG: declare extern_weak noundef signext i32 @__create()
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@ -52,7 +52,7 @@ int maini1() {
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return 0;
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}
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// DEVICE: define weak_odr protected void @__omp_offloading_{{.*}}_{{.*}}maini1{{.*}}_l44(ptr noundef nonnull align {{[0-9]+}} dereferenceable{{[^,]*}}
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// DEVICE: define weak_odr protected void @__omp_offloading_{{.*}}_{{.*}}maini1{{.*}}_l44(ptr noalias noundef %__context)
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// DEVICE: [[C_REF:%.+]] = load ptr, ptr @c_decl_tgt_ref_ptr,
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// DEVICE: [[C:%.+]] = load i32, ptr [[C_REF]],
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// DEVICE: store i32 [[C]], ptr %
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@ -2027,19 +2027,20 @@ int fint(void) { return ftemplate<int>(); }
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//
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//
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// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l56
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// CHECK17-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0:[0-9]+]] {
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// CHECK17-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0:[0-9]+]] {
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// CHECK17-NEXT: entry:
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// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8
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// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8
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// CHECK17-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8
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// CHECK17-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8
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// CHECK17-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
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// CHECK17-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8
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// CHECK17-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
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// CHECK17-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8
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// CHECK17-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8
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// CHECK17-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
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// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2:[0-9]+]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l56.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]])
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// CHECK17-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8
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// CHECK17-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
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// CHECK17-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
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// CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
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// CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
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// CHECK17-NEXT: [[B:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
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// CHECK17-NEXT: [[C:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 2
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// CHECK17-NEXT: [[D:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 3
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// CHECK17-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 4
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// CHECK17-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
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// CHECK17-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
|
||||
// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2:[0-9]+]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l56.omp_outlined, ptr [[A]], ptr [[B]], ptr [[C]], ptr [[D]])
|
||||
// CHECK17-NEXT: ret void
|
||||
//
|
||||
//
|
||||
@ -2138,19 +2139,20 @@ int fint(void) { return ftemplate<int>(); }
|
||||
//
|
||||
//
|
||||
// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l68
|
||||
// CHECK17-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK17-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK17-NEXT: entry:
|
||||
// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK17-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK17-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK17-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK17-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8
|
||||
// CHECK17-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
|
||||
// CHECK17-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8
|
||||
// CHECK17-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8
|
||||
// CHECK17-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l68.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]])
|
||||
// CHECK17-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK17-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
|
||||
// CHECK17-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
|
||||
// CHECK17-NEXT: [[B:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
|
||||
// CHECK17-NEXT: [[C:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 2
|
||||
// CHECK17-NEXT: [[D:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 3
|
||||
// CHECK17-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 4
|
||||
// CHECK17-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK17-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
|
||||
// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l68.omp_outlined, ptr [[A]], ptr [[B]], ptr [[C]], ptr [[D]])
|
||||
// CHECK17-NEXT: ret void
|
||||
//
|
||||
//
|
||||
@ -2249,19 +2251,20 @@ int fint(void) { return ftemplate<int>(); }
|
||||
//
|
||||
//
|
||||
// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l80
|
||||
// CHECK17-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK17-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK17-NEXT: entry:
|
||||
// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK17-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK17-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK17-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK17-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8
|
||||
// CHECK17-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
|
||||
// CHECK17-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8
|
||||
// CHECK17-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8
|
||||
// CHECK17-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l80.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]])
|
||||
// CHECK17-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK17-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
|
||||
// CHECK17-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
|
||||
// CHECK17-NEXT: [[B:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
|
||||
// CHECK17-NEXT: [[C:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 2
|
||||
// CHECK17-NEXT: [[D:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 3
|
||||
// CHECK17-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 4
|
||||
// CHECK17-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK17-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
|
||||
// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l80.omp_outlined, ptr [[A]], ptr [[B]], ptr [[C]], ptr [[D]])
|
||||
// CHECK17-NEXT: ret void
|
||||
//
|
||||
//
|
||||
@ -2377,13 +2380,20 @@ int fint(void) { return ftemplate<int>(); }
|
||||
//
|
||||
//
|
||||
// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l92
|
||||
// CHECK17-SAME: (i64 noundef [[A:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK17-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK17-NEXT: entry:
|
||||
// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK17-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK17-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8
|
||||
// CHECK17-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l92.omp_outlined, ptr [[A_ADDR]])
|
||||
// CHECK17-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK17-NEXT: [[A:%.*]] = alloca i8, align 1
|
||||
// CHECK17-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
|
||||
// CHECK17-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK17-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
|
||||
// CHECK17-NEXT: [[TMP2:%.*]] = load i8, ptr [[TMP1]], align 8
|
||||
// CHECK17-NEXT: store i8 [[TMP2]], ptr [[A]], align 1
|
||||
// CHECK17-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
|
||||
// CHECK17-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK17-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
|
||||
// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l92.omp_outlined, ptr [[A]])
|
||||
// CHECK17-NEXT: ret void
|
||||
//
|
||||
//
|
||||
@ -2481,13 +2491,20 @@ int fint(void) { return ftemplate<int>(); }
|
||||
//
|
||||
//
|
||||
// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l108
|
||||
// CHECK17-SAME: (i64 noundef [[AA:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK17-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK17-NEXT: entry:
|
||||
// CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK17-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK17-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8
|
||||
// CHECK17-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l108.omp_outlined, ptr [[AA_ADDR]])
|
||||
// CHECK17-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK17-NEXT: [[AA:%.*]] = alloca i16, align 2
|
||||
// CHECK17-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
|
||||
// CHECK17-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK17-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
|
||||
// CHECK17-NEXT: [[TMP2:%.*]] = load i16, ptr [[TMP1]], align 8
|
||||
// CHECK17-NEXT: store i16 [[TMP2]], ptr [[AA]], align 2
|
||||
// CHECK17-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
|
||||
// CHECK17-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK17-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
|
||||
// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l108.omp_outlined, ptr [[AA]])
|
||||
// CHECK17-NEXT: ret void
|
||||
//
|
||||
//
|
||||
@ -2574,19 +2591,20 @@ int fint(void) { return ftemplate<int>(); }
|
||||
//
|
||||
//
|
||||
// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l56
|
||||
// CHECK19-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK19-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK19-NEXT: entry:
|
||||
// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK19-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK19-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK19-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK19-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4
|
||||
// CHECK19-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4
|
||||
// CHECK19-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4
|
||||
// CHECK19-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4
|
||||
// CHECK19-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2:[0-9]+]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l56.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]])
|
||||
// CHECK19-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK19-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 4
|
||||
// CHECK19-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK19-NEXT: [[A:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
|
||||
// CHECK19-NEXT: [[B:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
|
||||
// CHECK19-NEXT: [[C:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 2
|
||||
// CHECK19-NEXT: [[D:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 3
|
||||
// CHECK19-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 4
|
||||
// CHECK19-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK19-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
|
||||
// CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2:[0-9]+]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l56.omp_outlined, ptr [[A]], ptr [[B]], ptr [[C]], ptr [[D]])
|
||||
// CHECK19-NEXT: ret void
|
||||
//
|
||||
//
|
||||
@ -2681,19 +2699,20 @@ int fint(void) { return ftemplate<int>(); }
|
||||
//
|
||||
//
|
||||
// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l68
|
||||
// CHECK19-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK19-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK19-NEXT: entry:
|
||||
// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK19-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK19-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK19-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK19-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4
|
||||
// CHECK19-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4
|
||||
// CHECK19-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4
|
||||
// CHECK19-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4
|
||||
// CHECK19-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l68.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]])
|
||||
// CHECK19-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK19-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 4
|
||||
// CHECK19-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK19-NEXT: [[A:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
|
||||
// CHECK19-NEXT: [[B:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
|
||||
// CHECK19-NEXT: [[C:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 2
|
||||
// CHECK19-NEXT: [[D:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 3
|
||||
// CHECK19-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 4
|
||||
// CHECK19-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK19-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
|
||||
// CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l68.omp_outlined, ptr [[A]], ptr [[B]], ptr [[C]], ptr [[D]])
|
||||
// CHECK19-NEXT: ret void
|
||||
//
|
||||
//
|
||||
@ -2788,19 +2807,20 @@ int fint(void) { return ftemplate<int>(); }
|
||||
//
|
||||
//
|
||||
// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l80
|
||||
// CHECK19-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK19-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK19-NEXT: entry:
|
||||
// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK19-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK19-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK19-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK19-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4
|
||||
// CHECK19-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4
|
||||
// CHECK19-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4
|
||||
// CHECK19-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4
|
||||
// CHECK19-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l80.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]])
|
||||
// CHECK19-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK19-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 4
|
||||
// CHECK19-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK19-NEXT: [[A:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
|
||||
// CHECK19-NEXT: [[B:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
|
||||
// CHECK19-NEXT: [[C:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 2
|
||||
// CHECK19-NEXT: [[D:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 3
|
||||
// CHECK19-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 4
|
||||
// CHECK19-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK19-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
|
||||
// CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l80.omp_outlined, ptr [[A]], ptr [[B]], ptr [[C]], ptr [[D]])
|
||||
// CHECK19-NEXT: ret void
|
||||
//
|
||||
//
|
||||
@ -2912,13 +2932,20 @@ int fint(void) { return ftemplate<int>(); }
|
||||
//
|
||||
//
|
||||
// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l92
|
||||
// CHECK19-SAME: (i32 noundef [[A:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK19-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK19-NEXT: entry:
|
||||
// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK19-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK19-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
|
||||
// CHECK19-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l92.omp_outlined, ptr [[A_ADDR]])
|
||||
// CHECK19-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK19-NEXT: [[A:%.*]] = alloca i8, align 1
|
||||
// CHECK19-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 4
|
||||
// CHECK19-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK19-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
|
||||
// CHECK19-NEXT: [[TMP2:%.*]] = load i8, ptr [[TMP1]], align 4
|
||||
// CHECK19-NEXT: store i8 [[TMP2]], ptr [[A]], align 1
|
||||
// CHECK19-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
|
||||
// CHECK19-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK19-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
|
||||
// CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l92.omp_outlined, ptr [[A]])
|
||||
// CHECK19-NEXT: ret void
|
||||
//
|
||||
//
|
||||
@ -3016,13 +3043,20 @@ int fint(void) { return ftemplate<int>(); }
|
||||
//
|
||||
//
|
||||
// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l108
|
||||
// CHECK19-SAME: (i32 noundef [[AA:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK19-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK19-NEXT: entry:
|
||||
// CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK19-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK19-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4
|
||||
// CHECK19-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l108.omp_outlined, ptr [[AA_ADDR]])
|
||||
// CHECK19-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK19-NEXT: [[AA:%.*]] = alloca i16, align 2
|
||||
// CHECK19-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 4
|
||||
// CHECK19-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK19-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
|
||||
// CHECK19-NEXT: [[TMP2:%.*]] = load i16, ptr [[TMP1]], align 4
|
||||
// CHECK19-NEXT: store i16 [[TMP2]], ptr [[AA]], align 2
|
||||
// CHECK19-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
|
||||
// CHECK19-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK19-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
|
||||
// CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l108.omp_outlined, ptr [[AA]])
|
||||
// CHECK19-NEXT: ret void
|
||||
//
|
||||
//
|
||||
|
||||
@ -5621,19 +5621,20 @@ int fint(void) { return ftemplate<int>(); }
|
||||
//
|
||||
//
|
||||
// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70
|
||||
// CHECK17-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK17-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK17-NEXT: entry:
|
||||
// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK17-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK17-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK17-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK17-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8
|
||||
// CHECK17-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
|
||||
// CHECK17-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8
|
||||
// CHECK17-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8
|
||||
// CHECK17-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2:[0-9]+]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]])
|
||||
// CHECK17-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK17-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
|
||||
// CHECK17-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
|
||||
// CHECK17-NEXT: [[B:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
|
||||
// CHECK17-NEXT: [[C:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 2
|
||||
// CHECK17-NEXT: [[D:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 3
|
||||
// CHECK17-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 4
|
||||
// CHECK17-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK17-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
|
||||
// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2:[0-9]+]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70.omp_outlined, ptr [[A]], ptr [[B]], ptr [[C]], ptr [[D]])
|
||||
// CHECK17-NEXT: ret void
|
||||
//
|
||||
//
|
||||
@ -5741,19 +5742,20 @@ int fint(void) { return ftemplate<int>(); }
|
||||
//
|
||||
//
|
||||
// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86
|
||||
// CHECK17-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK17-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK17-NEXT: entry:
|
||||
// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK17-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK17-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK17-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK17-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8
|
||||
// CHECK17-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
|
||||
// CHECK17-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8
|
||||
// CHECK17-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8
|
||||
// CHECK17-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]])
|
||||
// CHECK17-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK17-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
|
||||
// CHECK17-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
|
||||
// CHECK17-NEXT: [[B:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
|
||||
// CHECK17-NEXT: [[C:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 2
|
||||
// CHECK17-NEXT: [[D:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 3
|
||||
// CHECK17-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 4
|
||||
// CHECK17-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK17-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
|
||||
// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86.omp_outlined, ptr [[A]], ptr [[B]], ptr [[C]], ptr [[D]])
|
||||
// CHECK17-NEXT: ret void
|
||||
//
|
||||
//
|
||||
@ -5859,19 +5861,20 @@ int fint(void) { return ftemplate<int>(); }
|
||||
//
|
||||
//
|
||||
// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103
|
||||
// CHECK17-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK17-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK17-NEXT: entry:
|
||||
// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK17-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK17-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK17-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK17-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8
|
||||
// CHECK17-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
|
||||
// CHECK17-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8
|
||||
// CHECK17-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8
|
||||
// CHECK17-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]])
|
||||
// CHECK17-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK17-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
|
||||
// CHECK17-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
|
||||
// CHECK17-NEXT: [[B:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
|
||||
// CHECK17-NEXT: [[C:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 2
|
||||
// CHECK17-NEXT: [[D:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 3
|
||||
// CHECK17-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 4
|
||||
// CHECK17-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK17-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
|
||||
// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103.omp_outlined, ptr [[A]], ptr [[B]], ptr [[C]], ptr [[D]])
|
||||
// CHECK17-NEXT: ret void
|
||||
//
|
||||
//
|
||||
@ -5994,15 +5997,24 @@ int fint(void) { return ftemplate<int>(); }
|
||||
//
|
||||
//
|
||||
// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115
|
||||
// CHECK17-SAME: (i64 noundef [[I:%.*]], i64 noundef [[A:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK17-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK17-NEXT: entry:
|
||||
// CHECK17-NEXT: [[I_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK17-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK17-NEXT: store i64 [[I]], ptr [[I_ADDR]], align 8
|
||||
// CHECK17-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8
|
||||
// CHECK17-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115.omp_outlined, ptr [[I_ADDR]], ptr [[A_ADDR]])
|
||||
// CHECK17-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK17-NEXT: [[I:%.*]] = alloca i8, align 1
|
||||
// CHECK17-NEXT: [[A:%.*]] = alloca i8, align 1
|
||||
// CHECK17-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
|
||||
// CHECK17-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK17-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
|
||||
// CHECK17-NEXT: [[TMP2:%.*]] = load i8, ptr [[TMP1]], align 8
|
||||
// CHECK17-NEXT: store i8 [[TMP2]], ptr [[I]], align 1
|
||||
// CHECK17-NEXT: [[TMP3:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
|
||||
// CHECK17-NEXT: [[TMP4:%.*]] = load i8, ptr [[TMP3]], align 8
|
||||
// CHECK17-NEXT: store i8 [[TMP4]], ptr [[A]], align 1
|
||||
// CHECK17-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 2
|
||||
// CHECK17-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK17-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
|
||||
// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115.omp_outlined, ptr [[I]], ptr [[A]])
|
||||
// CHECK17-NEXT: ret void
|
||||
//
|
||||
//
|
||||
@ -6121,13 +6133,20 @@ int fint(void) { return ftemplate<int>(); }
|
||||
//
|
||||
//
|
||||
// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135
|
||||
// CHECK17-SAME: (i64 noundef [[AA:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK17-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK17-NEXT: entry:
|
||||
// CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK17-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK17-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8
|
||||
// CHECK17-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135.omp_outlined, ptr [[AA_ADDR]])
|
||||
// CHECK17-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK17-NEXT: [[AA:%.*]] = alloca i16, align 2
|
||||
// CHECK17-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
|
||||
// CHECK17-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK17-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
|
||||
// CHECK17-NEXT: [[TMP2:%.*]] = load i16, ptr [[TMP1]], align 8
|
||||
// CHECK17-NEXT: store i16 [[TMP2]], ptr [[AA]], align 2
|
||||
// CHECK17-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
|
||||
// CHECK17-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK17-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
|
||||
// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135.omp_outlined, ptr [[AA]])
|
||||
// CHECK17-NEXT: ret void
|
||||
//
|
||||
//
|
||||
@ -6221,19 +6240,20 @@ int fint(void) { return ftemplate<int>(); }
|
||||
//
|
||||
//
|
||||
// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70
|
||||
// CHECK19-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK19-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK19-NEXT: entry:
|
||||
// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK19-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK19-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK19-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK19-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4
|
||||
// CHECK19-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4
|
||||
// CHECK19-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4
|
||||
// CHECK19-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4
|
||||
// CHECK19-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2:[0-9]+]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]])
|
||||
// CHECK19-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK19-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 4
|
||||
// CHECK19-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK19-NEXT: [[A:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
|
||||
// CHECK19-NEXT: [[B:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
|
||||
// CHECK19-NEXT: [[C:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 2
|
||||
// CHECK19-NEXT: [[D:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 3
|
||||
// CHECK19-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 4
|
||||
// CHECK19-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK19-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
|
||||
// CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2:[0-9]+]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70.omp_outlined, ptr [[A]], ptr [[B]], ptr [[C]], ptr [[D]])
|
||||
// CHECK19-NEXT: ret void
|
||||
//
|
||||
//
|
||||
@ -6337,19 +6357,20 @@ int fint(void) { return ftemplate<int>(); }
|
||||
//
|
||||
//
|
||||
// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86
|
||||
// CHECK19-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK19-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK19-NEXT: entry:
|
||||
// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK19-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK19-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK19-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK19-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4
|
||||
// CHECK19-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4
|
||||
// CHECK19-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4
|
||||
// CHECK19-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4
|
||||
// CHECK19-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]])
|
||||
// CHECK19-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK19-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 4
|
||||
// CHECK19-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK19-NEXT: [[A:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
|
||||
// CHECK19-NEXT: [[B:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
|
||||
// CHECK19-NEXT: [[C:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 2
|
||||
// CHECK19-NEXT: [[D:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 3
|
||||
// CHECK19-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 4
|
||||
// CHECK19-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK19-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
|
||||
// CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86.omp_outlined, ptr [[A]], ptr [[B]], ptr [[C]], ptr [[D]])
|
||||
// CHECK19-NEXT: ret void
|
||||
//
|
||||
//
|
||||
@ -6451,19 +6472,20 @@ int fint(void) { return ftemplate<int>(); }
|
||||
//
|
||||
//
|
||||
// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103
|
||||
// CHECK19-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK19-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK19-NEXT: entry:
|
||||
// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK19-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK19-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK19-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK19-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4
|
||||
// CHECK19-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4
|
||||
// CHECK19-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4
|
||||
// CHECK19-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4
|
||||
// CHECK19-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]])
|
||||
// CHECK19-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK19-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 4
|
||||
// CHECK19-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK19-NEXT: [[A:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
|
||||
// CHECK19-NEXT: [[B:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
|
||||
// CHECK19-NEXT: [[C:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 2
|
||||
// CHECK19-NEXT: [[D:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 3
|
||||
// CHECK19-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 4
|
||||
// CHECK19-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK19-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
|
||||
// CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103.omp_outlined, ptr [[A]], ptr [[B]], ptr [[C]], ptr [[D]])
|
||||
// CHECK19-NEXT: ret void
|
||||
//
|
||||
//
|
||||
@ -6582,15 +6604,24 @@ int fint(void) { return ftemplate<int>(); }
|
||||
//
|
||||
//
|
||||
// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115
|
||||
// CHECK19-SAME: (i32 noundef [[I:%.*]], i32 noundef [[A:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK19-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK19-NEXT: entry:
|
||||
// CHECK19-NEXT: [[I_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK19-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK19-NEXT: store i32 [[I]], ptr [[I_ADDR]], align 4
|
||||
// CHECK19-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
|
||||
// CHECK19-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115.omp_outlined, ptr [[I_ADDR]], ptr [[A_ADDR]])
|
||||
// CHECK19-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK19-NEXT: [[I:%.*]] = alloca i8, align 1
|
||||
// CHECK19-NEXT: [[A:%.*]] = alloca i8, align 1
|
||||
// CHECK19-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 4
|
||||
// CHECK19-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK19-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
|
||||
// CHECK19-NEXT: [[TMP2:%.*]] = load i8, ptr [[TMP1]], align 4
|
||||
// CHECK19-NEXT: store i8 [[TMP2]], ptr [[I]], align 1
|
||||
// CHECK19-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
|
||||
// CHECK19-NEXT: [[TMP4:%.*]] = load i8, ptr [[TMP3]], align 4
|
||||
// CHECK19-NEXT: store i8 [[TMP4]], ptr [[A]], align 1
|
||||
// CHECK19-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 2
|
||||
// CHECK19-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK19-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
|
||||
// CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115.omp_outlined, ptr [[I]], ptr [[A]])
|
||||
// CHECK19-NEXT: ret void
|
||||
//
|
||||
//
|
||||
@ -6709,13 +6740,20 @@ int fint(void) { return ftemplate<int>(); }
|
||||
//
|
||||
//
|
||||
// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135
|
||||
// CHECK19-SAME: (i32 noundef [[AA:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK19-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK19-NEXT: entry:
|
||||
// CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK19-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK19-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4
|
||||
// CHECK19-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135.omp_outlined, ptr [[AA_ADDR]])
|
||||
// CHECK19-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK19-NEXT: [[AA:%.*]] = alloca i16, align 2
|
||||
// CHECK19-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 4
|
||||
// CHECK19-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK19-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
|
||||
// CHECK19-NEXT: [[TMP2:%.*]] = load i16, ptr [[TMP1]], align 4
|
||||
// CHECK19-NEXT: store i16 [[TMP2]], ptr [[AA]], align 2
|
||||
// CHECK19-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
|
||||
// CHECK19-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK19-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
|
||||
// CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135.omp_outlined, ptr [[AA]])
|
||||
// CHECK19-NEXT: ret void
|
||||
//
|
||||
//
|
||||
@ -6809,19 +6847,20 @@ int fint(void) { return ftemplate<int>(); }
|
||||
//
|
||||
//
|
||||
// CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70
|
||||
// CHECK21-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK21-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK21-NEXT: entry:
|
||||
// CHECK21-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK21-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK21-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK21-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK21-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK21-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8
|
||||
// CHECK21-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
|
||||
// CHECK21-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8
|
||||
// CHECK21-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8
|
||||
// CHECK21-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK21-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2:[0-9]+]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]])
|
||||
// CHECK21-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK21-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
|
||||
// CHECK21-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK21-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK21-NEXT: [[A:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
|
||||
// CHECK21-NEXT: [[B:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
|
||||
// CHECK21-NEXT: [[C:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 2
|
||||
// CHECK21-NEXT: [[D:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 3
|
||||
// CHECK21-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 4
|
||||
// CHECK21-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK21-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
|
||||
// CHECK21-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2:[0-9]+]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70.omp_outlined, ptr [[A]], ptr [[B]], ptr [[C]], ptr [[D]])
|
||||
// CHECK21-NEXT: ret void
|
||||
//
|
||||
//
|
||||
@ -6929,19 +6968,20 @@ int fint(void) { return ftemplate<int>(); }
|
||||
//
|
||||
//
|
||||
// CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86
|
||||
// CHECK21-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK21-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK21-NEXT: entry:
|
||||
// CHECK21-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK21-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK21-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK21-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK21-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK21-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8
|
||||
// CHECK21-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
|
||||
// CHECK21-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8
|
||||
// CHECK21-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8
|
||||
// CHECK21-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK21-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]])
|
||||
// CHECK21-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK21-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
|
||||
// CHECK21-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK21-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK21-NEXT: [[A:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
|
||||
// CHECK21-NEXT: [[B:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
|
||||
// CHECK21-NEXT: [[C:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 2
|
||||
// CHECK21-NEXT: [[D:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 3
|
||||
// CHECK21-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 4
|
||||
// CHECK21-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK21-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
|
||||
// CHECK21-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86.omp_outlined, ptr [[A]], ptr [[B]], ptr [[C]], ptr [[D]])
|
||||
// CHECK21-NEXT: ret void
|
||||
//
|
||||
//
|
||||
@ -7047,19 +7087,20 @@ int fint(void) { return ftemplate<int>(); }
|
||||
//
|
||||
//
|
||||
// CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103
|
||||
// CHECK21-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK21-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK21-NEXT: entry:
|
||||
// CHECK21-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK21-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK21-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK21-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK21-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK21-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8
|
||||
// CHECK21-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
|
||||
// CHECK21-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8
|
||||
// CHECK21-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8
|
||||
// CHECK21-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK21-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]])
|
||||
// CHECK21-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK21-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
|
||||
// CHECK21-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK21-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK21-NEXT: [[A:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
|
||||
// CHECK21-NEXT: [[B:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
|
||||
// CHECK21-NEXT: [[C:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 2
|
||||
// CHECK21-NEXT: [[D:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 3
|
||||
// CHECK21-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 4
|
||||
// CHECK21-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK21-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
|
||||
// CHECK21-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103.omp_outlined, ptr [[A]], ptr [[B]], ptr [[C]], ptr [[D]])
|
||||
// CHECK21-NEXT: ret void
|
||||
//
|
||||
//
|
||||
@ -7182,15 +7223,24 @@ int fint(void) { return ftemplate<int>(); }
|
||||
//
|
||||
//
|
||||
// CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115
|
||||
// CHECK21-SAME: (i64 noundef [[I:%.*]], i64 noundef [[A:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK21-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK21-NEXT: entry:
|
||||
// CHECK21-NEXT: [[I_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK21-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK21-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK21-NEXT: store i64 [[I]], ptr [[I_ADDR]], align 8
|
||||
// CHECK21-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8
|
||||
// CHECK21-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK21-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115.omp_outlined, ptr [[I_ADDR]], ptr [[A_ADDR]])
|
||||
// CHECK21-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK21-NEXT: [[I:%.*]] = alloca i8, align 1
|
||||
// CHECK21-NEXT: [[A:%.*]] = alloca i8, align 1
|
||||
// CHECK21-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
|
||||
// CHECK21-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK21-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK21-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
|
||||
// CHECK21-NEXT: [[TMP2:%.*]] = load i8, ptr [[TMP1]], align 8
|
||||
// CHECK21-NEXT: store i8 [[TMP2]], ptr [[I]], align 1
|
||||
// CHECK21-NEXT: [[TMP3:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
|
||||
// CHECK21-NEXT: [[TMP4:%.*]] = load i8, ptr [[TMP3]], align 8
|
||||
// CHECK21-NEXT: store i8 [[TMP4]], ptr [[A]], align 1
|
||||
// CHECK21-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 2
|
||||
// CHECK21-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK21-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
|
||||
// CHECK21-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115.omp_outlined, ptr [[I]], ptr [[A]])
|
||||
// CHECK21-NEXT: ret void
|
||||
//
|
||||
//
|
||||
@ -7340,13 +7390,20 @@ int fint(void) { return ftemplate<int>(); }
|
||||
//
|
||||
//
|
||||
// CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135
|
||||
// CHECK21-SAME: (i64 noundef [[AA:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK21-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK21-NEXT: entry:
|
||||
// CHECK21-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK21-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK21-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8
|
||||
// CHECK21-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK21-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135.omp_outlined, ptr [[AA_ADDR]])
|
||||
// CHECK21-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK21-NEXT: [[AA:%.*]] = alloca i16, align 2
|
||||
// CHECK21-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
|
||||
// CHECK21-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK21-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK21-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
|
||||
// CHECK21-NEXT: [[TMP2:%.*]] = load i16, ptr [[TMP1]], align 8
|
||||
// CHECK21-NEXT: store i16 [[TMP2]], ptr [[AA]], align 2
|
||||
// CHECK21-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
|
||||
// CHECK21-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK21-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
|
||||
// CHECK21-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135.omp_outlined, ptr [[AA]])
|
||||
// CHECK21-NEXT: ret void
|
||||
//
|
||||
//
|
||||
@ -7440,19 +7497,20 @@ int fint(void) { return ftemplate<int>(); }
|
||||
//
|
||||
//
|
||||
// CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70
|
||||
// CHECK23-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK23-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK23-NEXT: entry:
|
||||
// CHECK23-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK23-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK23-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK23-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK23-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK23-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4
|
||||
// CHECK23-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4
|
||||
// CHECK23-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4
|
||||
// CHECK23-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4
|
||||
// CHECK23-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK23-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2:[0-9]+]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]])
|
||||
// CHECK23-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK23-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 4
|
||||
// CHECK23-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK23-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK23-NEXT: [[A:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
|
||||
// CHECK23-NEXT: [[B:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
|
||||
// CHECK23-NEXT: [[C:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 2
|
||||
// CHECK23-NEXT: [[D:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 3
|
||||
// CHECK23-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 4
|
||||
// CHECK23-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK23-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
|
||||
// CHECK23-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2:[0-9]+]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70.omp_outlined, ptr [[A]], ptr [[B]], ptr [[C]], ptr [[D]])
|
||||
// CHECK23-NEXT: ret void
|
||||
//
|
||||
//
|
||||
@ -7556,19 +7614,20 @@ int fint(void) { return ftemplate<int>(); }
|
||||
//
|
||||
//
|
||||
// CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86
|
||||
// CHECK23-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK23-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK23-NEXT: entry:
|
||||
// CHECK23-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK23-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK23-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK23-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK23-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK23-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4
|
||||
// CHECK23-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4
|
||||
// CHECK23-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4
|
||||
// CHECK23-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4
|
||||
// CHECK23-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK23-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]])
|
||||
// CHECK23-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK23-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 4
|
||||
// CHECK23-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK23-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK23-NEXT: [[A:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
|
||||
// CHECK23-NEXT: [[B:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
|
||||
// CHECK23-NEXT: [[C:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 2
|
||||
// CHECK23-NEXT: [[D:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 3
|
||||
// CHECK23-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 4
|
||||
// CHECK23-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK23-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
|
||||
// CHECK23-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86.omp_outlined, ptr [[A]], ptr [[B]], ptr [[C]], ptr [[D]])
|
||||
// CHECK23-NEXT: ret void
|
||||
//
|
||||
//
|
||||
@ -7670,19 +7729,20 @@ int fint(void) { return ftemplate<int>(); }
|
||||
//
|
||||
//
|
||||
// CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103
|
||||
// CHECK23-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK23-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK23-NEXT: entry:
|
||||
// CHECK23-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK23-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK23-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK23-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK23-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK23-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4
|
||||
// CHECK23-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4
|
||||
// CHECK23-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4
|
||||
// CHECK23-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4
|
||||
// CHECK23-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK23-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]])
|
||||
// CHECK23-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK23-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 4
|
||||
// CHECK23-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK23-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK23-NEXT: [[A:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
|
||||
// CHECK23-NEXT: [[B:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
|
||||
// CHECK23-NEXT: [[C:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 2
|
||||
// CHECK23-NEXT: [[D:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 3
|
||||
// CHECK23-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 4
|
||||
// CHECK23-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK23-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
|
||||
// CHECK23-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103.omp_outlined, ptr [[A]], ptr [[B]], ptr [[C]], ptr [[D]])
|
||||
// CHECK23-NEXT: ret void
|
||||
//
|
||||
//
|
||||
@ -7801,15 +7861,24 @@ int fint(void) { return ftemplate<int>(); }
|
||||
//
|
||||
//
|
||||
// CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115
|
||||
// CHECK23-SAME: (i32 noundef [[I:%.*]], i32 noundef [[A:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK23-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK23-NEXT: entry:
|
||||
// CHECK23-NEXT: [[I_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK23-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK23-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK23-NEXT: store i32 [[I]], ptr [[I_ADDR]], align 4
|
||||
// CHECK23-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
|
||||
// CHECK23-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK23-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115.omp_outlined, ptr [[I_ADDR]], ptr [[A_ADDR]])
|
||||
// CHECK23-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK23-NEXT: [[I:%.*]] = alloca i8, align 1
|
||||
// CHECK23-NEXT: [[A:%.*]] = alloca i8, align 1
|
||||
// CHECK23-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 4
|
||||
// CHECK23-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK23-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK23-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
|
||||
// CHECK23-NEXT: [[TMP2:%.*]] = load i8, ptr [[TMP1]], align 4
|
||||
// CHECK23-NEXT: store i8 [[TMP2]], ptr [[I]], align 1
|
||||
// CHECK23-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
|
||||
// CHECK23-NEXT: [[TMP4:%.*]] = load i8, ptr [[TMP3]], align 4
|
||||
// CHECK23-NEXT: store i8 [[TMP4]], ptr [[A]], align 1
|
||||
// CHECK23-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 2
|
||||
// CHECK23-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK23-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
|
||||
// CHECK23-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115.omp_outlined, ptr [[I]], ptr [[A]])
|
||||
// CHECK23-NEXT: ret void
|
||||
//
|
||||
//
|
||||
@ -7959,13 +8028,20 @@ int fint(void) { return ftemplate<int>(); }
|
||||
//
|
||||
//
|
||||
// CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135
|
||||
// CHECK23-SAME: (i32 noundef [[AA:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK23-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK23-NEXT: entry:
|
||||
// CHECK23-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK23-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK23-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4
|
||||
// CHECK23-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK23-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135.omp_outlined, ptr [[AA_ADDR]])
|
||||
// CHECK23-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK23-NEXT: [[AA:%.*]] = alloca i16, align 2
|
||||
// CHECK23-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 4
|
||||
// CHECK23-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK23-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK23-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
|
||||
// CHECK23-NEXT: [[TMP2:%.*]] = load i16, ptr [[TMP1]], align 4
|
||||
// CHECK23-NEXT: store i16 [[TMP2]], ptr [[AA]], align 2
|
||||
// CHECK23-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
|
||||
// CHECK23-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK23-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
|
||||
// CHECK23-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135.omp_outlined, ptr [[AA]])
|
||||
// CHECK23-NEXT: ret void
|
||||
//
|
||||
//
|
||||
|
||||
@ -25,7 +25,7 @@ void target_maps_parallel_integer(int a){
|
||||
}
|
||||
}
|
||||
|
||||
// CK1-DEVICE: {{.*}}void @__omp_offloading_{{.*}}(ptr noundef nonnull align 4 dereferenceable(4){{.*}}, ptr {{[^)]+}})
|
||||
// CK1-DEVICE: {{.*}}void @__omp_offloading_{{.*}}(ptr noalias noundef %__context)
|
||||
|
||||
// CK1: {{.*}}void {{.*}}target_maps_parallel_integer{{.*}} {
|
||||
|
||||
|
||||
@ -2009,24 +2009,35 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l71
|
||||
// CHECK9-SAME: (i64 noundef [[N:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_1:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK9-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK9-NEXT: entry:
|
||||
// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[N:%.*]] = alloca i32, align 4
|
||||
// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
|
||||
// CHECK9-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
|
||||
// CHECK9-NEXT: [[DYN_PTR2:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB3:[0-9]+]])
|
||||
// CHECK9-NEXT: store i64 [[N]], ptr [[N_ADDR]], align 8
|
||||
// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8
|
||||
// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], ptr [[DOTCAPTURE_EXPR__ADDR2]], align 8
|
||||
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
|
||||
// CHECK9-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB3]], i32 [[TMP0]], i32 [[TMP1]], i32 0)
|
||||
// CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4
|
||||
// CHECK9-NEXT: store i32 [[TMP2]], ptr [[N_CASTED]], align 4
|
||||
// CHECK9-NEXT: [[TMP3:%.*]] = load i64, ptr [[N_CASTED]], align 8
|
||||
// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l71.omp_outlined, i64 [[TMP3]])
|
||||
// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 0
|
||||
// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 8
|
||||
// CHECK9-NEXT: store i32 [[TMP3]], ptr [[N]], align 4
|
||||
// CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 1
|
||||
// CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 8
|
||||
// CHECK9-NEXT: store i32 [[TMP5]], ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
// CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 2
|
||||
// CHECK9-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 8
|
||||
// CHECK9-NEXT: store i32 [[TMP7]], ptr [[DOTCAPTURE_EXPR_1]], align 4
|
||||
// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 3
|
||||
// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR2]], align 8
|
||||
// CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
// CHECK9-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB3]], i32 [[TMP0]], i32 [[TMP8]], i32 0)
|
||||
// CHECK9-NEXT: [[TMP9:%.*]] = load i32, ptr [[N]], align 4
|
||||
// CHECK9-NEXT: store i32 [[TMP9]], ptr [[N_CASTED]], align 4
|
||||
// CHECK9-NEXT: [[TMP10:%.*]] = load i64, ptr [[N_CASTED]], align 8
|
||||
// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l71.omp_outlined, i64 [[TMP10]])
|
||||
// CHECK9-NEXT: ret void
|
||||
//
|
||||
//
|
||||
@ -2237,12 +2248,19 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l75
|
||||
// CHECK9-SAME: (i64 noundef [[DOTCAPTURE_EXPR_:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK9-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK9-NEXT: entry:
|
||||
// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8
|
||||
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
|
||||
// CHECK9-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
|
||||
// CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 8
|
||||
// CHECK9-NEXT: store i32 [[TMP2]], ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
|
||||
// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
|
||||
// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l75.omp_outlined)
|
||||
// CHECK9-NEXT: ret void
|
||||
//
|
||||
@ -2258,22 +2276,30 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l88
|
||||
// CHECK9-SAME: (ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK9-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK9-NEXT: entry:
|
||||
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[B:%.*]] = alloca i32, align 4
|
||||
// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
|
||||
// CHECK9-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
|
||||
// CHECK9-NEXT: store i64 [[B]], ptr [[B_ADDR]], align 8
|
||||
// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8
|
||||
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP1:%.*]] = load i32, ptr [[B_ADDR]], align 4
|
||||
// CHECK9-NEXT: store i32 [[TMP1]], ptr [[B_CASTED]], align 4
|
||||
// CHECK9-NEXT: [[TMP2:%.*]] = load i64, ptr [[B_CASTED]], align 8
|
||||
// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l88.omp_outlined, ptr [[TMP0]], i64 [[TMP2]])
|
||||
// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
|
||||
// CHECK9-NEXT: [[THIS:%.*]] = load ptr, ptr [[TMP1]], align 8
|
||||
// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
|
||||
// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 8
|
||||
// CHECK9-NEXT: store i32 [[TMP3]], ptr [[B]], align 4
|
||||
// CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 2
|
||||
// CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 8
|
||||
// CHECK9-NEXT: store i32 [[TMP5]], ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 3
|
||||
// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
|
||||
// CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[B]], align 4
|
||||
// CHECK9-NEXT: store i32 [[TMP6]], ptr [[B_CASTED]], align 4
|
||||
// CHECK9-NEXT: [[TMP7:%.*]] = load i64, ptr [[B_CASTED]], align 8
|
||||
// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l88.omp_outlined, ptr [[THIS]], i64 [[TMP7]])
|
||||
// CHECK9-NEXT: ret void
|
||||
//
|
||||
//
|
||||
@ -2298,23 +2324,32 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l93
|
||||
// CHECK9-SAME: (ptr noundef [[THIS:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK9-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK9-NEXT: entry:
|
||||
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
|
||||
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 0
|
||||
// CHECK9-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
|
||||
// CHECK9-NEXT: [[THIS:%.*]] = load ptr, ptr [[TMP1]], align 8
|
||||
// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
|
||||
// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
|
||||
// CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[THIS]], i32 0, i32 0
|
||||
// CHECK9-NEXT: store double 2.500000e+00, ptr [[A]], align 8
|
||||
// CHECK9-NEXT: ret void
|
||||
//
|
||||
//
|
||||
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l55
|
||||
// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK9-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK9-NEXT: entry:
|
||||
// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
|
||||
// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
|
||||
// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l55.omp_outlined)
|
||||
// CHECK9-NEXT: ret void
|
||||
//
|
||||
@ -2330,29 +2365,40 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l60
|
||||
// CHECK9-SAME: (i64 noundef [[A:%.*]], i64 noundef [[B:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK9-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK9-NEXT: entry:
|
||||
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[A:%.*]] = alloca i32, align 4
|
||||
// CHECK9-NEXT: [[B:%.*]] = alloca i16, align 2
|
||||
// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2
|
||||
// CHECK9-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB3]])
|
||||
// CHECK9-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8
|
||||
// CHECK9-NEXT: store i64 [[B]], ptr [[B_ADDR]], align 8
|
||||
// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8
|
||||
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP1:%.*]] = load i16, ptr [[DOTCAPTURE_EXPR__ADDR]], align 2
|
||||
// CHECK9-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32
|
||||
// CHECK9-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB3]], i32 [[TMP0]], i32 [[TMP2]], i32 0)
|
||||
// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[A_ADDR]], align 4
|
||||
// CHECK9-NEXT: store i32 [[TMP3]], ptr [[A_CASTED]], align 4
|
||||
// CHECK9-NEXT: [[TMP4:%.*]] = load i64, ptr [[A_CASTED]], align 8
|
||||
// CHECK9-NEXT: [[TMP5:%.*]] = load i16, ptr [[B_ADDR]], align 2
|
||||
// CHECK9-NEXT: store i16 [[TMP5]], ptr [[B_CASTED]], align 2
|
||||
// CHECK9-NEXT: [[TMP6:%.*]] = load i64, ptr [[B_CASTED]], align 8
|
||||
// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l60.omp_outlined, i64 [[TMP4]], i64 [[TMP6]])
|
||||
// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 0
|
||||
// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 8
|
||||
// CHECK9-NEXT: store i32 [[TMP3]], ptr [[A]], align 4
|
||||
// CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 1
|
||||
// CHECK9-NEXT: [[TMP5:%.*]] = load i16, ptr [[TMP4]], align 8
|
||||
// CHECK9-NEXT: store i16 [[TMP5]], ptr [[B]], align 2
|
||||
// CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 2
|
||||
// CHECK9-NEXT: [[TMP7:%.*]] = load i16, ptr [[TMP6]], align 8
|
||||
// CHECK9-NEXT: store i16 [[TMP7]], ptr [[DOTCAPTURE_EXPR_]], align 2
|
||||
// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 3
|
||||
// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
|
||||
// CHECK9-NEXT: [[TMP8:%.*]] = load i16, ptr [[DOTCAPTURE_EXPR_]], align 2
|
||||
// CHECK9-NEXT: [[TMP9:%.*]] = sext i16 [[TMP8]] to i32
|
||||
// CHECK9-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB3]], i32 [[TMP0]], i32 [[TMP9]], i32 0)
|
||||
// CHECK9-NEXT: [[TMP10:%.*]] = load i32, ptr [[A]], align 4
|
||||
// CHECK9-NEXT: store i32 [[TMP10]], ptr [[A_CASTED]], align 4
|
||||
// CHECK9-NEXT: [[TMP11:%.*]] = load i64, ptr [[A_CASTED]], align 8
|
||||
// CHECK9-NEXT: [[TMP12:%.*]] = load i16, ptr [[B]], align 2
|
||||
// CHECK9-NEXT: store i16 [[TMP12]], ptr [[B_CASTED]], align 2
|
||||
// CHECK9-NEXT: [[TMP13:%.*]] = load i64, ptr [[B_CASTED]], align 8
|
||||
// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l60.omp_outlined, i64 [[TMP11]], i64 [[TMP13]])
|
||||
// CHECK9-NEXT: ret void
|
||||
//
|
||||
//
|
||||
@ -2376,24 +2422,35 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l71
|
||||
// CHECK11-SAME: (i32 noundef [[N:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]], i32 noundef [[DOTCAPTURE_EXPR_1:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK11-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK11-NEXT: entry:
|
||||
// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[N:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[DYN_PTR2:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB3:[0-9]+]])
|
||||
// CHECK11-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
|
||||
// CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
|
||||
// CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], ptr [[DOTCAPTURE_EXPR__ADDR2]], align 4
|
||||
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
|
||||
// CHECK11-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB3]], i32 [[TMP0]], i32 [[TMP1]], i32 0)
|
||||
// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4
|
||||
// CHECK11-NEXT: store i32 [[TMP2]], ptr [[N_CASTED]], align 4
|
||||
// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_CASTED]], align 4
|
||||
// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l71.omp_outlined, i32 [[TMP3]])
|
||||
// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 0
|
||||
// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
|
||||
// CHECK11-NEXT: store i32 [[TMP3]], ptr [[N]], align 4
|
||||
// CHECK11-NEXT: [[TMP4:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 1
|
||||
// CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
|
||||
// CHECK11-NEXT: store i32 [[TMP5]], ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
// CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 2
|
||||
// CHECK11-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4
|
||||
// CHECK11-NEXT: store i32 [[TMP7]], ptr [[DOTCAPTURE_EXPR_1]], align 4
|
||||
// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 3
|
||||
// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR2]], align 4
|
||||
// CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
// CHECK11-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB3]], i32 [[TMP0]], i32 [[TMP8]], i32 0)
|
||||
// CHECK11-NEXT: [[TMP9:%.*]] = load i32, ptr [[N]], align 4
|
||||
// CHECK11-NEXT: store i32 [[TMP9]], ptr [[N_CASTED]], align 4
|
||||
// CHECK11-NEXT: [[TMP10:%.*]] = load i32, ptr [[N_CASTED]], align 4
|
||||
// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l71.omp_outlined, i32 [[TMP10]])
|
||||
// CHECK11-NEXT: ret void
|
||||
//
|
||||
//
|
||||
@ -2600,12 +2657,19 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l75
|
||||
// CHECK11-SAME: (i32 noundef [[DOTCAPTURE_EXPR_:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK11-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK11-NEXT: entry:
|
||||
// CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
|
||||
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
|
||||
// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
|
||||
// CHECK11-NEXT: store i32 [[TMP2]], ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
|
||||
// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
|
||||
// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l75.omp_outlined)
|
||||
// CHECK11-NEXT: ret void
|
||||
//
|
||||
@ -2621,22 +2685,30 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l88
|
||||
// CHECK11-SAME: (ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK11-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK11-NEXT: entry:
|
||||
// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[B:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
|
||||
// CHECK11-NEXT: store i32 [[B]], ptr [[B_ADDR]], align 4
|
||||
// CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
|
||||
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[B_ADDR]], align 4
|
||||
// CHECK11-NEXT: store i32 [[TMP1]], ptr [[B_CASTED]], align 4
|
||||
// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[B_CASTED]], align 4
|
||||
// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l88.omp_outlined, ptr [[TMP0]], i32 [[TMP2]])
|
||||
// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
|
||||
// CHECK11-NEXT: [[THIS:%.*]] = load ptr, ptr [[TMP1]], align 4
|
||||
// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
|
||||
// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
|
||||
// CHECK11-NEXT: store i32 [[TMP3]], ptr [[B]], align 4
|
||||
// CHECK11-NEXT: [[TMP4:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 2
|
||||
// CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
|
||||
// CHECK11-NEXT: store i32 [[TMP5]], ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 3
|
||||
// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
|
||||
// CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[B]], align 4
|
||||
// CHECK11-NEXT: store i32 [[TMP6]], ptr [[B_CASTED]], align 4
|
||||
// CHECK11-NEXT: [[TMP7:%.*]] = load i32, ptr [[B_CASTED]], align 4
|
||||
// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l88.omp_outlined, ptr [[THIS]], i32 [[TMP7]])
|
||||
// CHECK11-NEXT: ret void
|
||||
//
|
||||
//
|
||||
@ -2661,23 +2733,32 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l93
|
||||
// CHECK11-SAME: (ptr noundef [[THIS:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK11-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK11-NEXT: entry:
|
||||
// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
|
||||
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 0
|
||||
// CHECK11-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
|
||||
// CHECK11-NEXT: [[THIS:%.*]] = load ptr, ptr [[TMP1]], align 4
|
||||
// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
|
||||
// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
|
||||
// CHECK11-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[THIS]], i32 0, i32 0
|
||||
// CHECK11-NEXT: store double 2.500000e+00, ptr [[A]], align 4
|
||||
// CHECK11-NEXT: ret void
|
||||
//
|
||||
//
|
||||
// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l55
|
||||
// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK11-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK11-NEXT: entry:
|
||||
// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
|
||||
// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
|
||||
// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l55.omp_outlined)
|
||||
// CHECK11-NEXT: ret void
|
||||
//
|
||||
@ -2693,29 +2774,40 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l60
|
||||
// CHECK11-SAME: (i32 noundef [[A:%.*]], i32 noundef [[B:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK11-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK11-NEXT: entry:
|
||||
// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[A:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[B:%.*]] = alloca i16, align 2
|
||||
// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2
|
||||
// CHECK11-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB3]])
|
||||
// CHECK11-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
|
||||
// CHECK11-NEXT: store i32 [[B]], ptr [[B_ADDR]], align 4
|
||||
// CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
|
||||
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP1:%.*]] = load i16, ptr [[DOTCAPTURE_EXPR__ADDR]], align 2
|
||||
// CHECK11-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32
|
||||
// CHECK11-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB3]], i32 [[TMP0]], i32 [[TMP2]], i32 0)
|
||||
// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[A_ADDR]], align 4
|
||||
// CHECK11-NEXT: store i32 [[TMP3]], ptr [[A_CASTED]], align 4
|
||||
// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[A_CASTED]], align 4
|
||||
// CHECK11-NEXT: [[TMP5:%.*]] = load i16, ptr [[B_ADDR]], align 2
|
||||
// CHECK11-NEXT: store i16 [[TMP5]], ptr [[B_CASTED]], align 2
|
||||
// CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[B_CASTED]], align 4
|
||||
// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l60.omp_outlined, i32 [[TMP4]], i32 [[TMP6]])
|
||||
// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 0
|
||||
// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
|
||||
// CHECK11-NEXT: store i32 [[TMP3]], ptr [[A]], align 4
|
||||
// CHECK11-NEXT: [[TMP4:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 1
|
||||
// CHECK11-NEXT: [[TMP5:%.*]] = load i16, ptr [[TMP4]], align 4
|
||||
// CHECK11-NEXT: store i16 [[TMP5]], ptr [[B]], align 2
|
||||
// CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 2
|
||||
// CHECK11-NEXT: [[TMP7:%.*]] = load i16, ptr [[TMP6]], align 4
|
||||
// CHECK11-NEXT: store i16 [[TMP7]], ptr [[DOTCAPTURE_EXPR_]], align 2
|
||||
// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 3
|
||||
// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
|
||||
// CHECK11-NEXT: [[TMP8:%.*]] = load i16, ptr [[DOTCAPTURE_EXPR_]], align 2
|
||||
// CHECK11-NEXT: [[TMP9:%.*]] = sext i16 [[TMP8]] to i32
|
||||
// CHECK11-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB3]], i32 [[TMP0]], i32 [[TMP9]], i32 0)
|
||||
// CHECK11-NEXT: [[TMP10:%.*]] = load i32, ptr [[A]], align 4
|
||||
// CHECK11-NEXT: store i32 [[TMP10]], ptr [[A_CASTED]], align 4
|
||||
// CHECK11-NEXT: [[TMP11:%.*]] = load i32, ptr [[A_CASTED]], align 4
|
||||
// CHECK11-NEXT: [[TMP12:%.*]] = load i16, ptr [[B]], align 2
|
||||
// CHECK11-NEXT: store i16 [[TMP12]], ptr [[B_CASTED]], align 2
|
||||
// CHECK11-NEXT: [[TMP13:%.*]] = load i32, ptr [[B_CASTED]], align 4
|
||||
// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l60.omp_outlined, i32 [[TMP11]], i32 [[TMP13]])
|
||||
// CHECK11-NEXT: ret void
|
||||
//
|
||||
//
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -2042,24 +2042,35 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104
|
||||
// CHECK9-SAME: (i64 noundef [[N:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_1:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK9-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK9-NEXT: entry:
|
||||
// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[N:%.*]] = alloca i32, align 4
|
||||
// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
|
||||
// CHECK9-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
|
||||
// CHECK9-NEXT: [[DYN_PTR2:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB3:[0-9]+]])
|
||||
// CHECK9-NEXT: store i64 [[N]], ptr [[N_ADDR]], align 8
|
||||
// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8
|
||||
// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], ptr [[DOTCAPTURE_EXPR__ADDR2]], align 8
|
||||
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
|
||||
// CHECK9-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB3]], i32 [[TMP0]], i32 [[TMP1]], i32 0)
|
||||
// CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4
|
||||
// CHECK9-NEXT: store i32 [[TMP2]], ptr [[N_CASTED]], align 4
|
||||
// CHECK9-NEXT: [[TMP3:%.*]] = load i64, ptr [[N_CASTED]], align 8
|
||||
// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104.omp_outlined, i64 [[TMP3]])
|
||||
// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 0
|
||||
// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 8
|
||||
// CHECK9-NEXT: store i32 [[TMP3]], ptr [[N]], align 4
|
||||
// CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 1
|
||||
// CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 8
|
||||
// CHECK9-NEXT: store i32 [[TMP5]], ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
// CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 2
|
||||
// CHECK9-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 8
|
||||
// CHECK9-NEXT: store i32 [[TMP7]], ptr [[DOTCAPTURE_EXPR_1]], align 4
|
||||
// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 3
|
||||
// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR2]], align 8
|
||||
// CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
// CHECK9-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB3]], i32 [[TMP0]], i32 [[TMP8]], i32 0)
|
||||
// CHECK9-NEXT: [[TMP9:%.*]] = load i32, ptr [[N]], align 4
|
||||
// CHECK9-NEXT: store i32 [[TMP9]], ptr [[N_CASTED]], align 4
|
||||
// CHECK9-NEXT: [[TMP10:%.*]] = load i64, ptr [[N_CASTED]], align 8
|
||||
// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104.omp_outlined, i64 [[TMP10]])
|
||||
// CHECK9-NEXT: ret void
|
||||
//
|
||||
//
|
||||
@ -2270,12 +2281,19 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108
|
||||
// CHECK9-SAME: (i64 noundef [[DOTCAPTURE_EXPR_:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK9-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK9-NEXT: entry:
|
||||
// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8
|
||||
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
|
||||
// CHECK9-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
|
||||
// CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 8
|
||||
// CHECK9-NEXT: store i32 [[TMP2]], ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
|
||||
// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
|
||||
// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108.omp_outlined)
|
||||
// CHECK9-NEXT: ret void
|
||||
//
|
||||
@ -2291,22 +2309,30 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121
|
||||
// CHECK9-SAME: (ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK9-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK9-NEXT: entry:
|
||||
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[B:%.*]] = alloca i32, align 4
|
||||
// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
|
||||
// CHECK9-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
|
||||
// CHECK9-NEXT: store i64 [[B]], ptr [[B_ADDR]], align 8
|
||||
// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8
|
||||
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP1:%.*]] = load i32, ptr [[B_ADDR]], align 4
|
||||
// CHECK9-NEXT: store i32 [[TMP1]], ptr [[B_CASTED]], align 4
|
||||
// CHECK9-NEXT: [[TMP2:%.*]] = load i64, ptr [[B_CASTED]], align 8
|
||||
// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.omp_outlined, ptr [[TMP0]], i64 [[TMP2]])
|
||||
// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
|
||||
// CHECK9-NEXT: [[THIS:%.*]] = load ptr, ptr [[TMP1]], align 8
|
||||
// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
|
||||
// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 8
|
||||
// CHECK9-NEXT: store i32 [[TMP3]], ptr [[B]], align 4
|
||||
// CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 2
|
||||
// CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 8
|
||||
// CHECK9-NEXT: store i32 [[TMP5]], ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 3
|
||||
// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
|
||||
// CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[B]], align 4
|
||||
// CHECK9-NEXT: store i32 [[TMP6]], ptr [[B_CASTED]], align 4
|
||||
// CHECK9-NEXT: [[TMP7:%.*]] = load i64, ptr [[B_CASTED]], align 8
|
||||
// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.omp_outlined, ptr [[THIS]], i64 [[TMP7]])
|
||||
// CHECK9-NEXT: ret void
|
||||
//
|
||||
//
|
||||
@ -2331,23 +2357,32 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126
|
||||
// CHECK9-SAME: (ptr noundef [[THIS:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK9-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK9-NEXT: entry:
|
||||
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
|
||||
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 0
|
||||
// CHECK9-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
|
||||
// CHECK9-NEXT: [[THIS:%.*]] = load ptr, ptr [[TMP1]], align 8
|
||||
// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
|
||||
// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
|
||||
// CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[THIS]], i32 0, i32 0
|
||||
// CHECK9-NEXT: store double 2.500000e+00, ptr [[A]], align 8
|
||||
// CHECK9-NEXT: ret void
|
||||
//
|
||||
//
|
||||
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88
|
||||
// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK9-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK9-NEXT: entry:
|
||||
// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
|
||||
// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
|
||||
// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88.omp_outlined)
|
||||
// CHECK9-NEXT: ret void
|
||||
//
|
||||
@ -2363,29 +2398,40 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93
|
||||
// CHECK9-SAME: (i64 noundef [[A:%.*]], i64 noundef [[B:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK9-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK9-NEXT: entry:
|
||||
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[A:%.*]] = alloca i32, align 4
|
||||
// CHECK9-NEXT: [[B:%.*]] = alloca i16, align 2
|
||||
// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2
|
||||
// CHECK9-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB3]])
|
||||
// CHECK9-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8
|
||||
// CHECK9-NEXT: store i64 [[B]], ptr [[B_ADDR]], align 8
|
||||
// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8
|
||||
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP1:%.*]] = load i16, ptr [[DOTCAPTURE_EXPR__ADDR]], align 2
|
||||
// CHECK9-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32
|
||||
// CHECK9-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB3]], i32 [[TMP0]], i32 [[TMP2]], i32 0)
|
||||
// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[A_ADDR]], align 4
|
||||
// CHECK9-NEXT: store i32 [[TMP3]], ptr [[A_CASTED]], align 4
|
||||
// CHECK9-NEXT: [[TMP4:%.*]] = load i64, ptr [[A_CASTED]], align 8
|
||||
// CHECK9-NEXT: [[TMP5:%.*]] = load i16, ptr [[B_ADDR]], align 2
|
||||
// CHECK9-NEXT: store i16 [[TMP5]], ptr [[B_CASTED]], align 2
|
||||
// CHECK9-NEXT: [[TMP6:%.*]] = load i64, ptr [[B_CASTED]], align 8
|
||||
// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93.omp_outlined, i64 [[TMP4]], i64 [[TMP6]])
|
||||
// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 0
|
||||
// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 8
|
||||
// CHECK9-NEXT: store i32 [[TMP3]], ptr [[A]], align 4
|
||||
// CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 1
|
||||
// CHECK9-NEXT: [[TMP5:%.*]] = load i16, ptr [[TMP4]], align 8
|
||||
// CHECK9-NEXT: store i16 [[TMP5]], ptr [[B]], align 2
|
||||
// CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 2
|
||||
// CHECK9-NEXT: [[TMP7:%.*]] = load i16, ptr [[TMP6]], align 8
|
||||
// CHECK9-NEXT: store i16 [[TMP7]], ptr [[DOTCAPTURE_EXPR_]], align 2
|
||||
// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 3
|
||||
// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
|
||||
// CHECK9-NEXT: [[TMP8:%.*]] = load i16, ptr [[DOTCAPTURE_EXPR_]], align 2
|
||||
// CHECK9-NEXT: [[TMP9:%.*]] = sext i16 [[TMP8]] to i32
|
||||
// CHECK9-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB3]], i32 [[TMP0]], i32 [[TMP9]], i32 0)
|
||||
// CHECK9-NEXT: [[TMP10:%.*]] = load i32, ptr [[A]], align 4
|
||||
// CHECK9-NEXT: store i32 [[TMP10]], ptr [[A_CASTED]], align 4
|
||||
// CHECK9-NEXT: [[TMP11:%.*]] = load i64, ptr [[A_CASTED]], align 8
|
||||
// CHECK9-NEXT: [[TMP12:%.*]] = load i16, ptr [[B]], align 2
|
||||
// CHECK9-NEXT: store i16 [[TMP12]], ptr [[B_CASTED]], align 2
|
||||
// CHECK9-NEXT: [[TMP13:%.*]] = load i64, ptr [[B_CASTED]], align 8
|
||||
// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93.omp_outlined, i64 [[TMP11]], i64 [[TMP13]])
|
||||
// CHECK9-NEXT: ret void
|
||||
//
|
||||
//
|
||||
@ -2409,24 +2455,35 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104
|
||||
// CHECK11-SAME: (i32 noundef [[N:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]], i32 noundef [[DOTCAPTURE_EXPR_1:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK11-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK11-NEXT: entry:
|
||||
// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[N:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[DYN_PTR2:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB3:[0-9]+]])
|
||||
// CHECK11-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
|
||||
// CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
|
||||
// CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], ptr [[DOTCAPTURE_EXPR__ADDR2]], align 4
|
||||
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
|
||||
// CHECK11-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB3]], i32 [[TMP0]], i32 [[TMP1]], i32 0)
|
||||
// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4
|
||||
// CHECK11-NEXT: store i32 [[TMP2]], ptr [[N_CASTED]], align 4
|
||||
// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_CASTED]], align 4
|
||||
// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104.omp_outlined, i32 [[TMP3]])
|
||||
// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 0
|
||||
// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
|
||||
// CHECK11-NEXT: store i32 [[TMP3]], ptr [[N]], align 4
|
||||
// CHECK11-NEXT: [[TMP4:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 1
|
||||
// CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
|
||||
// CHECK11-NEXT: store i32 [[TMP5]], ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
// CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 2
|
||||
// CHECK11-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4
|
||||
// CHECK11-NEXT: store i32 [[TMP7]], ptr [[DOTCAPTURE_EXPR_1]], align 4
|
||||
// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 3
|
||||
// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR2]], align 4
|
||||
// CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
// CHECK11-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB3]], i32 [[TMP0]], i32 [[TMP8]], i32 0)
|
||||
// CHECK11-NEXT: [[TMP9:%.*]] = load i32, ptr [[N]], align 4
|
||||
// CHECK11-NEXT: store i32 [[TMP9]], ptr [[N_CASTED]], align 4
|
||||
// CHECK11-NEXT: [[TMP10:%.*]] = load i32, ptr [[N_CASTED]], align 4
|
||||
// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104.omp_outlined, i32 [[TMP10]])
|
||||
// CHECK11-NEXT: ret void
|
||||
//
|
||||
//
|
||||
@ -2633,12 +2690,19 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108
|
||||
// CHECK11-SAME: (i32 noundef [[DOTCAPTURE_EXPR_:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK11-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK11-NEXT: entry:
|
||||
// CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
|
||||
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
|
||||
// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
|
||||
// CHECK11-NEXT: store i32 [[TMP2]], ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
|
||||
// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
|
||||
// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108.omp_outlined)
|
||||
// CHECK11-NEXT: ret void
|
||||
//
|
||||
@ -2654,22 +2718,30 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121
|
||||
// CHECK11-SAME: (ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK11-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK11-NEXT: entry:
|
||||
// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[B:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
|
||||
// CHECK11-NEXT: store i32 [[B]], ptr [[B_ADDR]], align 4
|
||||
// CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
|
||||
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[B_ADDR]], align 4
|
||||
// CHECK11-NEXT: store i32 [[TMP1]], ptr [[B_CASTED]], align 4
|
||||
// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[B_CASTED]], align 4
|
||||
// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.omp_outlined, ptr [[TMP0]], i32 [[TMP2]])
|
||||
// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
|
||||
// CHECK11-NEXT: [[THIS:%.*]] = load ptr, ptr [[TMP1]], align 4
|
||||
// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
|
||||
// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
|
||||
// CHECK11-NEXT: store i32 [[TMP3]], ptr [[B]], align 4
|
||||
// CHECK11-NEXT: [[TMP4:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 2
|
||||
// CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
|
||||
// CHECK11-NEXT: store i32 [[TMP5]], ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 3
|
||||
// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
|
||||
// CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[B]], align 4
|
||||
// CHECK11-NEXT: store i32 [[TMP6]], ptr [[B_CASTED]], align 4
|
||||
// CHECK11-NEXT: [[TMP7:%.*]] = load i32, ptr [[B_CASTED]], align 4
|
||||
// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.omp_outlined, ptr [[THIS]], i32 [[TMP7]])
|
||||
// CHECK11-NEXT: ret void
|
||||
//
|
||||
//
|
||||
@ -2694,23 +2766,32 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126
|
||||
// CHECK11-SAME: (ptr noundef [[THIS:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK11-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK11-NEXT: entry:
|
||||
// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
|
||||
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 0
|
||||
// CHECK11-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
|
||||
// CHECK11-NEXT: [[THIS:%.*]] = load ptr, ptr [[TMP1]], align 4
|
||||
// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
|
||||
// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
|
||||
// CHECK11-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[THIS]], i32 0, i32 0
|
||||
// CHECK11-NEXT: store double 2.500000e+00, ptr [[A]], align 4
|
||||
// CHECK11-NEXT: ret void
|
||||
//
|
||||
//
|
||||
// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88
|
||||
// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK11-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK11-NEXT: entry:
|
||||
// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
|
||||
// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
|
||||
// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88.omp_outlined)
|
||||
// CHECK11-NEXT: ret void
|
||||
//
|
||||
@ -2726,29 +2807,40 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93
|
||||
// CHECK11-SAME: (i32 noundef [[A:%.*]], i32 noundef [[B:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK11-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK11-NEXT: entry:
|
||||
// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[A:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[B:%.*]] = alloca i16, align 2
|
||||
// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2
|
||||
// CHECK11-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB3]])
|
||||
// CHECK11-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
|
||||
// CHECK11-NEXT: store i32 [[B]], ptr [[B_ADDR]], align 4
|
||||
// CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
|
||||
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP1:%.*]] = load i16, ptr [[DOTCAPTURE_EXPR__ADDR]], align 2
|
||||
// CHECK11-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32
|
||||
// CHECK11-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB3]], i32 [[TMP0]], i32 [[TMP2]], i32 0)
|
||||
// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[A_ADDR]], align 4
|
||||
// CHECK11-NEXT: store i32 [[TMP3]], ptr [[A_CASTED]], align 4
|
||||
// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[A_CASTED]], align 4
|
||||
// CHECK11-NEXT: [[TMP5:%.*]] = load i16, ptr [[B_ADDR]], align 2
|
||||
// CHECK11-NEXT: store i16 [[TMP5]], ptr [[B_CASTED]], align 2
|
||||
// CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[B_CASTED]], align 4
|
||||
// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93.omp_outlined, i32 [[TMP4]], i32 [[TMP6]])
|
||||
// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 0
|
||||
// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
|
||||
// CHECK11-NEXT: store i32 [[TMP3]], ptr [[A]], align 4
|
||||
// CHECK11-NEXT: [[TMP4:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 1
|
||||
// CHECK11-NEXT: [[TMP5:%.*]] = load i16, ptr [[TMP4]], align 4
|
||||
// CHECK11-NEXT: store i16 [[TMP5]], ptr [[B]], align 2
|
||||
// CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 2
|
||||
// CHECK11-NEXT: [[TMP7:%.*]] = load i16, ptr [[TMP6]], align 4
|
||||
// CHECK11-NEXT: store i16 [[TMP7]], ptr [[DOTCAPTURE_EXPR_]], align 2
|
||||
// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 3
|
||||
// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
|
||||
// CHECK11-NEXT: [[TMP8:%.*]] = load i16, ptr [[DOTCAPTURE_EXPR_]], align 2
|
||||
// CHECK11-NEXT: [[TMP9:%.*]] = sext i16 [[TMP8]] to i32
|
||||
// CHECK11-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB3]], i32 [[TMP0]], i32 [[TMP9]], i32 0)
|
||||
// CHECK11-NEXT: [[TMP10:%.*]] = load i32, ptr [[A]], align 4
|
||||
// CHECK11-NEXT: store i32 [[TMP10]], ptr [[A_CASTED]], align 4
|
||||
// CHECK11-NEXT: [[TMP11:%.*]] = load i32, ptr [[A_CASTED]], align 4
|
||||
// CHECK11-NEXT: [[TMP12:%.*]] = load i16, ptr [[B]], align 2
|
||||
// CHECK11-NEXT: store i16 [[TMP12]], ptr [[B_CASTED]], align 2
|
||||
// CHECK11-NEXT: [[TMP13:%.*]] = load i32, ptr [[B_CASTED]], align 4
|
||||
// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93.omp_outlined, i32 [[TMP11]], i32 [[TMP13]])
|
||||
// CHECK11-NEXT: ret void
|
||||
//
|
||||
//
|
||||
|
||||
@ -2692,10 +2692,15 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100
|
||||
// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK9-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK9-NEXT: entry:
|
||||
// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
|
||||
// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
|
||||
// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1:[0-9]+]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100.omp_outlined)
|
||||
// CHECK9-NEXT: ret void
|
||||
//
|
||||
@ -2711,17 +2716,24 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110
|
||||
// CHECK9-SAME: (i64 noundef [[AA:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK9-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK9-NEXT: entry:
|
||||
// CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[AA:%.*]] = alloca i16, align 2
|
||||
// CHECK9-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8
|
||||
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP0:%.*]] = load i16, ptr [[AA_ADDR]], align 2
|
||||
// CHECK9-NEXT: store i16 [[TMP0]], ptr [[AA_CASTED]], align 2
|
||||
// CHECK9-NEXT: [[TMP1:%.*]] = load i64, ptr [[AA_CASTED]], align 8
|
||||
// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110.omp_outlined, i64 [[TMP1]])
|
||||
// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
|
||||
// CHECK9-NEXT: [[TMP2:%.*]] = load i16, ptr [[TMP1]], align 8
|
||||
// CHECK9-NEXT: store i16 [[TMP2]], ptr [[AA]], align 2
|
||||
// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
|
||||
// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
|
||||
// CHECK9-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA]], align 2
|
||||
// CHECK9-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2
|
||||
// CHECK9-NEXT: [[TMP4:%.*]] = load i64, ptr [[AA_CASTED]], align 8
|
||||
// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110.omp_outlined, i64 [[TMP4]])
|
||||
// CHECK9-NEXT: ret void
|
||||
//
|
||||
//
|
||||
@ -2752,23 +2764,32 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119
|
||||
// CHECK9-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK9-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK9-NEXT: entry:
|
||||
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[A:%.*]] = alloca i32, align 4
|
||||
// CHECK9-NEXT: [[AA:%.*]] = alloca i16, align 2
|
||||
// CHECK9-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8
|
||||
// CHECK9-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8
|
||||
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
|
||||
// CHECK9-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4
|
||||
// CHECK9-NEXT: [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 8
|
||||
// CHECK9-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 2
|
||||
// CHECK9-NEXT: store i16 [[TMP2]], ptr [[AA_CASTED]], align 2
|
||||
// CHECK9-NEXT: [[TMP3:%.*]] = load i64, ptr [[AA_CASTED]], align 8
|
||||
// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119.omp_outlined, i64 [[TMP1]], i64 [[TMP3]])
|
||||
// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
|
||||
// CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 8
|
||||
// CHECK9-NEXT: store i32 [[TMP2]], ptr [[A]], align 4
|
||||
// CHECK9-NEXT: [[TMP3:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
|
||||
// CHECK9-NEXT: [[TMP4:%.*]] = load i16, ptr [[TMP3]], align 8
|
||||
// CHECK9-NEXT: store i16 [[TMP4]], ptr [[AA]], align 2
|
||||
// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 2
|
||||
// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
|
||||
// CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[A]], align 4
|
||||
// CHECK9-NEXT: store i32 [[TMP5]], ptr [[A_CASTED]], align 4
|
||||
// CHECK9-NEXT: [[TMP6:%.*]] = load i64, ptr [[A_CASTED]], align 8
|
||||
// CHECK9-NEXT: [[TMP7:%.*]] = load i16, ptr [[AA]], align 2
|
||||
// CHECK9-NEXT: store i16 [[TMP7]], ptr [[AA_CASTED]], align 2
|
||||
// CHECK9-NEXT: [[TMP8:%.*]] = load i64, ptr [[AA_CASTED]], align 8
|
||||
// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119.omp_outlined, i64 [[TMP6]], i64 [[TMP8]])
|
||||
// CHECK9-NEXT: ret void
|
||||
//
|
||||
//
|
||||
@ -2795,41 +2816,40 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144
|
||||
// CHECK9-SAME: (i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 8 dereferenceable(16) [[D:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK9-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK9-NEXT: entry:
|
||||
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[A:%.*]] = alloca i32, align 4
|
||||
// CHECK9-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8
|
||||
// CHECK9-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
|
||||
// CHECK9-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8
|
||||
// CHECK9-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 8
|
||||
// CHECK9-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8
|
||||
// CHECK9-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8
|
||||
// CHECK9-NEXT: store i64 [[VLA3]], ptr [[VLA_ADDR4]], align 8
|
||||
// CHECK9-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 8
|
||||
// CHECK9-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8
|
||||
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META19:![0-9]+]], !align [[META20:![0-9]+]]
|
||||
// CHECK9-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 8, !nonnull [[META19]], !align [[META20]]
|
||||
// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !nonnull [[META19]], !align [[META21:![0-9]+]]
|
||||
// CHECK9-NEXT: [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8
|
||||
// CHECK9-NEXT: [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR4]], align 8
|
||||
// CHECK9-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 8, !nonnull [[META19]], !align [[META21]]
|
||||
// CHECK9-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 8, !nonnull [[META19]], !align [[META21]]
|
||||
// CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4
|
||||
// CHECK9-NEXT: store i32 [[TMP8]], ptr [[A_CASTED]], align 4
|
||||
// CHECK9-NEXT: [[TMP9:%.*]] = load i64, ptr [[A_CASTED]], align 8
|
||||
// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 9, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144.omp_outlined, i64 [[TMP9]], ptr [[TMP0]], i64 [[TMP1]], ptr [[TMP2]], ptr [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], ptr [[TMP6]], ptr [[TMP7]])
|
||||
// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
|
||||
// CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 8
|
||||
// CHECK9-NEXT: store i32 [[TMP2]], ptr [[A]], align 4
|
||||
// CHECK9-NEXT: [[TMP3:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
|
||||
// CHECK9-NEXT: [[B:%.*]] = load ptr, ptr [[TMP3]], align 8
|
||||
// CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 2
|
||||
// CHECK9-NEXT: [[TMP5:%.*]] = load i64, ptr [[TMP4]], align 8
|
||||
// CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 3
|
||||
// CHECK9-NEXT: [[BN:%.*]] = load ptr, ptr [[TMP6]], align 8
|
||||
// CHECK9-NEXT: [[TMP7:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 4
|
||||
// CHECK9-NEXT: [[C:%.*]] = load ptr, ptr [[TMP7]], align 8
|
||||
// CHECK9-NEXT: [[TMP8:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 5
|
||||
// CHECK9-NEXT: [[TMP9:%.*]] = load i64, ptr [[TMP8]], align 8
|
||||
// CHECK9-NEXT: [[TMP10:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 6
|
||||
// CHECK9-NEXT: [[TMP11:%.*]] = load i64, ptr [[TMP10]], align 8
|
||||
// CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 7
|
||||
// CHECK9-NEXT: [[CN:%.*]] = load ptr, ptr [[TMP12]], align 8
|
||||
// CHECK9-NEXT: [[TMP13:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 8
|
||||
// CHECK9-NEXT: [[D:%.*]] = load ptr, ptr [[TMP13]], align 8
|
||||
// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 9
|
||||
// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
|
||||
// CHECK9-NEXT: [[TMP14:%.*]] = load i32, ptr [[A]], align 4
|
||||
// CHECK9-NEXT: store i32 [[TMP14]], ptr [[A_CASTED]], align 4
|
||||
// CHECK9-NEXT: [[TMP15:%.*]] = load i64, ptr [[A_CASTED]], align 8
|
||||
// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 9, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144.omp_outlined, i64 [[TMP15]], ptr [[B]], i64 [[TMP5]], ptr [[BN]], ptr [[C]], i64 [[TMP9]], i64 [[TMP11]], ptr [[CN]], ptr [[D]])
|
||||
// CHECK9-NEXT: ret void
|
||||
//
|
||||
//
|
||||
@ -2858,10 +2878,10 @@ int bar(int n){
|
||||
// CHECK9-NEXT: store i64 [[VLA3]], ptr [[VLA_ADDR4]], align 8
|
||||
// CHECK9-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 8
|
||||
// CHECK9-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META19]], !align [[META20]]
|
||||
// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META19:![0-9]+]], !align [[META20:![0-9]+]]
|
||||
// CHECK9-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 8, !nonnull [[META19]], !align [[META20]]
|
||||
// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !nonnull [[META19]], !align [[META21]]
|
||||
// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !nonnull [[META19]], !align [[META21:![0-9]+]]
|
||||
// CHECK9-NEXT: [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8
|
||||
// CHECK9-NEXT: [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR4]], align 8
|
||||
// CHECK9-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 8, !nonnull [[META19]], !align [[META21]]
|
||||
@ -2906,32 +2926,42 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198
|
||||
// CHECK9-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK9-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK9-NEXT: entry:
|
||||
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[A:%.*]] = alloca i32, align 4
|
||||
// CHECK9-NEXT: [[AA:%.*]] = alloca i16, align 2
|
||||
// CHECK9-NEXT: [[AAA:%.*]] = alloca i8, align 1
|
||||
// CHECK9-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8
|
||||
// CHECK9-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8
|
||||
// CHECK9-NEXT: store i64 [[AAA]], ptr [[AAA_ADDR]], align 8
|
||||
// CHECK9-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
|
||||
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META19]], !align [[META20]]
|
||||
// CHECK9-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
|
||||
// CHECK9-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4
|
||||
// CHECK9-NEXT: [[TMP2:%.*]] = load i64, ptr [[A_CASTED]], align 8
|
||||
// CHECK9-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2
|
||||
// CHECK9-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2
|
||||
// CHECK9-NEXT: [[TMP4:%.*]] = load i64, ptr [[AA_CASTED]], align 8
|
||||
// CHECK9-NEXT: [[TMP5:%.*]] = load i8, ptr [[AAA_ADDR]], align 1
|
||||
// CHECK9-NEXT: store i8 [[TMP5]], ptr [[AAA_CASTED]], align 1
|
||||
// CHECK9-NEXT: [[TMP6:%.*]] = load i64, ptr [[AAA_CASTED]], align 8
|
||||
// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198.omp_outlined, i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], ptr [[TMP0]])
|
||||
// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
|
||||
// CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 8
|
||||
// CHECK9-NEXT: store i32 [[TMP2]], ptr [[A]], align 4
|
||||
// CHECK9-NEXT: [[TMP3:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
|
||||
// CHECK9-NEXT: [[TMP4:%.*]] = load i16, ptr [[TMP3]], align 8
|
||||
// CHECK9-NEXT: store i16 [[TMP4]], ptr [[AA]], align 2
|
||||
// CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 2
|
||||
// CHECK9-NEXT: [[TMP6:%.*]] = load i8, ptr [[TMP5]], align 8
|
||||
// CHECK9-NEXT: store i8 [[TMP6]], ptr [[AAA]], align 1
|
||||
// CHECK9-NEXT: [[TMP7:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 3
|
||||
// CHECK9-NEXT: [[B:%.*]] = load ptr, ptr [[TMP7]], align 8
|
||||
// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 4
|
||||
// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
|
||||
// CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 4
|
||||
// CHECK9-NEXT: store i32 [[TMP8]], ptr [[A_CASTED]], align 4
|
||||
// CHECK9-NEXT: [[TMP9:%.*]] = load i64, ptr [[A_CASTED]], align 8
|
||||
// CHECK9-NEXT: [[TMP10:%.*]] = load i16, ptr [[AA]], align 2
|
||||
// CHECK9-NEXT: store i16 [[TMP10]], ptr [[AA_CASTED]], align 2
|
||||
// CHECK9-NEXT: [[TMP11:%.*]] = load i64, ptr [[AA_CASTED]], align 8
|
||||
// CHECK9-NEXT: [[TMP12:%.*]] = load i8, ptr [[AAA]], align 1
|
||||
// CHECK9-NEXT: store i8 [[TMP12]], ptr [[AAA_CASTED]], align 1
|
||||
// CHECK9-NEXT: [[TMP13:%.*]] = load i64, ptr [[AAA_CASTED]], align 8
|
||||
// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198.omp_outlined, i64 [[TMP9]], i64 [[TMP11]], i64 [[TMP13]], ptr [[B]])
|
||||
// CHECK9-NEXT: ret void
|
||||
//
|
||||
//
|
||||
@ -2972,29 +3002,32 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216
|
||||
// CHECK9-SAME: (ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK9-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK9-NEXT: entry:
|
||||
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[B:%.*]] = alloca i32, align 4
|
||||
// CHECK9-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
|
||||
// CHECK9-NEXT: store i64 [[B]], ptr [[B_ADDR]], align 8
|
||||
// CHECK9-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8
|
||||
// CHECK9-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8
|
||||
// CHECK9-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8
|
||||
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8
|
||||
// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !nonnull [[META19]], !align [[META22:![0-9]+]]
|
||||
// CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[B_ADDR]], align 4
|
||||
// CHECK9-NEXT: store i32 [[TMP4]], ptr [[B_CASTED]], align 4
|
||||
// CHECK9-NEXT: [[TMP5:%.*]] = load i64, ptr [[B_CASTED]], align 8
|
||||
// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216.omp_outlined, ptr [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], ptr [[TMP3]])
|
||||
// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
|
||||
// CHECK9-NEXT: [[THIS:%.*]] = load ptr, ptr [[TMP1]], align 8
|
||||
// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
|
||||
// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 8
|
||||
// CHECK9-NEXT: store i32 [[TMP3]], ptr [[B]], align 4
|
||||
// CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 2
|
||||
// CHECK9-NEXT: [[TMP5:%.*]] = load i64, ptr [[TMP4]], align 8
|
||||
// CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 3
|
||||
// CHECK9-NEXT: [[TMP7:%.*]] = load i64, ptr [[TMP6]], align 8
|
||||
// CHECK9-NEXT: [[TMP8:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 4
|
||||
// CHECK9-NEXT: [[C:%.*]] = load ptr, ptr [[TMP8]], align 8
|
||||
// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 5
|
||||
// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
|
||||
// CHECK9-NEXT: [[TMP9:%.*]] = load i32, ptr [[B]], align 4
|
||||
// CHECK9-NEXT: store i32 [[TMP9]], ptr [[B_CASTED]], align 4
|
||||
// CHECK9-NEXT: [[TMP10:%.*]] = load i64, ptr [[B_CASTED]], align 8
|
||||
// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216.omp_outlined, ptr [[THIS]], i64 [[TMP10]], i64 [[TMP5]], i64 [[TMP7]], ptr [[C]])
|
||||
// CHECK9-NEXT: ret void
|
||||
//
|
||||
//
|
||||
@ -3018,7 +3051,7 @@ int bar(int n){
|
||||
// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8
|
||||
// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !nonnull [[META19]], !align [[META22]]
|
||||
// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !nonnull [[META19]], !align [[META22:![0-9]+]]
|
||||
// CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[B_ADDR]], align 4
|
||||
// CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP4]] to double
|
||||
// CHECK9-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00
|
||||
@ -3037,26 +3070,34 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181
|
||||
// CHECK9-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK9-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK9-NEXT: entry:
|
||||
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[A:%.*]] = alloca i32, align 4
|
||||
// CHECK9-NEXT: [[AA:%.*]] = alloca i16, align 2
|
||||
// CHECK9-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8
|
||||
// CHECK9-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8
|
||||
// CHECK9-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
|
||||
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META19]], !align [[META20]]
|
||||
// CHECK9-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
|
||||
// CHECK9-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4
|
||||
// CHECK9-NEXT: [[TMP2:%.*]] = load i64, ptr [[A_CASTED]], align 8
|
||||
// CHECK9-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2
|
||||
// CHECK9-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2
|
||||
// CHECK9-NEXT: [[TMP4:%.*]] = load i64, ptr [[AA_CASTED]], align 8
|
||||
// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181.omp_outlined, i64 [[TMP2]], i64 [[TMP4]], ptr [[TMP0]])
|
||||
// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
|
||||
// CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 8
|
||||
// CHECK9-NEXT: store i32 [[TMP2]], ptr [[A]], align 4
|
||||
// CHECK9-NEXT: [[TMP3:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
|
||||
// CHECK9-NEXT: [[TMP4:%.*]] = load i16, ptr [[TMP3]], align 8
|
||||
// CHECK9-NEXT: store i16 [[TMP4]], ptr [[AA]], align 2
|
||||
// CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 2
|
||||
// CHECK9-NEXT: [[B:%.*]] = load ptr, ptr [[TMP5]], align 8
|
||||
// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 3
|
||||
// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
|
||||
// CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[A]], align 4
|
||||
// CHECK9-NEXT: store i32 [[TMP6]], ptr [[A_CASTED]], align 4
|
||||
// CHECK9-NEXT: [[TMP7:%.*]] = load i64, ptr [[A_CASTED]], align 8
|
||||
// CHECK9-NEXT: [[TMP8:%.*]] = load i16, ptr [[AA]], align 2
|
||||
// CHECK9-NEXT: store i16 [[TMP8]], ptr [[AA_CASTED]], align 2
|
||||
// CHECK9-NEXT: [[TMP9:%.*]] = load i64, ptr [[AA_CASTED]], align 8
|
||||
// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181.omp_outlined, i64 [[TMP7]], i64 [[TMP9]], ptr [[B]])
|
||||
// CHECK9-NEXT: ret void
|
||||
//
|
||||
//
|
||||
@ -3090,10 +3131,15 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100
|
||||
// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK11-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK11-NEXT: entry:
|
||||
// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
|
||||
// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
|
||||
// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1:[0-9]+]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100.omp_outlined)
|
||||
// CHECK11-NEXT: ret void
|
||||
//
|
||||
@ -3109,17 +3155,24 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110
|
||||
// CHECK11-SAME: (i32 noundef [[AA:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK11-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK11-NEXT: entry:
|
||||
// CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[AA:%.*]] = alloca i16, align 2
|
||||
// CHECK11-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4
|
||||
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP0:%.*]] = load i16, ptr [[AA_ADDR]], align 2
|
||||
// CHECK11-NEXT: store i16 [[TMP0]], ptr [[AA_CASTED]], align 2
|
||||
// CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[AA_CASTED]], align 4
|
||||
// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110.omp_outlined, i32 [[TMP1]])
|
||||
// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
|
||||
// CHECK11-NEXT: [[TMP2:%.*]] = load i16, ptr [[TMP1]], align 4
|
||||
// CHECK11-NEXT: store i16 [[TMP2]], ptr [[AA]], align 2
|
||||
// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
|
||||
// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
|
||||
// CHECK11-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA]], align 2
|
||||
// CHECK11-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2
|
||||
// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[AA_CASTED]], align 4
|
||||
// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110.omp_outlined, i32 [[TMP4]])
|
||||
// CHECK11-NEXT: ret void
|
||||
//
|
||||
//
|
||||
@ -3150,23 +3203,32 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119
|
||||
// CHECK11-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK11-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK11-NEXT: entry:
|
||||
// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[A:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[AA:%.*]] = alloca i16, align 2
|
||||
// CHECK11-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
|
||||
// CHECK11-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4
|
||||
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
|
||||
// CHECK11-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4
|
||||
// CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 4
|
||||
// CHECK11-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 2
|
||||
// CHECK11-NEXT: store i16 [[TMP2]], ptr [[AA_CASTED]], align 2
|
||||
// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[AA_CASTED]], align 4
|
||||
// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119.omp_outlined, i32 [[TMP1]], i32 [[TMP3]])
|
||||
// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
|
||||
// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
|
||||
// CHECK11-NEXT: store i32 [[TMP2]], ptr [[A]], align 4
|
||||
// CHECK11-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
|
||||
// CHECK11-NEXT: [[TMP4:%.*]] = load i16, ptr [[TMP3]], align 4
|
||||
// CHECK11-NEXT: store i16 [[TMP4]], ptr [[AA]], align 2
|
||||
// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 2
|
||||
// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
|
||||
// CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[A]], align 4
|
||||
// CHECK11-NEXT: store i32 [[TMP5]], ptr [[A_CASTED]], align 4
|
||||
// CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[A_CASTED]], align 4
|
||||
// CHECK11-NEXT: [[TMP7:%.*]] = load i16, ptr [[AA]], align 2
|
||||
// CHECK11-NEXT: store i16 [[TMP7]], ptr [[AA_CASTED]], align 2
|
||||
// CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[AA_CASTED]], align 4
|
||||
// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119.omp_outlined, i32 [[TMP6]], i32 [[TMP8]])
|
||||
// CHECK11-NEXT: ret void
|
||||
//
|
||||
//
|
||||
@ -3193,41 +3255,40 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144
|
||||
// CHECK11-SAME: (i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 4 dereferenceable(12) [[D:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK11-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK11-NEXT: entry:
|
||||
// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[A:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
|
||||
// CHECK11-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4
|
||||
// CHECK11-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 4
|
||||
// CHECK11-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 4
|
||||
// CHECK11-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4
|
||||
// CHECK11-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4
|
||||
// CHECK11-NEXT: store i32 [[VLA3]], ptr [[VLA_ADDR4]], align 4
|
||||
// CHECK11-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 4
|
||||
// CHECK11-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4
|
||||
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4, !nonnull [[META20:![0-9]+]], !align [[META21:![0-9]+]]
|
||||
// CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 4, !nonnull [[META20]], !align [[META21]]
|
||||
// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4, !nonnull [[META20]], !align [[META21]]
|
||||
// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4
|
||||
// CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[VLA_ADDR4]], align 4
|
||||
// CHECK11-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 4, !nonnull [[META20]], !align [[META21]]
|
||||
// CHECK11-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 4, !nonnull [[META20]], !align [[META21]]
|
||||
// CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4
|
||||
// CHECK11-NEXT: store i32 [[TMP8]], ptr [[A_CASTED]], align 4
|
||||
// CHECK11-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_CASTED]], align 4
|
||||
// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 9, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144.omp_outlined, i32 [[TMP9]], ptr [[TMP0]], i32 [[TMP1]], ptr [[TMP2]], ptr [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], ptr [[TMP6]], ptr [[TMP7]])
|
||||
// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
|
||||
// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
|
||||
// CHECK11-NEXT: store i32 [[TMP2]], ptr [[A]], align 4
|
||||
// CHECK11-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
|
||||
// CHECK11-NEXT: [[B:%.*]] = load ptr, ptr [[TMP3]], align 4
|
||||
// CHECK11-NEXT: [[TMP4:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 2
|
||||
// CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
|
||||
// CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 3
|
||||
// CHECK11-NEXT: [[BN:%.*]] = load ptr, ptr [[TMP6]], align 4
|
||||
// CHECK11-NEXT: [[TMP7:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 4
|
||||
// CHECK11-NEXT: [[C:%.*]] = load ptr, ptr [[TMP7]], align 4
|
||||
// CHECK11-NEXT: [[TMP8:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 5
|
||||
// CHECK11-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP8]], align 4
|
||||
// CHECK11-NEXT: [[TMP10:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 6
|
||||
// CHECK11-NEXT: [[TMP11:%.*]] = load i32, ptr [[TMP10]], align 4
|
||||
// CHECK11-NEXT: [[TMP12:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 7
|
||||
// CHECK11-NEXT: [[CN:%.*]] = load ptr, ptr [[TMP12]], align 4
|
||||
// CHECK11-NEXT: [[TMP13:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 8
|
||||
// CHECK11-NEXT: [[D:%.*]] = load ptr, ptr [[TMP13]], align 4
|
||||
// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 9
|
||||
// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
|
||||
// CHECK11-NEXT: [[TMP14:%.*]] = load i32, ptr [[A]], align 4
|
||||
// CHECK11-NEXT: store i32 [[TMP14]], ptr [[A_CASTED]], align 4
|
||||
// CHECK11-NEXT: [[TMP15:%.*]] = load i32, ptr [[A_CASTED]], align 4
|
||||
// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 9, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144.omp_outlined, i32 [[TMP15]], ptr [[B]], i32 [[TMP5]], ptr [[BN]], ptr [[C]], i32 [[TMP9]], i32 [[TMP11]], ptr [[CN]], ptr [[D]])
|
||||
// CHECK11-NEXT: ret void
|
||||
//
|
||||
//
|
||||
@ -3256,7 +3317,7 @@ int bar(int n){
|
||||
// CHECK11-NEXT: store i32 [[VLA3]], ptr [[VLA_ADDR4]], align 4
|
||||
// CHECK11-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 4
|
||||
// CHECK11-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4, !nonnull [[META20]], !align [[META21]]
|
||||
// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4, !nonnull [[META20:![0-9]+]], !align [[META21:![0-9]+]]
|
||||
// CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 4, !nonnull [[META20]], !align [[META21]]
|
||||
// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4, !nonnull [[META20]], !align [[META21]]
|
||||
@ -3304,32 +3365,42 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198
|
||||
// CHECK11-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK11-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK11-NEXT: entry:
|
||||
// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[A:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[AA:%.*]] = alloca i16, align 2
|
||||
// CHECK11-NEXT: [[AAA:%.*]] = alloca i8, align 1
|
||||
// CHECK11-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
|
||||
// CHECK11-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4
|
||||
// CHECK11-NEXT: store i32 [[AAA]], ptr [[AAA_ADDR]], align 4
|
||||
// CHECK11-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4
|
||||
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4, !nonnull [[META20]], !align [[META21]]
|
||||
// CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
|
||||
// CHECK11-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4
|
||||
// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 4
|
||||
// CHECK11-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2
|
||||
// CHECK11-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2
|
||||
// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[AA_CASTED]], align 4
|
||||
// CHECK11-NEXT: [[TMP5:%.*]] = load i8, ptr [[AAA_ADDR]], align 1
|
||||
// CHECK11-NEXT: store i8 [[TMP5]], ptr [[AAA_CASTED]], align 1
|
||||
// CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[AAA_CASTED]], align 4
|
||||
// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198.omp_outlined, i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], ptr [[TMP0]])
|
||||
// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
|
||||
// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
|
||||
// CHECK11-NEXT: store i32 [[TMP2]], ptr [[A]], align 4
|
||||
// CHECK11-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
|
||||
// CHECK11-NEXT: [[TMP4:%.*]] = load i16, ptr [[TMP3]], align 4
|
||||
// CHECK11-NEXT: store i16 [[TMP4]], ptr [[AA]], align 2
|
||||
// CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 2
|
||||
// CHECK11-NEXT: [[TMP6:%.*]] = load i8, ptr [[TMP5]], align 4
|
||||
// CHECK11-NEXT: store i8 [[TMP6]], ptr [[AAA]], align 1
|
||||
// CHECK11-NEXT: [[TMP7:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 3
|
||||
// CHECK11-NEXT: [[B:%.*]] = load ptr, ptr [[TMP7]], align 4
|
||||
// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 4
|
||||
// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
|
||||
// CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 4
|
||||
// CHECK11-NEXT: store i32 [[TMP8]], ptr [[A_CASTED]], align 4
|
||||
// CHECK11-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_CASTED]], align 4
|
||||
// CHECK11-NEXT: [[TMP10:%.*]] = load i16, ptr [[AA]], align 2
|
||||
// CHECK11-NEXT: store i16 [[TMP10]], ptr [[AA_CASTED]], align 2
|
||||
// CHECK11-NEXT: [[TMP11:%.*]] = load i32, ptr [[AA_CASTED]], align 4
|
||||
// CHECK11-NEXT: [[TMP12:%.*]] = load i8, ptr [[AAA]], align 1
|
||||
// CHECK11-NEXT: store i8 [[TMP12]], ptr [[AAA_CASTED]], align 1
|
||||
// CHECK11-NEXT: [[TMP13:%.*]] = load i32, ptr [[AAA_CASTED]], align 4
|
||||
// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198.omp_outlined, i32 [[TMP9]], i32 [[TMP11]], i32 [[TMP13]], ptr [[B]])
|
||||
// CHECK11-NEXT: ret void
|
||||
//
|
||||
//
|
||||
@ -3370,29 +3441,32 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216
|
||||
// CHECK11-SAME: (ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK11-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK11-NEXT: entry:
|
||||
// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[B:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
|
||||
// CHECK11-NEXT: store i32 [[B]], ptr [[B_ADDR]], align 4
|
||||
// CHECK11-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 4
|
||||
// CHECK11-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4
|
||||
// CHECK11-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4
|
||||
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4
|
||||
// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4, !nonnull [[META20]], !align [[META22:![0-9]+]]
|
||||
// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[B_ADDR]], align 4
|
||||
// CHECK11-NEXT: store i32 [[TMP4]], ptr [[B_CASTED]], align 4
|
||||
// CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[B_CASTED]], align 4
|
||||
// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216.omp_outlined, ptr [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], ptr [[TMP3]])
|
||||
// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
|
||||
// CHECK11-NEXT: [[THIS:%.*]] = load ptr, ptr [[TMP1]], align 4
|
||||
// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
|
||||
// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
|
||||
// CHECK11-NEXT: store i32 [[TMP3]], ptr [[B]], align 4
|
||||
// CHECK11-NEXT: [[TMP4:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 2
|
||||
// CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
|
||||
// CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 3
|
||||
// CHECK11-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4
|
||||
// CHECK11-NEXT: [[TMP8:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 4
|
||||
// CHECK11-NEXT: [[C:%.*]] = load ptr, ptr [[TMP8]], align 4
|
||||
// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 5
|
||||
// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
|
||||
// CHECK11-NEXT: [[TMP9:%.*]] = load i32, ptr [[B]], align 4
|
||||
// CHECK11-NEXT: store i32 [[TMP9]], ptr [[B_CASTED]], align 4
|
||||
// CHECK11-NEXT: [[TMP10:%.*]] = load i32, ptr [[B_CASTED]], align 4
|
||||
// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216.omp_outlined, ptr [[THIS]], i32 [[TMP10]], i32 [[TMP5]], i32 [[TMP7]], ptr [[C]])
|
||||
// CHECK11-NEXT: ret void
|
||||
//
|
||||
//
|
||||
@ -3416,7 +3490,7 @@ int bar(int n){
|
||||
// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4
|
||||
// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4, !nonnull [[META20]], !align [[META22]]
|
||||
// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4, !nonnull [[META20]], !align [[META22:![0-9]+]]
|
||||
// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[B_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP4]] to double
|
||||
// CHECK11-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00
|
||||
@ -3435,26 +3509,34 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181
|
||||
// CHECK11-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK11-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK11-NEXT: entry:
|
||||
// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[A:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[AA:%.*]] = alloca i16, align 2
|
||||
// CHECK11-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
|
||||
// CHECK11-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4
|
||||
// CHECK11-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4
|
||||
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4, !nonnull [[META20]], !align [[META21]]
|
||||
// CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
|
||||
// CHECK11-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4
|
||||
// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 4
|
||||
// CHECK11-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2
|
||||
// CHECK11-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2
|
||||
// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[AA_CASTED]], align 4
|
||||
// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181.omp_outlined, i32 [[TMP2]], i32 [[TMP4]], ptr [[TMP0]])
|
||||
// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
|
||||
// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
|
||||
// CHECK11-NEXT: store i32 [[TMP2]], ptr [[A]], align 4
|
||||
// CHECK11-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
|
||||
// CHECK11-NEXT: [[TMP4:%.*]] = load i16, ptr [[TMP3]], align 4
|
||||
// CHECK11-NEXT: store i16 [[TMP4]], ptr [[AA]], align 2
|
||||
// CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 2
|
||||
// CHECK11-NEXT: [[B:%.*]] = load ptr, ptr [[TMP5]], align 4
|
||||
// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 3
|
||||
// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
|
||||
// CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[A]], align 4
|
||||
// CHECK11-NEXT: store i32 [[TMP6]], ptr [[A_CASTED]], align 4
|
||||
// CHECK11-NEXT: [[TMP7:%.*]] = load i32, ptr [[A_CASTED]], align 4
|
||||
// CHECK11-NEXT: [[TMP8:%.*]] = load i16, ptr [[AA]], align 2
|
||||
// CHECK11-NEXT: store i16 [[TMP8]], ptr [[AA_CASTED]], align 2
|
||||
// CHECK11-NEXT: [[TMP9:%.*]] = load i32, ptr [[AA_CASTED]], align 4
|
||||
// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181.omp_outlined, i32 [[TMP7]], i32 [[TMP9]], ptr [[B]])
|
||||
// CHECK11-NEXT: ret void
|
||||
//
|
||||
//
|
||||
|
||||
@ -3767,10 +3767,15 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103
|
||||
// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK9-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK9-NEXT: entry:
|
||||
// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
|
||||
// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
|
||||
// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2:[0-9]+]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.omp_outlined)
|
||||
// CHECK9-NEXT: ret void
|
||||
//
|
||||
@ -3853,29 +3858,40 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l128
|
||||
// CHECK9-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK9-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK9-NEXT: entry:
|
||||
// CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[AA:%.*]] = alloca i16, align 2
|
||||
// CHECK9-NEXT: [[LIN:%.*]] = alloca i32, align 4
|
||||
// CHECK9-NEXT: [[A:%.*]] = alloca i32, align 4
|
||||
// CHECK9-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8
|
||||
// CHECK9-NEXT: store i64 [[LIN]], ptr [[LIN_ADDR]], align 8
|
||||
// CHECK9-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8
|
||||
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP0:%.*]] = load i16, ptr [[AA_ADDR]], align 2
|
||||
// CHECK9-NEXT: store i16 [[TMP0]], ptr [[AA_CASTED]], align 2
|
||||
// CHECK9-NEXT: [[TMP1:%.*]] = load i64, ptr [[AA_CASTED]], align 8
|
||||
// CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[LIN_ADDR]], align 4
|
||||
// CHECK9-NEXT: store i32 [[TMP2]], ptr [[LIN_CASTED]], align 4
|
||||
// CHECK9-NEXT: [[TMP3:%.*]] = load i64, ptr [[LIN_CASTED]], align 8
|
||||
// CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[A_ADDR]], align 4
|
||||
// CHECK9-NEXT: store i32 [[TMP4]], ptr [[A_CASTED]], align 4
|
||||
// CHECK9-NEXT: [[TMP5:%.*]] = load i64, ptr [[A_CASTED]], align 8
|
||||
// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l128.omp_outlined, i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]])
|
||||
// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
|
||||
// CHECK9-NEXT: [[TMP2:%.*]] = load i16, ptr [[TMP1]], align 8
|
||||
// CHECK9-NEXT: store i16 [[TMP2]], ptr [[AA]], align 2
|
||||
// CHECK9-NEXT: [[TMP3:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
|
||||
// CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 8
|
||||
// CHECK9-NEXT: store i32 [[TMP4]], ptr [[LIN]], align 4
|
||||
// CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 2
|
||||
// CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 8
|
||||
// CHECK9-NEXT: store i32 [[TMP6]], ptr [[A]], align 4
|
||||
// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 3
|
||||
// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
|
||||
// CHECK9-NEXT: [[TMP7:%.*]] = load i16, ptr [[AA]], align 2
|
||||
// CHECK9-NEXT: store i16 [[TMP7]], ptr [[AA_CASTED]], align 2
|
||||
// CHECK9-NEXT: [[TMP8:%.*]] = load i64, ptr [[AA_CASTED]], align 8
|
||||
// CHECK9-NEXT: [[TMP9:%.*]] = load i32, ptr [[LIN]], align 4
|
||||
// CHECK9-NEXT: store i32 [[TMP9]], ptr [[LIN_CASTED]], align 4
|
||||
// CHECK9-NEXT: [[TMP10:%.*]] = load i64, ptr [[LIN_CASTED]], align 8
|
||||
// CHECK9-NEXT: [[TMP11:%.*]] = load i32, ptr [[A]], align 4
|
||||
// CHECK9-NEXT: store i32 [[TMP11]], ptr [[A_CASTED]], align 4
|
||||
// CHECK9-NEXT: [[TMP12:%.*]] = load i64, ptr [[A_CASTED]], align 8
|
||||
// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l128.omp_outlined, i64 [[TMP8]], i64 [[TMP10]], i64 [[TMP12]])
|
||||
// CHECK9-NEXT: ret void
|
||||
//
|
||||
//
|
||||
@ -3995,23 +4011,32 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l136
|
||||
// CHECK9-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK9-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK9-NEXT: entry:
|
||||
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[A:%.*]] = alloca i32, align 4
|
||||
// CHECK9-NEXT: [[AA:%.*]] = alloca i16, align 2
|
||||
// CHECK9-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8
|
||||
// CHECK9-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8
|
||||
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
|
||||
// CHECK9-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4
|
||||
// CHECK9-NEXT: [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 8
|
||||
// CHECK9-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 2
|
||||
// CHECK9-NEXT: store i16 [[TMP2]], ptr [[AA_CASTED]], align 2
|
||||
// CHECK9-NEXT: [[TMP3:%.*]] = load i64, ptr [[AA_CASTED]], align 8
|
||||
// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l136.omp_outlined, i64 [[TMP1]], i64 [[TMP3]])
|
||||
// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
|
||||
// CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 8
|
||||
// CHECK9-NEXT: store i32 [[TMP2]], ptr [[A]], align 4
|
||||
// CHECK9-NEXT: [[TMP3:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
|
||||
// CHECK9-NEXT: [[TMP4:%.*]] = load i16, ptr [[TMP3]], align 8
|
||||
// CHECK9-NEXT: store i16 [[TMP4]], ptr [[AA]], align 2
|
||||
// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 2
|
||||
// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
|
||||
// CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[A]], align 4
|
||||
// CHECK9-NEXT: store i32 [[TMP5]], ptr [[A_CASTED]], align 4
|
||||
// CHECK9-NEXT: [[TMP6:%.*]] = load i64, ptr [[A_CASTED]], align 8
|
||||
// CHECK9-NEXT: [[TMP7:%.*]] = load i16, ptr [[AA]], align 2
|
||||
// CHECK9-NEXT: store i16 [[TMP7]], ptr [[AA_CASTED]], align 2
|
||||
// CHECK9-NEXT: [[TMP8:%.*]] = load i64, ptr [[AA_CASTED]], align 8
|
||||
// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l136.omp_outlined, i64 [[TMP6]], i64 [[TMP8]])
|
||||
// CHECK9-NEXT: ret void
|
||||
//
|
||||
//
|
||||
@ -4089,47 +4114,48 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160
|
||||
// CHECK9-SAME: (i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK9-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK9-NEXT: entry:
|
||||
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[A:%.*]] = alloca i32, align 4
|
||||
// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
|
||||
// CHECK9-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8
|
||||
// CHECK9-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
|
||||
// CHECK9-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8
|
||||
// CHECK9-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 8
|
||||
// CHECK9-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8
|
||||
// CHECK9-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8
|
||||
// CHECK9-NEXT: store i64 [[VLA3]], ptr [[VLA_ADDR4]], align 8
|
||||
// CHECK9-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 8
|
||||
// CHECK9-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8
|
||||
// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8
|
||||
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META19:![0-9]+]], !align [[META20:![0-9]+]]
|
||||
// CHECK9-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 8, !nonnull [[META19]], !align [[META20]]
|
||||
// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !nonnull [[META19]], !align [[META21:![0-9]+]]
|
||||
// CHECK9-NEXT: [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8
|
||||
// CHECK9-NEXT: [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR4]], align 8
|
||||
// CHECK9-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 8, !nonnull [[META19]], !align [[META21]]
|
||||
// CHECK9-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 8, !nonnull [[META19]], !align [[META21]]
|
||||
// CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4
|
||||
// CHECK9-NEXT: store i32 [[TMP8]], ptr [[A_CASTED]], align 4
|
||||
// CHECK9-NEXT: [[TMP9:%.*]] = load i64, ptr [[A_CASTED]], align 8
|
||||
// CHECK9-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
|
||||
// CHECK9-NEXT: store i32 [[TMP10]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 4
|
||||
// CHECK9-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED]], align 8
|
||||
// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 10, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160.omp_outlined, i64 [[TMP9]], ptr [[TMP0]], i64 [[TMP1]], ptr [[TMP2]], ptr [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], ptr [[TMP6]], ptr [[TMP7]], i64 [[TMP11]])
|
||||
// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
|
||||
// CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 8
|
||||
// CHECK9-NEXT: store i32 [[TMP2]], ptr [[A]], align 4
|
||||
// CHECK9-NEXT: [[TMP3:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
|
||||
// CHECK9-NEXT: [[B:%.*]] = load ptr, ptr [[TMP3]], align 8
|
||||
// CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 2
|
||||
// CHECK9-NEXT: [[TMP5:%.*]] = load i64, ptr [[TMP4]], align 8
|
||||
// CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 3
|
||||
// CHECK9-NEXT: [[BN:%.*]] = load ptr, ptr [[TMP6]], align 8
|
||||
// CHECK9-NEXT: [[TMP7:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 4
|
||||
// CHECK9-NEXT: [[C:%.*]] = load ptr, ptr [[TMP7]], align 8
|
||||
// CHECK9-NEXT: [[TMP8:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 5
|
||||
// CHECK9-NEXT: [[TMP9:%.*]] = load i64, ptr [[TMP8]], align 8
|
||||
// CHECK9-NEXT: [[TMP10:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 6
|
||||
// CHECK9-NEXT: [[TMP11:%.*]] = load i64, ptr [[TMP10]], align 8
|
||||
// CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 7
|
||||
// CHECK9-NEXT: [[CN:%.*]] = load ptr, ptr [[TMP12]], align 8
|
||||
// CHECK9-NEXT: [[TMP13:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 8
|
||||
// CHECK9-NEXT: [[D:%.*]] = load ptr, ptr [[TMP13]], align 8
|
||||
// CHECK9-NEXT: [[TMP14:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 9
|
||||
// CHECK9-NEXT: [[TMP15:%.*]] = load i32, ptr [[TMP14]], align 8
|
||||
// CHECK9-NEXT: store i32 [[TMP15]], ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 10
|
||||
// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
|
||||
// CHECK9-NEXT: [[TMP16:%.*]] = load i32, ptr [[A]], align 4
|
||||
// CHECK9-NEXT: store i32 [[TMP16]], ptr [[A_CASTED]], align 4
|
||||
// CHECK9-NEXT: [[TMP17:%.*]] = load i64, ptr [[A_CASTED]], align 8
|
||||
// CHECK9-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
// CHECK9-NEXT: store i32 [[TMP18]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 4
|
||||
// CHECK9-NEXT: [[TMP19:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED]], align 8
|
||||
// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 10, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160.omp_outlined, i64 [[TMP17]], ptr [[B]], i64 [[TMP5]], ptr [[BN]], ptr [[C]], i64 [[TMP9]], i64 [[TMP11]], ptr [[CN]], ptr [[D]], i64 [[TMP19]])
|
||||
// CHECK9-NEXT: ret void
|
||||
//
|
||||
//
|
||||
@ -4167,10 +4193,10 @@ int bar(int n){
|
||||
// CHECK9-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 8
|
||||
// CHECK9-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8
|
||||
// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META19]], !align [[META20]]
|
||||
// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META19:![0-9]+]], !align [[META20:![0-9]+]]
|
||||
// CHECK9-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 8, !nonnull [[META19]], !align [[META20]]
|
||||
// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !nonnull [[META19]], !align [[META21]]
|
||||
// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !nonnull [[META19]], !align [[META21:![0-9]+]]
|
||||
// CHECK9-NEXT: [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8
|
||||
// CHECK9-NEXT: [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR4]], align 8
|
||||
// CHECK9-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 8, !nonnull [[META19]], !align [[META21]]
|
||||
@ -4277,32 +4303,42 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l214
|
||||
// CHECK9-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK9-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK9-NEXT: entry:
|
||||
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[A:%.*]] = alloca i32, align 4
|
||||
// CHECK9-NEXT: [[AA:%.*]] = alloca i16, align 2
|
||||
// CHECK9-NEXT: [[AAA:%.*]] = alloca i8, align 1
|
||||
// CHECK9-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8
|
||||
// CHECK9-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8
|
||||
// CHECK9-NEXT: store i64 [[AAA]], ptr [[AAA_ADDR]], align 8
|
||||
// CHECK9-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
|
||||
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META19]], !align [[META20]]
|
||||
// CHECK9-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
|
||||
// CHECK9-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4
|
||||
// CHECK9-NEXT: [[TMP2:%.*]] = load i64, ptr [[A_CASTED]], align 8
|
||||
// CHECK9-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2
|
||||
// CHECK9-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2
|
||||
// CHECK9-NEXT: [[TMP4:%.*]] = load i64, ptr [[AA_CASTED]], align 8
|
||||
// CHECK9-NEXT: [[TMP5:%.*]] = load i8, ptr [[AAA_ADDR]], align 1
|
||||
// CHECK9-NEXT: store i8 [[TMP5]], ptr [[AAA_CASTED]], align 1
|
||||
// CHECK9-NEXT: [[TMP6:%.*]] = load i64, ptr [[AAA_CASTED]], align 8
|
||||
// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l214.omp_outlined, i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], ptr [[TMP0]])
|
||||
// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
|
||||
// CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 8
|
||||
// CHECK9-NEXT: store i32 [[TMP2]], ptr [[A]], align 4
|
||||
// CHECK9-NEXT: [[TMP3:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
|
||||
// CHECK9-NEXT: [[TMP4:%.*]] = load i16, ptr [[TMP3]], align 8
|
||||
// CHECK9-NEXT: store i16 [[TMP4]], ptr [[AA]], align 2
|
||||
// CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 2
|
||||
// CHECK9-NEXT: [[TMP6:%.*]] = load i8, ptr [[TMP5]], align 8
|
||||
// CHECK9-NEXT: store i8 [[TMP6]], ptr [[AAA]], align 1
|
||||
// CHECK9-NEXT: [[TMP7:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 3
|
||||
// CHECK9-NEXT: [[B:%.*]] = load ptr, ptr [[TMP7]], align 8
|
||||
// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 4
|
||||
// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
|
||||
// CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 4
|
||||
// CHECK9-NEXT: store i32 [[TMP8]], ptr [[A_CASTED]], align 4
|
||||
// CHECK9-NEXT: [[TMP9:%.*]] = load i64, ptr [[A_CASTED]], align 8
|
||||
// CHECK9-NEXT: [[TMP10:%.*]] = load i16, ptr [[AA]], align 2
|
||||
// CHECK9-NEXT: store i16 [[TMP10]], ptr [[AA_CASTED]], align 2
|
||||
// CHECK9-NEXT: [[TMP11:%.*]] = load i64, ptr [[AA_CASTED]], align 8
|
||||
// CHECK9-NEXT: [[TMP12:%.*]] = load i8, ptr [[AAA]], align 1
|
||||
// CHECK9-NEXT: store i8 [[TMP12]], ptr [[AAA_CASTED]], align 1
|
||||
// CHECK9-NEXT: [[TMP13:%.*]] = load i64, ptr [[AAA_CASTED]], align 8
|
||||
// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l214.omp_outlined, i64 [[TMP9]], i64 [[TMP11]], i64 [[TMP13]], ptr [[B]])
|
||||
// CHECK9-NEXT: ret void
|
||||
//
|
||||
//
|
||||
@ -4328,29 +4364,32 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l232
|
||||
// CHECK9-SAME: (ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK9-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK9-NEXT: entry:
|
||||
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[B:%.*]] = alloca i32, align 4
|
||||
// CHECK9-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
|
||||
// CHECK9-NEXT: store i64 [[B]], ptr [[B_ADDR]], align 8
|
||||
// CHECK9-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8
|
||||
// CHECK9-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8
|
||||
// CHECK9-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8
|
||||
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8
|
||||
// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !nonnull [[META19]], !align [[META22:![0-9]+]]
|
||||
// CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[B_ADDR]], align 4
|
||||
// CHECK9-NEXT: store i32 [[TMP4]], ptr [[B_CASTED]], align 4
|
||||
// CHECK9-NEXT: [[TMP5:%.*]] = load i64, ptr [[B_CASTED]], align 8
|
||||
// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l232.omp_outlined, ptr [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], ptr [[TMP3]])
|
||||
// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
|
||||
// CHECK9-NEXT: [[THIS:%.*]] = load ptr, ptr [[TMP1]], align 8
|
||||
// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
|
||||
// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 8
|
||||
// CHECK9-NEXT: store i32 [[TMP3]], ptr [[B]], align 4
|
||||
// CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 2
|
||||
// CHECK9-NEXT: [[TMP5:%.*]] = load i64, ptr [[TMP4]], align 8
|
||||
// CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 3
|
||||
// CHECK9-NEXT: [[TMP7:%.*]] = load i64, ptr [[TMP6]], align 8
|
||||
// CHECK9-NEXT: [[TMP8:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 4
|
||||
// CHECK9-NEXT: [[C:%.*]] = load ptr, ptr [[TMP8]], align 8
|
||||
// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 5
|
||||
// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
|
||||
// CHECK9-NEXT: [[TMP9:%.*]] = load i32, ptr [[B]], align 4
|
||||
// CHECK9-NEXT: store i32 [[TMP9]], ptr [[B_CASTED]], align 4
|
||||
// CHECK9-NEXT: [[TMP10:%.*]] = load i64, ptr [[B_CASTED]], align 8
|
||||
// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l232.omp_outlined, ptr [[THIS]], i64 [[TMP10]], i64 [[TMP5]], i64 [[TMP7]], ptr [[C]])
|
||||
// CHECK9-NEXT: ret void
|
||||
//
|
||||
//
|
||||
@ -4381,7 +4420,7 @@ int bar(int n){
|
||||
// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8
|
||||
// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !nonnull [[META19]], !align [[META22]]
|
||||
// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !nonnull [[META19]], !align [[META22:![0-9]+]]
|
||||
// CHECK9-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8
|
||||
// CHECK9-NEXT: store i64 3, ptr [[DOTOMP_UB]], align 8
|
||||
// CHECK9-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8
|
||||
@ -4443,26 +4482,34 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l197
|
||||
// CHECK9-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK9-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK9-NEXT: entry:
|
||||
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[A:%.*]] = alloca i32, align 4
|
||||
// CHECK9-NEXT: [[AA:%.*]] = alloca i16, align 2
|
||||
// CHECK9-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8
|
||||
// CHECK9-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8
|
||||
// CHECK9-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
|
||||
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META19]], !align [[META20]]
|
||||
// CHECK9-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
|
||||
// CHECK9-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4
|
||||
// CHECK9-NEXT: [[TMP2:%.*]] = load i64, ptr [[A_CASTED]], align 8
|
||||
// CHECK9-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2
|
||||
// CHECK9-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2
|
||||
// CHECK9-NEXT: [[TMP4:%.*]] = load i64, ptr [[AA_CASTED]], align 8
|
||||
// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l197.omp_outlined, i64 [[TMP2]], i64 [[TMP4]], ptr [[TMP0]])
|
||||
// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
|
||||
// CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 8
|
||||
// CHECK9-NEXT: store i32 [[TMP2]], ptr [[A]], align 4
|
||||
// CHECK9-NEXT: [[TMP3:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
|
||||
// CHECK9-NEXT: [[TMP4:%.*]] = load i16, ptr [[TMP3]], align 8
|
||||
// CHECK9-NEXT: store i16 [[TMP4]], ptr [[AA]], align 2
|
||||
// CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 2
|
||||
// CHECK9-NEXT: [[B:%.*]] = load ptr, ptr [[TMP5]], align 8
|
||||
// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 3
|
||||
// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
|
||||
// CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[A]], align 4
|
||||
// CHECK9-NEXT: store i32 [[TMP6]], ptr [[A_CASTED]], align 4
|
||||
// CHECK9-NEXT: [[TMP7:%.*]] = load i64, ptr [[A_CASTED]], align 8
|
||||
// CHECK9-NEXT: [[TMP8:%.*]] = load i16, ptr [[AA]], align 2
|
||||
// CHECK9-NEXT: store i16 [[TMP8]], ptr [[AA_CASTED]], align 2
|
||||
// CHECK9-NEXT: [[TMP9:%.*]] = load i64, ptr [[AA_CASTED]], align 8
|
||||
// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l197.omp_outlined, i64 [[TMP7]], i64 [[TMP9]], ptr [[B]])
|
||||
// CHECK9-NEXT: ret void
|
||||
//
|
||||
//
|
||||
@ -4546,10 +4593,15 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103
|
||||
// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK11-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK11-NEXT: entry:
|
||||
// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
|
||||
// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
|
||||
// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2:[0-9]+]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.omp_outlined)
|
||||
// CHECK11-NEXT: ret void
|
||||
//
|
||||
@ -4632,29 +4684,40 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l128
|
||||
// CHECK11-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK11-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK11-NEXT: entry:
|
||||
// CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[AA:%.*]] = alloca i16, align 2
|
||||
// CHECK11-NEXT: [[LIN:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[A:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4
|
||||
// CHECK11-NEXT: store i32 [[LIN]], ptr [[LIN_ADDR]], align 4
|
||||
// CHECK11-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
|
||||
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP0:%.*]] = load i16, ptr [[AA_ADDR]], align 2
|
||||
// CHECK11-NEXT: store i16 [[TMP0]], ptr [[AA_CASTED]], align 2
|
||||
// CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[AA_CASTED]], align 4
|
||||
// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[LIN_ADDR]], align 4
|
||||
// CHECK11-NEXT: store i32 [[TMP2]], ptr [[LIN_CASTED]], align 4
|
||||
// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[LIN_CASTED]], align 4
|
||||
// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[A_ADDR]], align 4
|
||||
// CHECK11-NEXT: store i32 [[TMP4]], ptr [[A_CASTED]], align 4
|
||||
// CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[A_CASTED]], align 4
|
||||
// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l128.omp_outlined, i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]])
|
||||
// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
|
||||
// CHECK11-NEXT: [[TMP2:%.*]] = load i16, ptr [[TMP1]], align 4
|
||||
// CHECK11-NEXT: store i16 [[TMP2]], ptr [[AA]], align 2
|
||||
// CHECK11-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
|
||||
// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4
|
||||
// CHECK11-NEXT: store i32 [[TMP4]], ptr [[LIN]], align 4
|
||||
// CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 2
|
||||
// CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4
|
||||
// CHECK11-NEXT: store i32 [[TMP6]], ptr [[A]], align 4
|
||||
// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 3
|
||||
// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
|
||||
// CHECK11-NEXT: [[TMP7:%.*]] = load i16, ptr [[AA]], align 2
|
||||
// CHECK11-NEXT: store i16 [[TMP7]], ptr [[AA_CASTED]], align 2
|
||||
// CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[AA_CASTED]], align 4
|
||||
// CHECK11-NEXT: [[TMP9:%.*]] = load i32, ptr [[LIN]], align 4
|
||||
// CHECK11-NEXT: store i32 [[TMP9]], ptr [[LIN_CASTED]], align 4
|
||||
// CHECK11-NEXT: [[TMP10:%.*]] = load i32, ptr [[LIN_CASTED]], align 4
|
||||
// CHECK11-NEXT: [[TMP11:%.*]] = load i32, ptr [[A]], align 4
|
||||
// CHECK11-NEXT: store i32 [[TMP11]], ptr [[A_CASTED]], align 4
|
||||
// CHECK11-NEXT: [[TMP12:%.*]] = load i32, ptr [[A_CASTED]], align 4
|
||||
// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l128.omp_outlined, i32 [[TMP8]], i32 [[TMP10]], i32 [[TMP12]])
|
||||
// CHECK11-NEXT: ret void
|
||||
//
|
||||
//
|
||||
@ -4774,23 +4837,32 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l136
|
||||
// CHECK11-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK11-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK11-NEXT: entry:
|
||||
// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[A:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[AA:%.*]] = alloca i16, align 2
|
||||
// CHECK11-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
|
||||
// CHECK11-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4
|
||||
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
|
||||
// CHECK11-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4
|
||||
// CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 4
|
||||
// CHECK11-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 2
|
||||
// CHECK11-NEXT: store i16 [[TMP2]], ptr [[AA_CASTED]], align 2
|
||||
// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[AA_CASTED]], align 4
|
||||
// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l136.omp_outlined, i32 [[TMP1]], i32 [[TMP3]])
|
||||
// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
|
||||
// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
|
||||
// CHECK11-NEXT: store i32 [[TMP2]], ptr [[A]], align 4
|
||||
// CHECK11-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
|
||||
// CHECK11-NEXT: [[TMP4:%.*]] = load i16, ptr [[TMP3]], align 4
|
||||
// CHECK11-NEXT: store i16 [[TMP4]], ptr [[AA]], align 2
|
||||
// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 2
|
||||
// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
|
||||
// CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[A]], align 4
|
||||
// CHECK11-NEXT: store i32 [[TMP5]], ptr [[A_CASTED]], align 4
|
||||
// CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[A_CASTED]], align 4
|
||||
// CHECK11-NEXT: [[TMP7:%.*]] = load i16, ptr [[AA]], align 2
|
||||
// CHECK11-NEXT: store i16 [[TMP7]], ptr [[AA_CASTED]], align 2
|
||||
// CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[AA_CASTED]], align 4
|
||||
// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l136.omp_outlined, i32 [[TMP6]], i32 [[TMP8]])
|
||||
// CHECK11-NEXT: ret void
|
||||
//
|
||||
//
|
||||
@ -4868,47 +4940,48 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160
|
||||
// CHECK11-SAME: (i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK11-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK11-NEXT: entry:
|
||||
// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[A:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
|
||||
// CHECK11-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4
|
||||
// CHECK11-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 4
|
||||
// CHECK11-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 4
|
||||
// CHECK11-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4
|
||||
// CHECK11-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4
|
||||
// CHECK11-NEXT: store i32 [[VLA3]], ptr [[VLA_ADDR4]], align 4
|
||||
// CHECK11-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 4
|
||||
// CHECK11-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4
|
||||
// CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
|
||||
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4, !nonnull [[META20:![0-9]+]], !align [[META21:![0-9]+]]
|
||||
// CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 4, !nonnull [[META20]], !align [[META21]]
|
||||
// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4, !nonnull [[META20]], !align [[META21]]
|
||||
// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4
|
||||
// CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[VLA_ADDR4]], align 4
|
||||
// CHECK11-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 4, !nonnull [[META20]], !align [[META21]]
|
||||
// CHECK11-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 4, !nonnull [[META20]], !align [[META21]]
|
||||
// CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4
|
||||
// CHECK11-NEXT: store i32 [[TMP8]], ptr [[A_CASTED]], align 4
|
||||
// CHECK11-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_CASTED]], align 4
|
||||
// CHECK11-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
|
||||
// CHECK11-NEXT: store i32 [[TMP10]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 4
|
||||
// CHECK11-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__CASTED]], align 4
|
||||
// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 10, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160.omp_outlined, i32 [[TMP9]], ptr [[TMP0]], i32 [[TMP1]], ptr [[TMP2]], ptr [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], ptr [[TMP6]], ptr [[TMP7]], i32 [[TMP11]])
|
||||
// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
|
||||
// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
|
||||
// CHECK11-NEXT: store i32 [[TMP2]], ptr [[A]], align 4
|
||||
// CHECK11-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
|
||||
// CHECK11-NEXT: [[B:%.*]] = load ptr, ptr [[TMP3]], align 4
|
||||
// CHECK11-NEXT: [[TMP4:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 2
|
||||
// CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
|
||||
// CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 3
|
||||
// CHECK11-NEXT: [[BN:%.*]] = load ptr, ptr [[TMP6]], align 4
|
||||
// CHECK11-NEXT: [[TMP7:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 4
|
||||
// CHECK11-NEXT: [[C:%.*]] = load ptr, ptr [[TMP7]], align 4
|
||||
// CHECK11-NEXT: [[TMP8:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 5
|
||||
// CHECK11-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP8]], align 4
|
||||
// CHECK11-NEXT: [[TMP10:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 6
|
||||
// CHECK11-NEXT: [[TMP11:%.*]] = load i32, ptr [[TMP10]], align 4
|
||||
// CHECK11-NEXT: [[TMP12:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 7
|
||||
// CHECK11-NEXT: [[CN:%.*]] = load ptr, ptr [[TMP12]], align 4
|
||||
// CHECK11-NEXT: [[TMP13:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 8
|
||||
// CHECK11-NEXT: [[D:%.*]] = load ptr, ptr [[TMP13]], align 4
|
||||
// CHECK11-NEXT: [[TMP14:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 9
|
||||
// CHECK11-NEXT: [[TMP15:%.*]] = load i32, ptr [[TMP14]], align 4
|
||||
// CHECK11-NEXT: store i32 [[TMP15]], ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 10
|
||||
// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
|
||||
// CHECK11-NEXT: [[TMP16:%.*]] = load i32, ptr [[A]], align 4
|
||||
// CHECK11-NEXT: store i32 [[TMP16]], ptr [[A_CASTED]], align 4
|
||||
// CHECK11-NEXT: [[TMP17:%.*]] = load i32, ptr [[A_CASTED]], align 4
|
||||
// CHECK11-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
// CHECK11-NEXT: store i32 [[TMP18]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 4
|
||||
// CHECK11-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__CASTED]], align 4
|
||||
// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 10, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160.omp_outlined, i32 [[TMP17]], ptr [[B]], i32 [[TMP5]], ptr [[BN]], ptr [[C]], i32 [[TMP9]], i32 [[TMP11]], ptr [[CN]], ptr [[D]], i32 [[TMP19]])
|
||||
// CHECK11-NEXT: ret void
|
||||
//
|
||||
//
|
||||
@ -4946,7 +5019,7 @@ int bar(int n){
|
||||
// CHECK11-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 4
|
||||
// CHECK11-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4
|
||||
// CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4, !nonnull [[META20]], !align [[META21]]
|
||||
// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4, !nonnull [[META20:![0-9]+]], !align [[META21:![0-9]+]]
|
||||
// CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 4, !nonnull [[META20]], !align [[META21]]
|
||||
// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4, !nonnull [[META20]], !align [[META21]]
|
||||
@ -5056,32 +5129,42 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l214
|
||||
// CHECK11-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK11-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK11-NEXT: entry:
|
||||
// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[A:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[AA:%.*]] = alloca i16, align 2
|
||||
// CHECK11-NEXT: [[AAA:%.*]] = alloca i8, align 1
|
||||
// CHECK11-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
|
||||
// CHECK11-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4
|
||||
// CHECK11-NEXT: store i32 [[AAA]], ptr [[AAA_ADDR]], align 4
|
||||
// CHECK11-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4
|
||||
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4, !nonnull [[META20]], !align [[META21]]
|
||||
// CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
|
||||
// CHECK11-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4
|
||||
// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 4
|
||||
// CHECK11-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2
|
||||
// CHECK11-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2
|
||||
// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[AA_CASTED]], align 4
|
||||
// CHECK11-NEXT: [[TMP5:%.*]] = load i8, ptr [[AAA_ADDR]], align 1
|
||||
// CHECK11-NEXT: store i8 [[TMP5]], ptr [[AAA_CASTED]], align 1
|
||||
// CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[AAA_CASTED]], align 4
|
||||
// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l214.omp_outlined, i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], ptr [[TMP0]])
|
||||
// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
|
||||
// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
|
||||
// CHECK11-NEXT: store i32 [[TMP2]], ptr [[A]], align 4
|
||||
// CHECK11-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
|
||||
// CHECK11-NEXT: [[TMP4:%.*]] = load i16, ptr [[TMP3]], align 4
|
||||
// CHECK11-NEXT: store i16 [[TMP4]], ptr [[AA]], align 2
|
||||
// CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 2
|
||||
// CHECK11-NEXT: [[TMP6:%.*]] = load i8, ptr [[TMP5]], align 4
|
||||
// CHECK11-NEXT: store i8 [[TMP6]], ptr [[AAA]], align 1
|
||||
// CHECK11-NEXT: [[TMP7:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 3
|
||||
// CHECK11-NEXT: [[B:%.*]] = load ptr, ptr [[TMP7]], align 4
|
||||
// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 4
|
||||
// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
|
||||
// CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 4
|
||||
// CHECK11-NEXT: store i32 [[TMP8]], ptr [[A_CASTED]], align 4
|
||||
// CHECK11-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_CASTED]], align 4
|
||||
// CHECK11-NEXT: [[TMP10:%.*]] = load i16, ptr [[AA]], align 2
|
||||
// CHECK11-NEXT: store i16 [[TMP10]], ptr [[AA_CASTED]], align 2
|
||||
// CHECK11-NEXT: [[TMP11:%.*]] = load i32, ptr [[AA_CASTED]], align 4
|
||||
// CHECK11-NEXT: [[TMP12:%.*]] = load i8, ptr [[AAA]], align 1
|
||||
// CHECK11-NEXT: store i8 [[TMP12]], ptr [[AAA_CASTED]], align 1
|
||||
// CHECK11-NEXT: [[TMP13:%.*]] = load i32, ptr [[AAA_CASTED]], align 4
|
||||
// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l214.omp_outlined, i32 [[TMP9]], i32 [[TMP11]], i32 [[TMP13]], ptr [[B]])
|
||||
// CHECK11-NEXT: ret void
|
||||
//
|
||||
//
|
||||
@ -5107,29 +5190,32 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l232
|
||||
// CHECK11-SAME: (ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK11-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK11-NEXT: entry:
|
||||
// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[B:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
|
||||
// CHECK11-NEXT: store i32 [[B]], ptr [[B_ADDR]], align 4
|
||||
// CHECK11-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 4
|
||||
// CHECK11-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4
|
||||
// CHECK11-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4
|
||||
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4
|
||||
// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4, !nonnull [[META20]], !align [[META22:![0-9]+]]
|
||||
// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[B_ADDR]], align 4
|
||||
// CHECK11-NEXT: store i32 [[TMP4]], ptr [[B_CASTED]], align 4
|
||||
// CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[B_CASTED]], align 4
|
||||
// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l232.omp_outlined, ptr [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], ptr [[TMP3]])
|
||||
// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
|
||||
// CHECK11-NEXT: [[THIS:%.*]] = load ptr, ptr [[TMP1]], align 4
|
||||
// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
|
||||
// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
|
||||
// CHECK11-NEXT: store i32 [[TMP3]], ptr [[B]], align 4
|
||||
// CHECK11-NEXT: [[TMP4:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 2
|
||||
// CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
|
||||
// CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 3
|
||||
// CHECK11-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4
|
||||
// CHECK11-NEXT: [[TMP8:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 4
|
||||
// CHECK11-NEXT: [[C:%.*]] = load ptr, ptr [[TMP8]], align 4
|
||||
// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 5
|
||||
// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
|
||||
// CHECK11-NEXT: [[TMP9:%.*]] = load i32, ptr [[B]], align 4
|
||||
// CHECK11-NEXT: store i32 [[TMP9]], ptr [[B_CASTED]], align 4
|
||||
// CHECK11-NEXT: [[TMP10:%.*]] = load i32, ptr [[B_CASTED]], align 4
|
||||
// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l232.omp_outlined, ptr [[THIS]], i32 [[TMP10]], i32 [[TMP5]], i32 [[TMP7]], ptr [[C]])
|
||||
// CHECK11-NEXT: ret void
|
||||
//
|
||||
//
|
||||
@ -5160,7 +5246,7 @@ int bar(int n){
|
||||
// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4
|
||||
// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4, !nonnull [[META20]], !align [[META22]]
|
||||
// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4, !nonnull [[META20]], !align [[META22:![0-9]+]]
|
||||
// CHECK11-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8
|
||||
// CHECK11-NEXT: store i64 3, ptr [[DOTOMP_UB]], align 8
|
||||
// CHECK11-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8
|
||||
@ -5222,26 +5308,34 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l197
|
||||
// CHECK11-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK11-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK11-NEXT: entry:
|
||||
// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[A:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[AA:%.*]] = alloca i16, align 2
|
||||
// CHECK11-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
|
||||
// CHECK11-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4
|
||||
// CHECK11-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4
|
||||
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4, !nonnull [[META20]], !align [[META21]]
|
||||
// CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
|
||||
// CHECK11-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4
|
||||
// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 4
|
||||
// CHECK11-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2
|
||||
// CHECK11-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2
|
||||
// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[AA_CASTED]], align 4
|
||||
// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l197.omp_outlined, i32 [[TMP2]], i32 [[TMP4]], ptr [[TMP0]])
|
||||
// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
|
||||
// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
|
||||
// CHECK11-NEXT: store i32 [[TMP2]], ptr [[A]], align 4
|
||||
// CHECK11-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
|
||||
// CHECK11-NEXT: [[TMP4:%.*]] = load i16, ptr [[TMP3]], align 4
|
||||
// CHECK11-NEXT: store i16 [[TMP4]], ptr [[AA]], align 2
|
||||
// CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 2
|
||||
// CHECK11-NEXT: [[B:%.*]] = load ptr, ptr [[TMP5]], align 4
|
||||
// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 3
|
||||
// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
|
||||
// CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[A]], align 4
|
||||
// CHECK11-NEXT: store i32 [[TMP6]], ptr [[A_CASTED]], align 4
|
||||
// CHECK11-NEXT: [[TMP7:%.*]] = load i32, ptr [[A_CASTED]], align 4
|
||||
// CHECK11-NEXT: [[TMP8:%.*]] = load i16, ptr [[AA]], align 2
|
||||
// CHECK11-NEXT: store i16 [[TMP8]], ptr [[AA_CASTED]], align 2
|
||||
// CHECK11-NEXT: [[TMP9:%.*]] = load i32, ptr [[AA_CASTED]], align 4
|
||||
// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l197.omp_outlined, i32 [[TMP7]], i32 [[TMP9]], ptr [[B]])
|
||||
// CHECK11-NEXT: ret void
|
||||
//
|
||||
//
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -584,17 +584,24 @@ int nested(int a){
|
||||
//
|
||||
//
|
||||
// TCHECK-TARGET-LABEL: define weak_odr protected void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6nestedi_l42
|
||||
// TCHECK-TARGET-SAME: (i64 noundef [[A:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// TCHECK-TARGET-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// TCHECK-TARGET-NEXT: entry:
|
||||
// TCHECK-TARGET-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
||||
// TCHECK-TARGET-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// TCHECK-TARGET-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8
|
||||
// TCHECK-TARGET-NEXT: [[A:%.*]] = alloca i32, align 4
|
||||
// TCHECK-TARGET-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
|
||||
// TCHECK-TARGET-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
||||
// TCHECK-TARGET-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8
|
||||
// TCHECK-TARGET-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// TCHECK-TARGET-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
|
||||
// TCHECK-TARGET-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4
|
||||
// TCHECK-TARGET-NEXT: [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 8
|
||||
// TCHECK-TARGET-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2:[0-9]+]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6nestedi_l42.omp_outlined, i64 [[TMP1]])
|
||||
// TCHECK-TARGET-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
|
||||
// TCHECK-TARGET-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
|
||||
// TCHECK-TARGET-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
|
||||
// TCHECK-TARGET-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 8
|
||||
// TCHECK-TARGET-NEXT: store i32 [[TMP2]], ptr [[A]], align 4
|
||||
// TCHECK-TARGET-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
|
||||
// TCHECK-TARGET-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
|
||||
// TCHECK-TARGET-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
|
||||
// TCHECK-TARGET-NEXT: [[TMP3:%.*]] = load i32, ptr [[A]], align 4
|
||||
// TCHECK-TARGET-NEXT: store i32 [[TMP3]], ptr [[A_CASTED]], align 4
|
||||
// TCHECK-TARGET-NEXT: [[TMP4:%.*]] = load i64, ptr [[A_CASTED]], align 8
|
||||
// TCHECK-TARGET-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2:[0-9]+]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6nestedi_l42.omp_outlined, i64 [[TMP4]])
|
||||
// TCHECK-TARGET-NEXT: ret void
|
||||
//
|
||||
//
|
||||
@ -664,17 +671,24 @@ int nested(int a){
|
||||
//
|
||||
//
|
||||
// TCHECK-TARGET-LABEL: define weak_odr protected void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6nestedi_l49
|
||||
// TCHECK-TARGET-SAME: (i64 noundef [[A:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// TCHECK-TARGET-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// TCHECK-TARGET-NEXT: entry:
|
||||
// TCHECK-TARGET-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
||||
// TCHECK-TARGET-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// TCHECK-TARGET-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8
|
||||
// TCHECK-TARGET-NEXT: [[A:%.*]] = alloca i32, align 4
|
||||
// TCHECK-TARGET-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
|
||||
// TCHECK-TARGET-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
||||
// TCHECK-TARGET-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8
|
||||
// TCHECK-TARGET-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// TCHECK-TARGET-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
|
||||
// TCHECK-TARGET-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4
|
||||
// TCHECK-TARGET-NEXT: [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 8
|
||||
// TCHECK-TARGET-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6nestedi_l49.omp_outlined, i64 [[TMP1]])
|
||||
// TCHECK-TARGET-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
|
||||
// TCHECK-TARGET-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
|
||||
// TCHECK-TARGET-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
|
||||
// TCHECK-TARGET-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 8
|
||||
// TCHECK-TARGET-NEXT: store i32 [[TMP2]], ptr [[A]], align 4
|
||||
// TCHECK-TARGET-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
|
||||
// TCHECK-TARGET-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
|
||||
// TCHECK-TARGET-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
|
||||
// TCHECK-TARGET-NEXT: [[TMP3:%.*]] = load i32, ptr [[A]], align 4
|
||||
// TCHECK-TARGET-NEXT: store i32 [[TMP3]], ptr [[A_CASTED]], align 4
|
||||
// TCHECK-TARGET-NEXT: [[TMP4:%.*]] = load i64, ptr [[A_CASTED]], align 8
|
||||
// TCHECK-TARGET-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6nestedi_l49.omp_outlined, i64 [[TMP4]])
|
||||
// TCHECK-TARGET-NEXT: ret void
|
||||
//
|
||||
//
|
||||
@ -744,17 +758,24 @@ int nested(int a){
|
||||
//
|
||||
//
|
||||
// TCHECK-TARGET-X86-LABEL: define weak_odr protected void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6nestedi_l42
|
||||
// TCHECK-TARGET-X86-SAME: (i32 noundef [[A:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// TCHECK-TARGET-X86-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// TCHECK-TARGET-X86-NEXT: entry:
|
||||
// TCHECK-TARGET-X86-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
||||
// TCHECK-TARGET-X86-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// TCHECK-TARGET-X86-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4
|
||||
// TCHECK-TARGET-X86-NEXT: [[A:%.*]] = alloca i32, align 4
|
||||
// TCHECK-TARGET-X86-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 4
|
||||
// TCHECK-TARGET-X86-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
||||
// TCHECK-TARGET-X86-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
|
||||
// TCHECK-TARGET-X86-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// TCHECK-TARGET-X86-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
|
||||
// TCHECK-TARGET-X86-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4
|
||||
// TCHECK-TARGET-X86-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 4
|
||||
// TCHECK-TARGET-X86-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2:[0-9]+]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6nestedi_l42.omp_outlined, i32 [[TMP1]])
|
||||
// TCHECK-TARGET-X86-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
|
||||
// TCHECK-TARGET-X86-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
|
||||
// TCHECK-TARGET-X86-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
|
||||
// TCHECK-TARGET-X86-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
|
||||
// TCHECK-TARGET-X86-NEXT: store i32 [[TMP2]], ptr [[A]], align 4
|
||||
// TCHECK-TARGET-X86-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
|
||||
// TCHECK-TARGET-X86-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
|
||||
// TCHECK-TARGET-X86-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
|
||||
// TCHECK-TARGET-X86-NEXT: [[TMP3:%.*]] = load i32, ptr [[A]], align 4
|
||||
// TCHECK-TARGET-X86-NEXT: store i32 [[TMP3]], ptr [[A_CASTED]], align 4
|
||||
// TCHECK-TARGET-X86-NEXT: [[TMP4:%.*]] = load i32, ptr [[A_CASTED]], align 4
|
||||
// TCHECK-TARGET-X86-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2:[0-9]+]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6nestedi_l42.omp_outlined, i32 [[TMP4]])
|
||||
// TCHECK-TARGET-X86-NEXT: ret void
|
||||
//
|
||||
//
|
||||
@ -824,17 +845,24 @@ int nested(int a){
|
||||
//
|
||||
//
|
||||
// TCHECK-TARGET-X86-LABEL: define weak_odr protected void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6nestedi_l49
|
||||
// TCHECK-TARGET-X86-SAME: (i32 noundef [[A:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// TCHECK-TARGET-X86-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// TCHECK-TARGET-X86-NEXT: entry:
|
||||
// TCHECK-TARGET-X86-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
||||
// TCHECK-TARGET-X86-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// TCHECK-TARGET-X86-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4
|
||||
// TCHECK-TARGET-X86-NEXT: [[A:%.*]] = alloca i32, align 4
|
||||
// TCHECK-TARGET-X86-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 4
|
||||
// TCHECK-TARGET-X86-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
||||
// TCHECK-TARGET-X86-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
|
||||
// TCHECK-TARGET-X86-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// TCHECK-TARGET-X86-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
|
||||
// TCHECK-TARGET-X86-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4
|
||||
// TCHECK-TARGET-X86-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 4
|
||||
// TCHECK-TARGET-X86-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6nestedi_l49.omp_outlined, i32 [[TMP1]])
|
||||
// TCHECK-TARGET-X86-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
|
||||
// TCHECK-TARGET-X86-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
|
||||
// TCHECK-TARGET-X86-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
|
||||
// TCHECK-TARGET-X86-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
|
||||
// TCHECK-TARGET-X86-NEXT: store i32 [[TMP2]], ptr [[A]], align 4
|
||||
// TCHECK-TARGET-X86-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
|
||||
// TCHECK-TARGET-X86-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
|
||||
// TCHECK-TARGET-X86-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
|
||||
// TCHECK-TARGET-X86-NEXT: [[TMP3:%.*]] = load i32, ptr [[A]], align 4
|
||||
// TCHECK-TARGET-X86-NEXT: store i32 [[TMP3]], ptr [[A_CASTED]], align 4
|
||||
// TCHECK-TARGET-X86-NEXT: [[TMP4:%.*]] = load i32, ptr [[A_CASTED]], align 4
|
||||
// TCHECK-TARGET-X86-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6nestedi_l49.omp_outlined, i32 [[TMP4]])
|
||||
// TCHECK-TARGET-X86-NEXT: ret void
|
||||
//
|
||||
//
|
||||
|
||||
@ -1613,18 +1613,27 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104
|
||||
// CHECK9-SAME: (i64 noundef [[DOTCAPTURE_EXPR_:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK9-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK9-NEXT: entry:
|
||||
// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
|
||||
// CHECK9-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
|
||||
// CHECK9-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]])
|
||||
// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8
|
||||
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP1:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 1
|
||||
// CHECK9-NEXT: [[LOADEDV:%.*]] = trunc i8 [[TMP1]] to i1
|
||||
// CHECK9-NEXT: br i1 [[LOADEDV]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
|
||||
// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 0
|
||||
// CHECK9-NEXT: [[TMP3:%.*]] = load i8, ptr [[TMP2]], align 8
|
||||
// CHECK9-NEXT: [[LOADEDV:%.*]] = trunc i8 [[TMP3]] to i1
|
||||
// CHECK9-NEXT: [[STOREDV:%.*]] = zext i1 [[LOADEDV]] to i8
|
||||
// CHECK9-NEXT: store i8 [[STOREDV]], ptr [[DOTCAPTURE_EXPR_]], align 1
|
||||
// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 1
|
||||
// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
|
||||
// CHECK9-NEXT: [[TMP4:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1
|
||||
// CHECK9-NEXT: [[LOADEDV2:%.*]] = trunc i8 [[TMP4]] to i1
|
||||
// CHECK9-NEXT: br i1 [[LOADEDV2]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
|
||||
// CHECK9: omp_if.then:
|
||||
// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104.omp_outlined)
|
||||
// CHECK9-NEXT: br label [[OMP_IF_END:%.*]]
|
||||
@ -1650,10 +1659,15 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108
|
||||
// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK9-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK9-NEXT: entry:
|
||||
// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
|
||||
// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
|
||||
// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108.omp_outlined)
|
||||
// CHECK9-NEXT: ret void
|
||||
//
|
||||
@ -1669,35 +1683,45 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121
|
||||
// CHECK9-SAME: (ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK9-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK9-NEXT: entry:
|
||||
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[B:%.*]] = alloca i32, align 4
|
||||
// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
|
||||
// CHECK9-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
|
||||
// CHECK9-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
|
||||
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
|
||||
// CHECK9-NEXT: store i64 [[B]], ptr [[B_ADDR]], align 8
|
||||
// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8
|
||||
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[B_ADDR]], align 4
|
||||
// CHECK9-NEXT: store i32 [[TMP2]], ptr [[B_CASTED]], align 4
|
||||
// CHECK9-NEXT: [[TMP3:%.*]] = load i64, ptr [[B_CASTED]], align 8
|
||||
// CHECK9-NEXT: [[TMP4:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 1
|
||||
// CHECK9-NEXT: [[LOADEDV:%.*]] = trunc i8 [[TMP4]] to i1
|
||||
// CHECK9-NEXT: br i1 [[LOADEDV]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
|
||||
// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 0
|
||||
// CHECK9-NEXT: [[THIS:%.*]] = load ptr, ptr [[TMP2]], align 8
|
||||
// CHECK9-NEXT: [[TMP3:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 1
|
||||
// CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 8
|
||||
// CHECK9-NEXT: store i32 [[TMP4]], ptr [[B]], align 4
|
||||
// CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 2
|
||||
// CHECK9-NEXT: [[TMP6:%.*]] = load i8, ptr [[TMP5]], align 8
|
||||
// CHECK9-NEXT: [[LOADEDV:%.*]] = trunc i8 [[TMP6]] to i1
|
||||
// CHECK9-NEXT: [[STOREDV:%.*]] = zext i1 [[LOADEDV]] to i8
|
||||
// CHECK9-NEXT: store i8 [[STOREDV]], ptr [[DOTCAPTURE_EXPR_]], align 1
|
||||
// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 3
|
||||
// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
|
||||
// CHECK9-NEXT: [[TMP7:%.*]] = load i32, ptr [[B]], align 4
|
||||
// CHECK9-NEXT: store i32 [[TMP7]], ptr [[B_CASTED]], align 4
|
||||
// CHECK9-NEXT: [[TMP8:%.*]] = load i64, ptr [[B_CASTED]], align 8
|
||||
// CHECK9-NEXT: [[TMP9:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1
|
||||
// CHECK9-NEXT: [[LOADEDV2:%.*]] = trunc i8 [[TMP9]] to i1
|
||||
// CHECK9-NEXT: br i1 [[LOADEDV2]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
|
||||
// CHECK9: omp_if.then:
|
||||
// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.omp_outlined, ptr [[TMP1]], i64 [[TMP3]])
|
||||
// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.omp_outlined, ptr [[THIS]], i64 [[TMP8]])
|
||||
// CHECK9-NEXT: br label [[OMP_IF_END:%.*]]
|
||||
// CHECK9: omp_if.else:
|
||||
// CHECK9-NEXT: call void @__kmpc_serialized_parallel(ptr @[[GLOB1]], i32 [[TMP0]])
|
||||
// CHECK9-NEXT: store i32 [[TMP0]], ptr [[DOTTHREADID_TEMP_]], align 4
|
||||
// CHECK9-NEXT: store i32 0, ptr [[DOTBOUND_ZERO_ADDR]], align 4
|
||||
// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTBOUND_ZERO_ADDR]], ptr [[TMP1]], i64 [[TMP3]]) #[[ATTR1]]
|
||||
// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTBOUND_ZERO_ADDR]], ptr [[THIS]], i64 [[TMP8]]) #[[ATTR1]]
|
||||
// CHECK9-NEXT: call void @__kmpc_end_serialized_parallel(ptr @[[GLOB1]], i32 [[TMP0]])
|
||||
// CHECK9-NEXT: br label [[OMP_IF_END]]
|
||||
// CHECK9: omp_if.end:
|
||||
@ -1725,29 +1749,37 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126
|
||||
// CHECK9-SAME: (ptr noundef [[THIS:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK9-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK9-NEXT: entry:
|
||||
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
|
||||
// CHECK9-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
|
||||
// CHECK9-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
|
||||
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
|
||||
// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8
|
||||
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP2:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 1
|
||||
// CHECK9-NEXT: [[LOADEDV:%.*]] = trunc i8 [[TMP2]] to i1
|
||||
// CHECK9-NEXT: br i1 [[LOADEDV]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
|
||||
// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 0
|
||||
// CHECK9-NEXT: [[THIS:%.*]] = load ptr, ptr [[TMP2]], align 8
|
||||
// CHECK9-NEXT: [[TMP3:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 1
|
||||
// CHECK9-NEXT: [[TMP4:%.*]] = load i8, ptr [[TMP3]], align 8
|
||||
// CHECK9-NEXT: [[LOADEDV:%.*]] = trunc i8 [[TMP4]] to i1
|
||||
// CHECK9-NEXT: [[STOREDV:%.*]] = zext i1 [[LOADEDV]] to i8
|
||||
// CHECK9-NEXT: store i8 [[STOREDV]], ptr [[DOTCAPTURE_EXPR_]], align 1
|
||||
// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 2
|
||||
// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
|
||||
// CHECK9-NEXT: [[TMP5:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1
|
||||
// CHECK9-NEXT: [[LOADEDV2:%.*]] = trunc i8 [[TMP5]] to i1
|
||||
// CHECK9-NEXT: br i1 [[LOADEDV2]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
|
||||
// CHECK9: omp_if.then:
|
||||
// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126.omp_outlined, ptr [[TMP1]])
|
||||
// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126.omp_outlined, ptr [[THIS]])
|
||||
// CHECK9-NEXT: br label [[OMP_IF_END:%.*]]
|
||||
// CHECK9: omp_if.else:
|
||||
// CHECK9-NEXT: call void @__kmpc_serialized_parallel(ptr @[[GLOB1]], i32 [[TMP0]])
|
||||
// CHECK9-NEXT: store i32 [[TMP0]], ptr [[DOTTHREADID_TEMP_]], align 4
|
||||
// CHECK9-NEXT: store i32 0, ptr [[DOTBOUND_ZERO_ADDR]], align 4
|
||||
// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126.omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTBOUND_ZERO_ADDR]], ptr [[TMP1]]) #[[ATTR1]]
|
||||
// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126.omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTBOUND_ZERO_ADDR]], ptr [[THIS]]) #[[ATTR1]]
|
||||
// CHECK9-NEXT: call void @__kmpc_end_serialized_parallel(ptr @[[GLOB1]], i32 [[TMP0]])
|
||||
// CHECK9-NEXT: br label [[OMP_IF_END]]
|
||||
// CHECK9: omp_if.end:
|
||||
@ -1770,23 +1802,30 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l87
|
||||
// CHECK9-SAME: (i64 noundef [[A:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK9-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK9-NEXT: entry:
|
||||
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[A:%.*]] = alloca i32, align 4
|
||||
// CHECK9-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
|
||||
// CHECK9-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
|
||||
// CHECK9-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8
|
||||
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
|
||||
// CHECK9-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4
|
||||
// CHECK9-NEXT: [[TMP2:%.*]] = load i64, ptr [[A_CASTED]], align 8
|
||||
// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 0
|
||||
// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 8
|
||||
// CHECK9-NEXT: store i32 [[TMP3]], ptr [[A]], align 4
|
||||
// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 1
|
||||
// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
|
||||
// CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[A]], align 4
|
||||
// CHECK9-NEXT: store i32 [[TMP4]], ptr [[A_CASTED]], align 4
|
||||
// CHECK9-NEXT: [[TMP5:%.*]] = load i64, ptr [[A_CASTED]], align 8
|
||||
// CHECK9-NEXT: call void @__kmpc_serialized_parallel(ptr @[[GLOB1]], i32 [[TMP0]])
|
||||
// CHECK9-NEXT: store i32 [[TMP0]], ptr [[DOTTHREADID_TEMP_]], align 4
|
||||
// CHECK9-NEXT: store i32 0, ptr [[DOTBOUND_ZERO_ADDR]], align 4
|
||||
// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l87.omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTBOUND_ZERO_ADDR]], i64 [[TMP2]]) #[[ATTR1]]
|
||||
// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l87.omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTBOUND_ZERO_ADDR]], i64 [[TMP5]]) #[[ATTR1]]
|
||||
// CHECK9-NEXT: call void @__kmpc_end_serialized_parallel(ptr @[[GLOB1]], i32 [[TMP0]])
|
||||
// CHECK9-NEXT: ret void
|
||||
//
|
||||
@ -1807,23 +1846,32 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93
|
||||
// CHECK9-SAME: (i64 noundef [[A:%.*]], i64 noundef [[B:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK9-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK9-NEXT: entry:
|
||||
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[A:%.*]] = alloca i32, align 4
|
||||
// CHECK9-NEXT: [[B:%.*]] = alloca i16, align 2
|
||||
// CHECK9-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8
|
||||
// CHECK9-NEXT: store i64 [[B]], ptr [[B_ADDR]], align 8
|
||||
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
|
||||
// CHECK9-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4
|
||||
// CHECK9-NEXT: [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 8
|
||||
// CHECK9-NEXT: [[TMP2:%.*]] = load i16, ptr [[B_ADDR]], align 2
|
||||
// CHECK9-NEXT: store i16 [[TMP2]], ptr [[B_CASTED]], align 2
|
||||
// CHECK9-NEXT: [[TMP3:%.*]] = load i64, ptr [[B_CASTED]], align 8
|
||||
// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93.omp_outlined, i64 [[TMP1]], i64 [[TMP3]])
|
||||
// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
|
||||
// CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 8
|
||||
// CHECK9-NEXT: store i32 [[TMP2]], ptr [[A]], align 4
|
||||
// CHECK9-NEXT: [[TMP3:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
|
||||
// CHECK9-NEXT: [[TMP4:%.*]] = load i16, ptr [[TMP3]], align 8
|
||||
// CHECK9-NEXT: store i16 [[TMP4]], ptr [[B]], align 2
|
||||
// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 2
|
||||
// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
|
||||
// CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[A]], align 4
|
||||
// CHECK9-NEXT: store i32 [[TMP5]], ptr [[A_CASTED]], align 4
|
||||
// CHECK9-NEXT: [[TMP6:%.*]] = load i64, ptr [[A_CASTED]], align 8
|
||||
// CHECK9-NEXT: [[TMP7:%.*]] = load i16, ptr [[B]], align 2
|
||||
// CHECK9-NEXT: store i16 [[TMP7]], ptr [[B_CASTED]], align 2
|
||||
// CHECK9-NEXT: [[TMP8:%.*]] = load i64, ptr [[B_CASTED]], align 8
|
||||
// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93.omp_outlined, i64 [[TMP6]], i64 [[TMP8]])
|
||||
// CHECK9-NEXT: ret void
|
||||
//
|
||||
//
|
||||
@ -1847,18 +1895,27 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104
|
||||
// CHECK11-SAME: (i32 noundef [[DOTCAPTURE_EXPR_:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK11-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK11-NEXT: entry:
|
||||
// CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
|
||||
// CHECK11-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]])
|
||||
// CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
|
||||
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP1:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 1
|
||||
// CHECK11-NEXT: [[LOADEDV:%.*]] = trunc i8 [[TMP1]] to i1
|
||||
// CHECK11-NEXT: br i1 [[LOADEDV]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
|
||||
// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 0
|
||||
// CHECK11-NEXT: [[TMP3:%.*]] = load i8, ptr [[TMP2]], align 4
|
||||
// CHECK11-NEXT: [[LOADEDV:%.*]] = trunc i8 [[TMP3]] to i1
|
||||
// CHECK11-NEXT: [[STOREDV:%.*]] = zext i1 [[LOADEDV]] to i8
|
||||
// CHECK11-NEXT: store i8 [[STOREDV]], ptr [[DOTCAPTURE_EXPR_]], align 1
|
||||
// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 1
|
||||
// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
|
||||
// CHECK11-NEXT: [[TMP4:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1
|
||||
// CHECK11-NEXT: [[LOADEDV2:%.*]] = trunc i8 [[TMP4]] to i1
|
||||
// CHECK11-NEXT: br i1 [[LOADEDV2]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
|
||||
// CHECK11: omp_if.then:
|
||||
// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104.omp_outlined)
|
||||
// CHECK11-NEXT: br label [[OMP_IF_END:%.*]]
|
||||
@ -1884,10 +1941,15 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108
|
||||
// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK11-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK11-NEXT: entry:
|
||||
// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
|
||||
// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
|
||||
// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108.omp_outlined)
|
||||
// CHECK11-NEXT: ret void
|
||||
//
|
||||
@ -1903,35 +1965,45 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121
|
||||
// CHECK11-SAME: (ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK11-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK11-NEXT: entry:
|
||||
// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[B:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
|
||||
// CHECK11-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
|
||||
// CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
|
||||
// CHECK11-NEXT: store i32 [[B]], ptr [[B_ADDR]], align 4
|
||||
// CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
|
||||
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[B_ADDR]], align 4
|
||||
// CHECK11-NEXT: store i32 [[TMP2]], ptr [[B_CASTED]], align 4
|
||||
// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[B_CASTED]], align 4
|
||||
// CHECK11-NEXT: [[TMP4:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 1
|
||||
// CHECK11-NEXT: [[LOADEDV:%.*]] = trunc i8 [[TMP4]] to i1
|
||||
// CHECK11-NEXT: br i1 [[LOADEDV]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
|
||||
// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 0
|
||||
// CHECK11-NEXT: [[THIS:%.*]] = load ptr, ptr [[TMP2]], align 4
|
||||
// CHECK11-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 1
|
||||
// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4
|
||||
// CHECK11-NEXT: store i32 [[TMP4]], ptr [[B]], align 4
|
||||
// CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 2
|
||||
// CHECK11-NEXT: [[TMP6:%.*]] = load i8, ptr [[TMP5]], align 4
|
||||
// CHECK11-NEXT: [[LOADEDV:%.*]] = trunc i8 [[TMP6]] to i1
|
||||
// CHECK11-NEXT: [[STOREDV:%.*]] = zext i1 [[LOADEDV]] to i8
|
||||
// CHECK11-NEXT: store i8 [[STOREDV]], ptr [[DOTCAPTURE_EXPR_]], align 1
|
||||
// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 3
|
||||
// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
|
||||
// CHECK11-NEXT: [[TMP7:%.*]] = load i32, ptr [[B]], align 4
|
||||
// CHECK11-NEXT: store i32 [[TMP7]], ptr [[B_CASTED]], align 4
|
||||
// CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[B_CASTED]], align 4
|
||||
// CHECK11-NEXT: [[TMP9:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1
|
||||
// CHECK11-NEXT: [[LOADEDV2:%.*]] = trunc i8 [[TMP9]] to i1
|
||||
// CHECK11-NEXT: br i1 [[LOADEDV2]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
|
||||
// CHECK11: omp_if.then:
|
||||
// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.omp_outlined, ptr [[TMP1]], i32 [[TMP3]])
|
||||
// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.omp_outlined, ptr [[THIS]], i32 [[TMP8]])
|
||||
// CHECK11-NEXT: br label [[OMP_IF_END:%.*]]
|
||||
// CHECK11: omp_if.else:
|
||||
// CHECK11-NEXT: call void @__kmpc_serialized_parallel(ptr @[[GLOB1]], i32 [[TMP0]])
|
||||
// CHECK11-NEXT: store i32 [[TMP0]], ptr [[DOTTHREADID_TEMP_]], align 4
|
||||
// CHECK11-NEXT: store i32 0, ptr [[DOTBOUND_ZERO_ADDR]], align 4
|
||||
// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTBOUND_ZERO_ADDR]], ptr [[TMP1]], i32 [[TMP3]]) #[[ATTR1]]
|
||||
// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTBOUND_ZERO_ADDR]], ptr [[THIS]], i32 [[TMP8]]) #[[ATTR1]]
|
||||
// CHECK11-NEXT: call void @__kmpc_end_serialized_parallel(ptr @[[GLOB1]], i32 [[TMP0]])
|
||||
// CHECK11-NEXT: br label [[OMP_IF_END]]
|
||||
// CHECK11: omp_if.end:
|
||||
@ -1959,29 +2031,37 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126
|
||||
// CHECK11-SAME: (ptr noundef [[THIS:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK11-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK11-NEXT: entry:
|
||||
// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
|
||||
// CHECK11-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
|
||||
// CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
|
||||
// CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
|
||||
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP2:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 1
|
||||
// CHECK11-NEXT: [[LOADEDV:%.*]] = trunc i8 [[TMP2]] to i1
|
||||
// CHECK11-NEXT: br i1 [[LOADEDV]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
|
||||
// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 0
|
||||
// CHECK11-NEXT: [[THIS:%.*]] = load ptr, ptr [[TMP2]], align 4
|
||||
// CHECK11-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 1
|
||||
// CHECK11-NEXT: [[TMP4:%.*]] = load i8, ptr [[TMP3]], align 4
|
||||
// CHECK11-NEXT: [[LOADEDV:%.*]] = trunc i8 [[TMP4]] to i1
|
||||
// CHECK11-NEXT: [[STOREDV:%.*]] = zext i1 [[LOADEDV]] to i8
|
||||
// CHECK11-NEXT: store i8 [[STOREDV]], ptr [[DOTCAPTURE_EXPR_]], align 1
|
||||
// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 2
|
||||
// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
|
||||
// CHECK11-NEXT: [[TMP5:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1
|
||||
// CHECK11-NEXT: [[LOADEDV2:%.*]] = trunc i8 [[TMP5]] to i1
|
||||
// CHECK11-NEXT: br i1 [[LOADEDV2]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
|
||||
// CHECK11: omp_if.then:
|
||||
// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126.omp_outlined, ptr [[TMP1]])
|
||||
// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126.omp_outlined, ptr [[THIS]])
|
||||
// CHECK11-NEXT: br label [[OMP_IF_END:%.*]]
|
||||
// CHECK11: omp_if.else:
|
||||
// CHECK11-NEXT: call void @__kmpc_serialized_parallel(ptr @[[GLOB1]], i32 [[TMP0]])
|
||||
// CHECK11-NEXT: store i32 [[TMP0]], ptr [[DOTTHREADID_TEMP_]], align 4
|
||||
// CHECK11-NEXT: store i32 0, ptr [[DOTBOUND_ZERO_ADDR]], align 4
|
||||
// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126.omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTBOUND_ZERO_ADDR]], ptr [[TMP1]]) #[[ATTR1]]
|
||||
// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126.omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTBOUND_ZERO_ADDR]], ptr [[THIS]]) #[[ATTR1]]
|
||||
// CHECK11-NEXT: call void @__kmpc_end_serialized_parallel(ptr @[[GLOB1]], i32 [[TMP0]])
|
||||
// CHECK11-NEXT: br label [[OMP_IF_END]]
|
||||
// CHECK11: omp_if.end:
|
||||
@ -2004,23 +2084,30 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l87
|
||||
// CHECK11-SAME: (i32 noundef [[A:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK11-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK11-NEXT: entry:
|
||||
// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[A:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
|
||||
// CHECK11-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
|
||||
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
|
||||
// CHECK11-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4
|
||||
// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 4
|
||||
// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 0
|
||||
// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
|
||||
// CHECK11-NEXT: store i32 [[TMP3]], ptr [[A]], align 4
|
||||
// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 1
|
||||
// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
|
||||
// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[A]], align 4
|
||||
// CHECK11-NEXT: store i32 [[TMP4]], ptr [[A_CASTED]], align 4
|
||||
// CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[A_CASTED]], align 4
|
||||
// CHECK11-NEXT: call void @__kmpc_serialized_parallel(ptr @[[GLOB1]], i32 [[TMP0]])
|
||||
// CHECK11-NEXT: store i32 [[TMP0]], ptr [[DOTTHREADID_TEMP_]], align 4
|
||||
// CHECK11-NEXT: store i32 0, ptr [[DOTBOUND_ZERO_ADDR]], align 4
|
||||
// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l87.omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTBOUND_ZERO_ADDR]], i32 [[TMP2]]) #[[ATTR1]]
|
||||
// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l87.omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTBOUND_ZERO_ADDR]], i32 [[TMP5]]) #[[ATTR1]]
|
||||
// CHECK11-NEXT: call void @__kmpc_end_serialized_parallel(ptr @[[GLOB1]], i32 [[TMP0]])
|
||||
// CHECK11-NEXT: ret void
|
||||
//
|
||||
@ -2041,23 +2128,32 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93
|
||||
// CHECK11-SAME: (i32 noundef [[A:%.*]], i32 noundef [[B:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK11-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK11-NEXT: entry:
|
||||
// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[A:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[B:%.*]] = alloca i16, align 2
|
||||
// CHECK11-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
|
||||
// CHECK11-NEXT: store i32 [[B]], ptr [[B_ADDR]], align 4
|
||||
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
|
||||
// CHECK11-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4
|
||||
// CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 4
|
||||
// CHECK11-NEXT: [[TMP2:%.*]] = load i16, ptr [[B_ADDR]], align 2
|
||||
// CHECK11-NEXT: store i16 [[TMP2]], ptr [[B_CASTED]], align 2
|
||||
// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[B_CASTED]], align 4
|
||||
// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93.omp_outlined, i32 [[TMP1]], i32 [[TMP3]])
|
||||
// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
|
||||
// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
|
||||
// CHECK11-NEXT: store i32 [[TMP2]], ptr [[A]], align 4
|
||||
// CHECK11-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
|
||||
// CHECK11-NEXT: [[TMP4:%.*]] = load i16, ptr [[TMP3]], align 4
|
||||
// CHECK11-NEXT: store i16 [[TMP4]], ptr [[B]], align 2
|
||||
// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 2
|
||||
// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
|
||||
// CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[A]], align 4
|
||||
// CHECK11-NEXT: store i32 [[TMP5]], ptr [[A_CASTED]], align 4
|
||||
// CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[A_CASTED]], align 4
|
||||
// CHECK11-NEXT: [[TMP7:%.*]] = load i16, ptr [[B]], align 2
|
||||
// CHECK11-NEXT: store i16 [[TMP7]], ptr [[B_CASTED]], align 2
|
||||
// CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[B_CASTED]], align 4
|
||||
// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93.omp_outlined, i32 [[TMP6]], i32 [[TMP8]])
|
||||
// CHECK11-NEXT: ret void
|
||||
//
|
||||
//
|
||||
|
||||
@ -1452,15 +1452,22 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104
|
||||
// CHECK9-SAME: (i64 noundef [[DOTCAPTURE_EXPR_:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK9-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK9-NEXT: entry:
|
||||
// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
|
||||
// CHECK9-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]])
|
||||
// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8
|
||||
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
|
||||
// CHECK9-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]])
|
||||
// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 0
|
||||
// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 8
|
||||
// CHECK9-NEXT: store i32 [[TMP3]], ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 1
|
||||
// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
|
||||
// CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
// CHECK9-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP4]])
|
||||
// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104.omp_outlined)
|
||||
// CHECK9-NEXT: ret void
|
||||
//
|
||||
@ -1476,15 +1483,22 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108
|
||||
// CHECK9-SAME: (i64 noundef [[DOTCAPTURE_EXPR_:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK9-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK9-NEXT: entry:
|
||||
// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
|
||||
// CHECK9-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
|
||||
// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8
|
||||
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
|
||||
// CHECK9-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]])
|
||||
// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 0
|
||||
// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 8
|
||||
// CHECK9-NEXT: store i32 [[TMP3]], ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 1
|
||||
// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
|
||||
// CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
// CHECK9-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP4]])
|
||||
// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108.omp_outlined)
|
||||
// CHECK9-NEXT: ret void
|
||||
//
|
||||
@ -1500,25 +1514,33 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121
|
||||
// CHECK9-SAME: (ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK9-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK9-NEXT: entry:
|
||||
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[B:%.*]] = alloca i32, align 4
|
||||
// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
|
||||
// CHECK9-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
|
||||
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
|
||||
// CHECK9-NEXT: store i64 [[B]], ptr [[B_ADDR]], align 8
|
||||
// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8
|
||||
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
|
||||
// CHECK9-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]])
|
||||
// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[B_ADDR]], align 4
|
||||
// CHECK9-NEXT: store i32 [[TMP3]], ptr [[B_CASTED]], align 4
|
||||
// CHECK9-NEXT: [[TMP4:%.*]] = load i64, ptr [[B_CASTED]], align 8
|
||||
// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.omp_outlined, ptr [[TMP1]], i64 [[TMP4]])
|
||||
// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 0
|
||||
// CHECK9-NEXT: [[THIS:%.*]] = load ptr, ptr [[TMP2]], align 8
|
||||
// CHECK9-NEXT: [[TMP3:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 1
|
||||
// CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 8
|
||||
// CHECK9-NEXT: store i32 [[TMP4]], ptr [[B]], align 4
|
||||
// CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 2
|
||||
// CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 8
|
||||
// CHECK9-NEXT: store i32 [[TMP6]], ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 3
|
||||
// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
|
||||
// CHECK9-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
// CHECK9-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP7]])
|
||||
// CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[B]], align 4
|
||||
// CHECK9-NEXT: store i32 [[TMP8]], ptr [[B_CASTED]], align 4
|
||||
// CHECK9-NEXT: [[TMP9:%.*]] = load i64, ptr [[B_CASTED]], align 8
|
||||
// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.omp_outlined, ptr [[THIS]], i64 [[TMP9]])
|
||||
// CHECK9-NEXT: ret void
|
||||
//
|
||||
//
|
||||
@ -1543,16 +1565,20 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126
|
||||
// CHECK9-SAME: (ptr noundef [[THIS:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK9-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK9-NEXT: entry:
|
||||
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
|
||||
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
|
||||
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
|
||||
// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 0
|
||||
// CHECK9-NEXT: [[THIS:%.*]] = load ptr, ptr [[TMP2]], align 8
|
||||
// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 1
|
||||
// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
|
||||
// CHECK9-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB1]], i32 [[TMP0]], i32 1024)
|
||||
// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126.omp_outlined, ptr [[TMP1]])
|
||||
// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126.omp_outlined, ptr [[THIS]])
|
||||
// CHECK9-NEXT: ret void
|
||||
//
|
||||
//
|
||||
@ -1572,11 +1598,16 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88
|
||||
// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK9-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK9-NEXT: entry:
|
||||
// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
|
||||
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 0
|
||||
// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
|
||||
// CHECK9-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB1]], i32 [[TMP0]], i32 20)
|
||||
// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88.omp_outlined)
|
||||
// CHECK9-NEXT: ret void
|
||||
@ -1593,29 +1624,40 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93
|
||||
// CHECK9-SAME: (i64 noundef [[A:%.*]], i64 noundef [[B:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK9-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK9-NEXT: entry:
|
||||
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[A:%.*]] = alloca i32, align 4
|
||||
// CHECK9-NEXT: [[B:%.*]] = alloca i16, align 2
|
||||
// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2
|
||||
// CHECK9-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
|
||||
// CHECK9-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8
|
||||
// CHECK9-NEXT: store i64 [[B]], ptr [[B_ADDR]], align 8
|
||||
// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8
|
||||
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP1:%.*]] = load i16, ptr [[DOTCAPTURE_EXPR__ADDR]], align 2
|
||||
// CHECK9-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32
|
||||
// CHECK9-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]])
|
||||
// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[A_ADDR]], align 4
|
||||
// CHECK9-NEXT: store i32 [[TMP3]], ptr [[A_CASTED]], align 4
|
||||
// CHECK9-NEXT: [[TMP4:%.*]] = load i64, ptr [[A_CASTED]], align 8
|
||||
// CHECK9-NEXT: [[TMP5:%.*]] = load i16, ptr [[B_ADDR]], align 2
|
||||
// CHECK9-NEXT: store i16 [[TMP5]], ptr [[B_CASTED]], align 2
|
||||
// CHECK9-NEXT: [[TMP6:%.*]] = load i64, ptr [[B_CASTED]], align 8
|
||||
// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93.omp_outlined, i64 [[TMP4]], i64 [[TMP6]])
|
||||
// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 0
|
||||
// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 8
|
||||
// CHECK9-NEXT: store i32 [[TMP3]], ptr [[A]], align 4
|
||||
// CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 1
|
||||
// CHECK9-NEXT: [[TMP5:%.*]] = load i16, ptr [[TMP4]], align 8
|
||||
// CHECK9-NEXT: store i16 [[TMP5]], ptr [[B]], align 2
|
||||
// CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 2
|
||||
// CHECK9-NEXT: [[TMP7:%.*]] = load i16, ptr [[TMP6]], align 8
|
||||
// CHECK9-NEXT: store i16 [[TMP7]], ptr [[DOTCAPTURE_EXPR_]], align 2
|
||||
// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 3
|
||||
// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
|
||||
// CHECK9-NEXT: [[TMP8:%.*]] = load i16, ptr [[DOTCAPTURE_EXPR_]], align 2
|
||||
// CHECK9-NEXT: [[TMP9:%.*]] = sext i16 [[TMP8]] to i32
|
||||
// CHECK9-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP9]])
|
||||
// CHECK9-NEXT: [[TMP10:%.*]] = load i32, ptr [[A]], align 4
|
||||
// CHECK9-NEXT: store i32 [[TMP10]], ptr [[A_CASTED]], align 4
|
||||
// CHECK9-NEXT: [[TMP11:%.*]] = load i64, ptr [[A_CASTED]], align 8
|
||||
// CHECK9-NEXT: [[TMP12:%.*]] = load i16, ptr [[B]], align 2
|
||||
// CHECK9-NEXT: store i16 [[TMP12]], ptr [[B_CASTED]], align 2
|
||||
// CHECK9-NEXT: [[TMP13:%.*]] = load i64, ptr [[B_CASTED]], align 8
|
||||
// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93.omp_outlined, i64 [[TMP11]], i64 [[TMP13]])
|
||||
// CHECK9-NEXT: ret void
|
||||
//
|
||||
//
|
||||
@ -1639,15 +1681,22 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104
|
||||
// CHECK11-SAME: (i32 noundef [[DOTCAPTURE_EXPR_:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK11-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK11-NEXT: entry:
|
||||
// CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]])
|
||||
// CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
|
||||
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
|
||||
// CHECK11-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]])
|
||||
// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 0
|
||||
// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
|
||||
// CHECK11-NEXT: store i32 [[TMP3]], ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 1
|
||||
// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
|
||||
// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
// CHECK11-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP4]])
|
||||
// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104.omp_outlined)
|
||||
// CHECK11-NEXT: ret void
|
||||
//
|
||||
@ -1663,15 +1712,22 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108
|
||||
// CHECK11-SAME: (i32 noundef [[DOTCAPTURE_EXPR_:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK11-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK11-NEXT: entry:
|
||||
// CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
|
||||
// CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
|
||||
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
|
||||
// CHECK11-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]])
|
||||
// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 0
|
||||
// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
|
||||
// CHECK11-NEXT: store i32 [[TMP3]], ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 1
|
||||
// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
|
||||
// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
// CHECK11-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP4]])
|
||||
// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108.omp_outlined)
|
||||
// CHECK11-NEXT: ret void
|
||||
//
|
||||
@ -1687,25 +1743,33 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121
|
||||
// CHECK11-SAME: (ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK11-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK11-NEXT: entry:
|
||||
// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[B:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
|
||||
// CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
|
||||
// CHECK11-NEXT: store i32 [[B]], ptr [[B_ADDR]], align 4
|
||||
// CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
|
||||
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
|
||||
// CHECK11-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]])
|
||||
// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[B_ADDR]], align 4
|
||||
// CHECK11-NEXT: store i32 [[TMP3]], ptr [[B_CASTED]], align 4
|
||||
// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[B_CASTED]], align 4
|
||||
// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.omp_outlined, ptr [[TMP1]], i32 [[TMP4]])
|
||||
// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 0
|
||||
// CHECK11-NEXT: [[THIS:%.*]] = load ptr, ptr [[TMP2]], align 4
|
||||
// CHECK11-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 1
|
||||
// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4
|
||||
// CHECK11-NEXT: store i32 [[TMP4]], ptr [[B]], align 4
|
||||
// CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 2
|
||||
// CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4
|
||||
// CHECK11-NEXT: store i32 [[TMP6]], ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 3
|
||||
// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
|
||||
// CHECK11-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
// CHECK11-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP7]])
|
||||
// CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[B]], align 4
|
||||
// CHECK11-NEXT: store i32 [[TMP8]], ptr [[B_CASTED]], align 4
|
||||
// CHECK11-NEXT: [[TMP9:%.*]] = load i32, ptr [[B_CASTED]], align 4
|
||||
// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.omp_outlined, ptr [[THIS]], i32 [[TMP9]])
|
||||
// CHECK11-NEXT: ret void
|
||||
//
|
||||
//
|
||||
@ -1730,16 +1794,20 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126
|
||||
// CHECK11-SAME: (ptr noundef [[THIS:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK11-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK11-NEXT: entry:
|
||||
// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
|
||||
// CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
|
||||
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
|
||||
// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 0
|
||||
// CHECK11-NEXT: [[THIS:%.*]] = load ptr, ptr [[TMP2]], align 4
|
||||
// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 1
|
||||
// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
|
||||
// CHECK11-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB1]], i32 [[TMP0]], i32 1024)
|
||||
// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126.omp_outlined, ptr [[TMP1]])
|
||||
// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126.omp_outlined, ptr [[THIS]])
|
||||
// CHECK11-NEXT: ret void
|
||||
//
|
||||
//
|
||||
@ -1759,11 +1827,16 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88
|
||||
// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK11-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK11-NEXT: entry:
|
||||
// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
|
||||
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 0
|
||||
// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
|
||||
// CHECK11-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB1]], i32 [[TMP0]], i32 20)
|
||||
// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88.omp_outlined)
|
||||
// CHECK11-NEXT: ret void
|
||||
@ -1780,29 +1853,40 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93
|
||||
// CHECK11-SAME: (i32 noundef [[A:%.*]], i32 noundef [[B:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK11-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK11-NEXT: entry:
|
||||
// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[A:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[B:%.*]] = alloca i16, align 2
|
||||
// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2
|
||||
// CHECK11-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
|
||||
// CHECK11-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
|
||||
// CHECK11-NEXT: store i32 [[B]], ptr [[B_ADDR]], align 4
|
||||
// CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
|
||||
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP1:%.*]] = load i16, ptr [[DOTCAPTURE_EXPR__ADDR]], align 2
|
||||
// CHECK11-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32
|
||||
// CHECK11-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]])
|
||||
// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[A_ADDR]], align 4
|
||||
// CHECK11-NEXT: store i32 [[TMP3]], ptr [[A_CASTED]], align 4
|
||||
// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[A_CASTED]], align 4
|
||||
// CHECK11-NEXT: [[TMP5:%.*]] = load i16, ptr [[B_ADDR]], align 2
|
||||
// CHECK11-NEXT: store i16 [[TMP5]], ptr [[B_CASTED]], align 2
|
||||
// CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[B_CASTED]], align 4
|
||||
// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93.omp_outlined, i32 [[TMP4]], i32 [[TMP6]])
|
||||
// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 0
|
||||
// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
|
||||
// CHECK11-NEXT: store i32 [[TMP3]], ptr [[A]], align 4
|
||||
// CHECK11-NEXT: [[TMP4:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 1
|
||||
// CHECK11-NEXT: [[TMP5:%.*]] = load i16, ptr [[TMP4]], align 4
|
||||
// CHECK11-NEXT: store i16 [[TMP5]], ptr [[B]], align 2
|
||||
// CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 2
|
||||
// CHECK11-NEXT: [[TMP7:%.*]] = load i16, ptr [[TMP6]], align 4
|
||||
// CHECK11-NEXT: store i16 [[TMP7]], ptr [[DOTCAPTURE_EXPR_]], align 2
|
||||
// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 3
|
||||
// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
|
||||
// CHECK11-NEXT: [[TMP8:%.*]] = load i16, ptr [[DOTCAPTURE_EXPR_]], align 2
|
||||
// CHECK11-NEXT: [[TMP9:%.*]] = sext i16 [[TMP8]] to i32
|
||||
// CHECK11-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP9]])
|
||||
// CHECK11-NEXT: [[TMP10:%.*]] = load i32, ptr [[A]], align 4
|
||||
// CHECK11-NEXT: store i32 [[TMP10]], ptr [[A_CASTED]], align 4
|
||||
// CHECK11-NEXT: [[TMP11:%.*]] = load i32, ptr [[A_CASTED]], align 4
|
||||
// CHECK11-NEXT: [[TMP12:%.*]] = load i16, ptr [[B]], align 2
|
||||
// CHECK11-NEXT: store i16 [[TMP12]], ptr [[B_CASTED]], align 2
|
||||
// CHECK11-NEXT: [[TMP13:%.*]] = load i32, ptr [[B_CASTED]], align 4
|
||||
// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93.omp_outlined, i32 [[TMP11]], i32 [[TMP13]])
|
||||
// CHECK11-NEXT: ret void
|
||||
//
|
||||
//
|
||||
|
||||
@ -1088,22 +1088,28 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l61
|
||||
// CHECK9-SAME: (i64 noundef [[DOTCAPTURE_EXPR_:%.*]], ptr noundef nonnull align 1 dereferenceable(4) [[DOTCAPTURE_EXPR_1:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK9-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK9-NEXT: entry:
|
||||
// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
|
||||
// CHECK9-NEXT: [[DYN_PTR2:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[TMP:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]])
|
||||
// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8
|
||||
// CHECK9-NEXT: store ptr [[DOTCAPTURE_EXPR_1]], ptr [[DOTCAPTURE_EXPR__ADDR2]], align 8
|
||||
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR__ADDR2]], align 8, !nonnull [[META11:![0-9]+]]
|
||||
// CHECK9-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 8
|
||||
// CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
|
||||
// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META11]]
|
||||
// CHECK9-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [4 x i8], ptr [[TMP3]], i64 0, i64 0
|
||||
// CHECK9-NEXT: call void @__kmpc_push_num_threads_strict(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 2, ptr [[ARRAYDECAY]])
|
||||
// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 0
|
||||
// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 8
|
||||
// CHECK9-NEXT: store i32 [[TMP3]], ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
// CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 1
|
||||
// CHECK9-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = load ptr, ptr [[TMP4]], align 8
|
||||
// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 2
|
||||
// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR2]], align 8
|
||||
// CHECK9-NEXT: store ptr [[DOTCAPTURE_EXPR_1]], ptr [[TMP]], align 8
|
||||
// CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
// CHECK9-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META11:![0-9]+]]
|
||||
// CHECK9-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [4 x i8], ptr [[TMP6]], i64 0, i64 0
|
||||
// CHECK9-NEXT: call void @__kmpc_push_num_threads_strict(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP5]], i32 2, ptr [[ARRAYDECAY]])
|
||||
// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l61.omp_outlined)
|
||||
// CHECK9-NEXT: ret void
|
||||
//
|
||||
@ -1119,15 +1125,22 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l65
|
||||
// CHECK9-SAME: (i64 noundef [[DOTCAPTURE_EXPR_:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK9-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK9-NEXT: entry:
|
||||
// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
|
||||
// CHECK9-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
|
||||
// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8
|
||||
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
|
||||
// CHECK9-NEXT: call void @__kmpc_push_num_threads_strict(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 1, ptr null)
|
||||
// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 0
|
||||
// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 8
|
||||
// CHECK9-NEXT: store i32 [[TMP3]], ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 1
|
||||
// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
|
||||
// CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
// CHECK9-NEXT: call void @__kmpc_push_num_threads_strict(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP4]], i32 1, ptr null)
|
||||
// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l65.omp_outlined)
|
||||
// CHECK9-NEXT: ret void
|
||||
//
|
||||
@ -1143,20 +1156,29 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3bari_l95
|
||||
// CHECK9-SAME: (i64 noundef [[A:%.*]], i64 noundef [[N:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK9-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK9-NEXT: entry:
|
||||
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[A:%.*]] = alloca i32, align 4
|
||||
// CHECK9-NEXT: [[N:%.*]] = alloca i32, align 4
|
||||
// CHECK9-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8
|
||||
// CHECK9-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8
|
||||
// CHECK9-NEXT: store i64 [[N]], ptr [[N_ADDR]], align 8
|
||||
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4
|
||||
// CHECK9-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(ptr noundef nonnull align 8 dereferenceable(8) [[S]], i32 noundef signext [[TMP0]])
|
||||
// CHECK9-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
|
||||
// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
|
||||
// CHECK9-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 4
|
||||
// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
|
||||
// CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 8
|
||||
// CHECK9-NEXT: store i32 [[TMP2]], ptr [[A]], align 4
|
||||
// CHECK9-NEXT: [[TMP3:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
|
||||
// CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 8
|
||||
// CHECK9-NEXT: store i32 [[TMP4]], ptr [[N]], align 4
|
||||
// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 2
|
||||
// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
|
||||
// CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[N]], align 4
|
||||
// CHECK9-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(ptr noundef nonnull align 8 dereferenceable(8) [[S]], i32 noundef signext [[TMP5]])
|
||||
// CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[A]], align 4
|
||||
// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], [[CALL]]
|
||||
// CHECK9-NEXT: store i32 [[ADD]], ptr [[A]], align 4
|
||||
// CHECK9-NEXT: ret void
|
||||
//
|
||||
//
|
||||
@ -1185,19 +1207,28 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3bari_l103
|
||||
// CHECK9-SAME: (i64 noundef [[A:%.*]], i64 noundef [[N:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK9-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK9-NEXT: entry:
|
||||
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8
|
||||
// CHECK9-NEXT: store i64 [[N]], ptr [[N_ADDR]], align 8
|
||||
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4
|
||||
// CHECK9-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP0]])
|
||||
// CHECK9-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
|
||||
// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
|
||||
// CHECK9-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 4
|
||||
// CHECK9-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[A:%.*]] = alloca i32, align 4
|
||||
// CHECK9-NEXT: [[N:%.*]] = alloca i32, align 4
|
||||
// CHECK9-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
|
||||
// CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 8
|
||||
// CHECK9-NEXT: store i32 [[TMP2]], ptr [[A]], align 4
|
||||
// CHECK9-NEXT: [[TMP3:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
|
||||
// CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 8
|
||||
// CHECK9-NEXT: store i32 [[TMP4]], ptr [[N]], align 4
|
||||
// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 2
|
||||
// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
|
||||
// CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[N]], align 4
|
||||
// CHECK9-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP5]])
|
||||
// CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[A]], align 4
|
||||
// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], [[CALL]]
|
||||
// CHECK9-NEXT: store i32 [[ADD]], ptr [[A]], align 4
|
||||
// CHECK9-NEXT: ret void
|
||||
//
|
||||
//
|
||||
@ -1289,20 +1320,29 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3bari_l95
|
||||
// CHECK10-SAME: (i64 noundef [[A:%.*]], i64 noundef [[N:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK10-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK10-NEXT: entry:
|
||||
// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK10-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK10-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK10-NEXT: [[A:%.*]] = alloca i32, align 4
|
||||
// CHECK10-NEXT: [[N:%.*]] = alloca i32, align 4
|
||||
// CHECK10-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
|
||||
// CHECK10-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8
|
||||
// CHECK10-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8
|
||||
// CHECK10-NEXT: store i64 [[N]], ptr [[N_ADDR]], align 8
|
||||
// CHECK10-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK10-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4
|
||||
// CHECK10-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(ptr noundef nonnull align 8 dereferenceable(8) [[S]], i32 noundef signext [[TMP0]])
|
||||
// CHECK10-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
|
||||
// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
|
||||
// CHECK10-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 4
|
||||
// CHECK10-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK10-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK10-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
|
||||
// CHECK10-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 8
|
||||
// CHECK10-NEXT: store i32 [[TMP2]], ptr [[A]], align 4
|
||||
// CHECK10-NEXT: [[TMP3:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
|
||||
// CHECK10-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 8
|
||||
// CHECK10-NEXT: store i32 [[TMP4]], ptr [[N]], align 4
|
||||
// CHECK10-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 2
|
||||
// CHECK10-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK10-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
|
||||
// CHECK10-NEXT: [[TMP5:%.*]] = load i32, ptr [[N]], align 4
|
||||
// CHECK10-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(ptr noundef nonnull align 8 dereferenceable(8) [[S]], i32 noundef signext [[TMP5]])
|
||||
// CHECK10-NEXT: [[TMP6:%.*]] = load i32, ptr [[A]], align 4
|
||||
// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], [[CALL]]
|
||||
// CHECK10-NEXT: store i32 [[ADD]], ptr [[A]], align 4
|
||||
// CHECK10-NEXT: ret void
|
||||
//
|
||||
//
|
||||
@ -1331,19 +1371,28 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3bari_l103
|
||||
// CHECK10-SAME: (i64 noundef [[A:%.*]], i64 noundef [[N:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK10-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK10-NEXT: entry:
|
||||
// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK10-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK10-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8
|
||||
// CHECK10-NEXT: store i64 [[N]], ptr [[N_ADDR]], align 8
|
||||
// CHECK10-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK10-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4
|
||||
// CHECK10-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP0]])
|
||||
// CHECK10-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
|
||||
// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
|
||||
// CHECK10-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 4
|
||||
// CHECK10-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK10-NEXT: [[A:%.*]] = alloca i32, align 4
|
||||
// CHECK10-NEXT: [[N:%.*]] = alloca i32, align 4
|
||||
// CHECK10-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
|
||||
// CHECK10-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK10-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK10-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
|
||||
// CHECK10-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 8
|
||||
// CHECK10-NEXT: store i32 [[TMP2]], ptr [[A]], align 4
|
||||
// CHECK10-NEXT: [[TMP3:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
|
||||
// CHECK10-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 8
|
||||
// CHECK10-NEXT: store i32 [[TMP4]], ptr [[N]], align 4
|
||||
// CHECK10-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 2
|
||||
// CHECK10-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK10-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
|
||||
// CHECK10-NEXT: [[TMP5:%.*]] = load i32, ptr [[N]], align 4
|
||||
// CHECK10-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP5]])
|
||||
// CHECK10-NEXT: [[TMP6:%.*]] = load i32, ptr [[A]], align 4
|
||||
// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], [[CALL]]
|
||||
// CHECK10-NEXT: store i32 [[ADD]], ptr [[A]], align 4
|
||||
// CHECK10-NEXT: ret void
|
||||
//
|
||||
//
|
||||
@ -1368,22 +1417,28 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l61
|
||||
// CHECK10-SAME: (i64 noundef [[DOTCAPTURE_EXPR_:%.*]], ptr noundef nonnull align 1 dereferenceable(4) [[DOTCAPTURE_EXPR_1:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK10-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK10-NEXT: entry:
|
||||
// CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca ptr, align 8
|
||||
// CHECK10-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK10-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
|
||||
// CHECK10-NEXT: [[DYN_PTR2:%.*]] = alloca ptr, align 8
|
||||
// CHECK10-NEXT: [[TMP:%.*]] = alloca ptr, align 8
|
||||
// CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
|
||||
// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8
|
||||
// CHECK10-NEXT: store ptr [[DOTCAPTURE_EXPR_1]], ptr [[DOTCAPTURE_EXPR__ADDR2]], align 8
|
||||
// CHECK10-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK10-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR__ADDR2]], align 8, !nonnull [[META11:![0-9]+]]
|
||||
// CHECK10-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 8
|
||||
// CHECK10-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
|
||||
// CHECK10-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META11]]
|
||||
// CHECK10-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [4 x i8], ptr [[TMP3]], i64 0, i64 0
|
||||
// CHECK10-NEXT: call void @__kmpc_push_num_threads_strict(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 2, ptr [[ARRAYDECAY]])
|
||||
// CHECK10-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK10-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK10-NEXT: [[TMP2:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 0
|
||||
// CHECK10-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 8
|
||||
// CHECK10-NEXT: store i32 [[TMP3]], ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
// CHECK10-NEXT: [[TMP4:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 1
|
||||
// CHECK10-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = load ptr, ptr [[TMP4]], align 8
|
||||
// CHECK10-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 2
|
||||
// CHECK10-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK10-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR2]], align 8
|
||||
// CHECK10-NEXT: store ptr [[DOTCAPTURE_EXPR_1]], ptr [[TMP]], align 8
|
||||
// CHECK10-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
// CHECK10-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META11:![0-9]+]]
|
||||
// CHECK10-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [4 x i8], ptr [[TMP6]], i64 0, i64 0
|
||||
// CHECK10-NEXT: call void @__kmpc_push_num_threads_strict(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP5]], i32 2, ptr [[ARRAYDECAY]])
|
||||
// CHECK10-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l61.omp_outlined)
|
||||
// CHECK10-NEXT: ret void
|
||||
//
|
||||
@ -1399,15 +1454,22 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l65
|
||||
// CHECK10-SAME: (i64 noundef [[DOTCAPTURE_EXPR_:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK10-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK10-NEXT: entry:
|
||||
// CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK10-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK10-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
|
||||
// CHECK10-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
|
||||
// CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
|
||||
// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8
|
||||
// CHECK10-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK10-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
|
||||
// CHECK10-NEXT: call void @__kmpc_push_num_threads_strict(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 1, ptr null)
|
||||
// CHECK10-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK10-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK10-NEXT: [[TMP2:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 0
|
||||
// CHECK10-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 8
|
||||
// CHECK10-NEXT: store i32 [[TMP3]], ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
// CHECK10-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 1
|
||||
// CHECK10-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK10-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
|
||||
// CHECK10-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
// CHECK10-NEXT: call void @__kmpc_push_num_threads_strict(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP4]], i32 1, ptr null)
|
||||
// CHECK10-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l65.omp_outlined)
|
||||
// CHECK10-NEXT: ret void
|
||||
//
|
||||
@ -1490,22 +1552,28 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l61
|
||||
// CHECK11-SAME: (i32 noundef [[DOTCAPTURE_EXPR_:%.*]], ptr noundef nonnull align 1 dereferenceable(4) [[DOTCAPTURE_EXPR_1:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK11-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK11-NEXT: entry:
|
||||
// CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[DYN_PTR2:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[TMP:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]])
|
||||
// CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
|
||||
// CHECK11-NEXT: store ptr [[DOTCAPTURE_EXPR_1]], ptr [[DOTCAPTURE_EXPR__ADDR2]], align 4
|
||||
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR__ADDR2]], align 4, !nonnull [[META12:![0-9]+]]
|
||||
// CHECK11-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 4
|
||||
// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META12]]
|
||||
// CHECK11-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [4 x i8], ptr [[TMP3]], i32 0, i32 0
|
||||
// CHECK11-NEXT: call void @__kmpc_push_num_threads_strict(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 2, ptr [[ARRAYDECAY]])
|
||||
// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 0
|
||||
// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
|
||||
// CHECK11-NEXT: store i32 [[TMP3]], ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
// CHECK11-NEXT: [[TMP4:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 1
|
||||
// CHECK11-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = load ptr, ptr [[TMP4]], align 4
|
||||
// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 2
|
||||
// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR2]], align 4
|
||||
// CHECK11-NEXT: store ptr [[DOTCAPTURE_EXPR_1]], ptr [[TMP]], align 4
|
||||
// CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
// CHECK11-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META12:![0-9]+]]
|
||||
// CHECK11-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [4 x i8], ptr [[TMP6]], i32 0, i32 0
|
||||
// CHECK11-NEXT: call void @__kmpc_push_num_threads_strict(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP5]], i32 2, ptr [[ARRAYDECAY]])
|
||||
// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l61.omp_outlined)
|
||||
// CHECK11-NEXT: ret void
|
||||
//
|
||||
@ -1521,15 +1589,22 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l65
|
||||
// CHECK11-SAME: (i32 noundef [[DOTCAPTURE_EXPR_:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK11-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK11-NEXT: entry:
|
||||
// CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
|
||||
// CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
|
||||
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
|
||||
// CHECK11-NEXT: call void @__kmpc_push_num_threads_strict(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 1, ptr null)
|
||||
// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 0
|
||||
// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
|
||||
// CHECK11-NEXT: store i32 [[TMP3]], ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 1
|
||||
// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
|
||||
// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
// CHECK11-NEXT: call void @__kmpc_push_num_threads_strict(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP4]], i32 1, ptr null)
|
||||
// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l65.omp_outlined)
|
||||
// CHECK11-NEXT: ret void
|
||||
//
|
||||
@ -1545,20 +1620,29 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3bari_l95
|
||||
// CHECK11-SAME: (i32 noundef [[A:%.*]], i32 noundef [[N:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK11-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK11-NEXT: entry:
|
||||
// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[A:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[N:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4
|
||||
// CHECK11-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
|
||||
// CHECK11-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
|
||||
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[CALL:%.*]] = call noundef i32 @_ZN2S12r1Ei(ptr noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP0]])
|
||||
// CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
|
||||
// CHECK11-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 4
|
||||
// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
|
||||
// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
|
||||
// CHECK11-NEXT: store i32 [[TMP2]], ptr [[A]], align 4
|
||||
// CHECK11-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
|
||||
// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4
|
||||
// CHECK11-NEXT: store i32 [[TMP4]], ptr [[N]], align 4
|
||||
// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 2
|
||||
// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
|
||||
// CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[N]], align 4
|
||||
// CHECK11-NEXT: [[CALL:%.*]] = call noundef i32 @_ZN2S12r1Ei(ptr noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP5]])
|
||||
// CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[A]], align 4
|
||||
// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], [[CALL]]
|
||||
// CHECK11-NEXT: store i32 [[ADD]], ptr [[A]], align 4
|
||||
// CHECK11-NEXT: ret void
|
||||
//
|
||||
//
|
||||
@ -1587,19 +1671,28 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3bari_l103
|
||||
// CHECK11-SAME: (i32 noundef [[A:%.*]], i32 noundef [[N:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK11-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK11-NEXT: entry:
|
||||
// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
|
||||
// CHECK11-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
|
||||
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[CALL:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP0]])
|
||||
// CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
|
||||
// CHECK11-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[A:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[N:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
|
||||
// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
|
||||
// CHECK11-NEXT: store i32 [[TMP2]], ptr [[A]], align 4
|
||||
// CHECK11-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
|
||||
// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4
|
||||
// CHECK11-NEXT: store i32 [[TMP4]], ptr [[N]], align 4
|
||||
// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 2
|
||||
// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
|
||||
// CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[N]], align 4
|
||||
// CHECK11-NEXT: [[CALL:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP5]])
|
||||
// CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[A]], align 4
|
||||
// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], [[CALL]]
|
||||
// CHECK11-NEXT: store i32 [[ADD]], ptr [[A]], align 4
|
||||
// CHECK11-NEXT: ret void
|
||||
//
|
||||
//
|
||||
@ -1691,20 +1784,29 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3bari_l95
|
||||
// CHECK12-SAME: (i32 noundef [[A:%.*]], i32 noundef [[N:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK12-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK12-NEXT: entry:
|
||||
// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK12-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK12-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK12-NEXT: [[A:%.*]] = alloca i32, align 4
|
||||
// CHECK12-NEXT: [[N:%.*]] = alloca i32, align 4
|
||||
// CHECK12-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 4
|
||||
// CHECK12-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4
|
||||
// CHECK12-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
|
||||
// CHECK12-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
|
||||
// CHECK12-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK12-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4
|
||||
// CHECK12-NEXT: [[CALL:%.*]] = call noundef i32 @_ZN2S12r1Ei(ptr noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP0]])
|
||||
// CHECK12-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
|
||||
// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
|
||||
// CHECK12-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 4
|
||||
// CHECK12-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK12-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK12-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
|
||||
// CHECK12-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
|
||||
// CHECK12-NEXT: store i32 [[TMP2]], ptr [[A]], align 4
|
||||
// CHECK12-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
|
||||
// CHECK12-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4
|
||||
// CHECK12-NEXT: store i32 [[TMP4]], ptr [[N]], align 4
|
||||
// CHECK12-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 2
|
||||
// CHECK12-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK12-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
|
||||
// CHECK12-NEXT: [[TMP5:%.*]] = load i32, ptr [[N]], align 4
|
||||
// CHECK12-NEXT: [[CALL:%.*]] = call noundef i32 @_ZN2S12r1Ei(ptr noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP5]])
|
||||
// CHECK12-NEXT: [[TMP6:%.*]] = load i32, ptr [[A]], align 4
|
||||
// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], [[CALL]]
|
||||
// CHECK12-NEXT: store i32 [[ADD]], ptr [[A]], align 4
|
||||
// CHECK12-NEXT: ret void
|
||||
//
|
||||
//
|
||||
@ -1733,19 +1835,28 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3bari_l103
|
||||
// CHECK12-SAME: (i32 noundef [[A:%.*]], i32 noundef [[N:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK12-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK12-NEXT: entry:
|
||||
// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK12-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK12-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
|
||||
// CHECK12-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
|
||||
// CHECK12-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK12-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4
|
||||
// CHECK12-NEXT: [[CALL:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP0]])
|
||||
// CHECK12-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
|
||||
// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
|
||||
// CHECK12-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 4
|
||||
// CHECK12-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK12-NEXT: [[A:%.*]] = alloca i32, align 4
|
||||
// CHECK12-NEXT: [[N:%.*]] = alloca i32, align 4
|
||||
// CHECK12-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 4
|
||||
// CHECK12-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK12-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK12-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
|
||||
// CHECK12-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
|
||||
// CHECK12-NEXT: store i32 [[TMP2]], ptr [[A]], align 4
|
||||
// CHECK12-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
|
||||
// CHECK12-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4
|
||||
// CHECK12-NEXT: store i32 [[TMP4]], ptr [[N]], align 4
|
||||
// CHECK12-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 2
|
||||
// CHECK12-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK12-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
|
||||
// CHECK12-NEXT: [[TMP5:%.*]] = load i32, ptr [[N]], align 4
|
||||
// CHECK12-NEXT: [[CALL:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP5]])
|
||||
// CHECK12-NEXT: [[TMP6:%.*]] = load i32, ptr [[A]], align 4
|
||||
// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], [[CALL]]
|
||||
// CHECK12-NEXT: store i32 [[ADD]], ptr [[A]], align 4
|
||||
// CHECK12-NEXT: ret void
|
||||
//
|
||||
//
|
||||
@ -1770,22 +1881,28 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l61
|
||||
// CHECK12-SAME: (i32 noundef [[DOTCAPTURE_EXPR_:%.*]], ptr noundef nonnull align 1 dereferenceable(4) [[DOTCAPTURE_EXPR_1:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK12-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK12-NEXT: entry:
|
||||
// CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca ptr, align 4
|
||||
// CHECK12-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK12-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
|
||||
// CHECK12-NEXT: [[DYN_PTR2:%.*]] = alloca ptr, align 4
|
||||
// CHECK12-NEXT: [[TMP:%.*]] = alloca ptr, align 4
|
||||
// CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
|
||||
// CHECK12-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
|
||||
// CHECK12-NEXT: store ptr [[DOTCAPTURE_EXPR_1]], ptr [[DOTCAPTURE_EXPR__ADDR2]], align 4
|
||||
// CHECK12-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK12-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR__ADDR2]], align 4, !nonnull [[META12:![0-9]+]]
|
||||
// CHECK12-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 4
|
||||
// CHECK12-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
|
||||
// CHECK12-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META12]]
|
||||
// CHECK12-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [4 x i8], ptr [[TMP3]], i32 0, i32 0
|
||||
// CHECK12-NEXT: call void @__kmpc_push_num_threads_strict(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 2, ptr [[ARRAYDECAY]])
|
||||
// CHECK12-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK12-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK12-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 0
|
||||
// CHECK12-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
|
||||
// CHECK12-NEXT: store i32 [[TMP3]], ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
// CHECK12-NEXT: [[TMP4:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 1
|
||||
// CHECK12-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = load ptr, ptr [[TMP4]], align 4
|
||||
// CHECK12-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 2
|
||||
// CHECK12-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK12-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR2]], align 4
|
||||
// CHECK12-NEXT: store ptr [[DOTCAPTURE_EXPR_1]], ptr [[TMP]], align 4
|
||||
// CHECK12-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
// CHECK12-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META12:![0-9]+]]
|
||||
// CHECK12-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [4 x i8], ptr [[TMP6]], i32 0, i32 0
|
||||
// CHECK12-NEXT: call void @__kmpc_push_num_threads_strict(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP5]], i32 2, ptr [[ARRAYDECAY]])
|
||||
// CHECK12-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l61.omp_outlined)
|
||||
// CHECK12-NEXT: ret void
|
||||
//
|
||||
@ -1801,15 +1918,22 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l65
|
||||
// CHECK12-SAME: (i32 noundef [[DOTCAPTURE_EXPR_:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK12-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK12-NEXT: entry:
|
||||
// CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK12-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK12-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
|
||||
// CHECK12-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 4
|
||||
// CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
|
||||
// CHECK12-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
|
||||
// CHECK12-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK12-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
|
||||
// CHECK12-NEXT: call void @__kmpc_push_num_threads_strict(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 1, ptr null)
|
||||
// CHECK12-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK12-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK12-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 0
|
||||
// CHECK12-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
|
||||
// CHECK12-NEXT: store i32 [[TMP3]], ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
// CHECK12-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 1
|
||||
// CHECK12-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK12-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
|
||||
// CHECK12-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
// CHECK12-NEXT: call void @__kmpc_push_num_threads_strict(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP4]], i32 1, ptr null)
|
||||
// CHECK12-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l65.omp_outlined)
|
||||
// CHECK12-NEXT: ret void
|
||||
//
|
||||
|
||||
@ -88,22 +88,16 @@ int foo(int n) {
|
||||
}
|
||||
// make sure that private variables are generated in all cases and that we use those instances for operations inside the
|
||||
// target region
|
||||
// TCHECK: define weak_odr protected void @__omp_offloading_{{.+}}(i{{[0-9]+}} noundef [[VLA:%.+]], i{{[0-9]+}} noundef [[VLA1:%.+]], i{{[0-9]+}} noundef [[VLA3:%.+]], ptr {{[^,]+}})
|
||||
// TCHECK: [[VLA_ADDR:%.+]] = alloca i{{[0-9]+}},
|
||||
// TCHECK: [[VLA_ADDR2:%.+]] = alloca i{{[0-9]+}},
|
||||
// TCHECK: [[VLA_ADDR4:%.+]] = alloca i{{[0-9]+}},
|
||||
// TCHECK: define weak_odr protected void @__omp_offloading_{{.+}}(ptr noalias noundef %__context)
|
||||
// TCHECK: [[DYN_PTR:%.+]] = alloca ptr
|
||||
// TCHECK: [[A:%.+]] = alloca i{{[0-9]+}},
|
||||
// TCHECK: [[B:%.+]] = alloca [10 x float],
|
||||
// TCHECK: [[SSTACK:%.+]] = alloca ptr,
|
||||
// TCHECK: [[C:%.+]] = alloca [5 x [10 x double]],
|
||||
// TCHECK: [[D:%.+]] = alloca [[TT]],
|
||||
// TCHECK: store i{{[0-9]+}} [[VLA]], ptr [[VLA_ADDR]],
|
||||
// TCHECK: store i{{[0-9]+}} [[VLA1]], ptr [[VLA_ADDR2]],
|
||||
// TCHECK: store i{{[0-9]+}} [[VLA3]], ptr [[VLA_ADDR4]],
|
||||
// TCHECK: [[VLA_ADDR_REF:%.+]] = load i{{[0-9]+}}, ptr [[VLA_ADDR]],
|
||||
// TCHECK: [[VLA_ADDR_REF2:%.+]] = load i{{[0-9]+}}, ptr [[VLA_ADDR2]],
|
||||
// TCHECK: [[VLA_ADDR_REF4:%.+]] = load i{{[0-9]+}}, ptr [[VLA_ADDR4]],
|
||||
// TCHECK: [[VLA_ADDR_REF:%.+]] = load i{{[0-9]+}}, ptr {{%.+}},
|
||||
// TCHECK: [[VLA_ADDR_REF2:%.+]] = load i{{[0-9]+}}, ptr {{%.+}},
|
||||
// TCHECK: [[VLA_ADDR_REF4:%.+]] = load i{{[0-9]+}}, ptr {{%.+}},
|
||||
// TCHECK: [[RET_STACK:%.+]] = call ptr @llvm.stacksave.p0()
|
||||
// TCHECK: store ptr [[RET_STACK]], ptr [[SSTACK]],
|
||||
// TCHECK: [[VLA5:%.+]] = alloca float, i{{[0-9]+}} [[VLA_ADDR_REF]],
|
||||
@ -212,19 +206,14 @@ struct S1 {
|
||||
return c[1][1] + (int)b;
|
||||
}
|
||||
|
||||
// TCHECK: define weak_odr protected void @__omp_offloading_{{.+}}(ptr noundef [[TH:%.+]], i{{[0-9]+}} noundef [[VLA:%.+]], i{{[0-9]+}} noundef [[VLA1:%.+]], ptr {{[^,]+}})
|
||||
// TCHECK: [[TH_ADDR:%.+]] = alloca ptr,
|
||||
// TCHECK: [[VLA_ADDR:%.+]] = alloca i{{[0-9]+}},
|
||||
// TCHECK: [[VLA_ADDR2:%.+]] = alloca i{{[0-9]+}},
|
||||
// TCHECK: define weak_odr protected void @__omp_offloading_{{.+}}(ptr noalias noundef %__context)
|
||||
// TCHECK: [[DYN_PTR:%.+]] = alloca ptr
|
||||
// TCHECK: [[B:%.+]] = alloca i{{[0-9]+}},
|
||||
// TCHECK: [[SSTACK:%.+]] = alloca ptr,
|
||||
// TCHECK: store ptr [[TH]], ptr [[TH_ADDR]],
|
||||
// TCHECK: store i{{[0-9]+}} [[VLA]], ptr [[VLA_ADDR]],
|
||||
// TCHECK: store i{{[0-9]+}} [[VLA1]], ptr [[VLA_ADDR2]],
|
||||
// TCHECK: [[TH_ADDR_REF:%.+]] = load ptr, ptr [[TH_ADDR]],
|
||||
// TCHECK: [[VLA_ADDR_REF:%.+]] = load i{{[0-9]+}}, ptr [[VLA_ADDR]],
|
||||
// TCHECK: [[VLA_ADDR_REF2:%.+]] = load i{{[0-9]+}}, ptr [[VLA_ADDR2]],
|
||||
// TCHECK: getelementptr inbounds i{{[0-9]+}}, ptr {{%.+}}, i32 0
|
||||
// TCHECK: [[TH_ADDR_REF:%.+]] = load ptr, ptr {{%.+}},
|
||||
// TCHECK: [[VLA_ADDR_REF:%.+]] = load i{{[0-9]+}}, ptr {{%.+}},
|
||||
// TCHECK: [[VLA_ADDR_REF2:%.+]] = load i{{[0-9]+}}, ptr {{%.+}},
|
||||
// TCHECK: [[RET_STACK:%.+]] = call ptr @llvm.stacksave.p0()
|
||||
// TCHECK: store ptr [[RET_STACK:%.+]], ptr [[SSTACK]],
|
||||
|
||||
|
||||
@ -638,46 +638,49 @@ int main() {
|
||||
//
|
||||
//
|
||||
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l44
|
||||
// CHECK9-SAME: (ptr noundef [[B:%.*]], ptr noundef [[A:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK9-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK9-NEXT: entry:
|
||||
// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 8
|
||||
// CHECK9-NEXT: [[DOTAFFS_ARR_ADDR:%.*]] = alloca [1 x [[STRUCT_KMP_TASK_AFFINITY_INFO_T:%.*]]], align 8
|
||||
// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]])
|
||||
// CHECK9-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
|
||||
// CHECK9-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8
|
||||
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 0
|
||||
// CHECK9-NEXT: store ptr [[B_ADDR]], ptr [[TMP1]], align 8
|
||||
// CHECK9-NEXT: [[TMP2:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[TMP0]], i32 1, i64 48, i64 8, ptr @.omp_task_entry.)
|
||||
// CHECK9-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x [[STRUCT_KMP_TASK_AFFINITY_INFO_T]]], ptr [[DOTAFFS_ARR_ADDR]], i64 0, i64 0
|
||||
// CHECK9-NEXT: [[TMP4:%.*]] = load ptr, ptr [[A_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds nuw i32, ptr [[TMP4]], i64 0
|
||||
// CHECK9-NEXT: [[TMP5:%.*]] = load ptr, ptr [[A_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds nuw i32, ptr [[TMP5]], i64 1023
|
||||
// CHECK9-NEXT: [[TMP6:%.*]] = getelementptr i32, ptr [[ARRAYIDX1]], i32 1
|
||||
// CHECK9-NEXT: [[TMP7:%.*]] = ptrtoaddr ptr [[TMP6]] to i64
|
||||
// CHECK9-NEXT: [[TMP8:%.*]] = ptrtoaddr ptr [[ARRAYIDX]] to i64
|
||||
// CHECK9-NEXT: [[TMP9:%.*]] = sub nuw i64 [[TMP7]], [[TMP8]]
|
||||
// CHECK9-NEXT: [[TMP10:%.*]] = getelementptr [[STRUCT_KMP_TASK_AFFINITY_INFO_T]], ptr [[TMP3]], i64 0
|
||||
// CHECK9-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_AFFINITY_INFO_T]], ptr [[TMP10]], i32 0, i32 0
|
||||
// CHECK9-NEXT: [[TMP12:%.*]] = ptrtoint ptr [[ARRAYIDX]] to i64
|
||||
// CHECK9-NEXT: store i64 [[TMP12]], ptr [[TMP11]], align 8
|
||||
// CHECK9-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_AFFINITY_INFO_T]], ptr [[TMP10]], i32 0, i32 1
|
||||
// CHECK9-NEXT: store i64 [[TMP9]], ptr [[TMP13]], align 8
|
||||
// CHECK9-NEXT: [[TMP14:%.*]] = call i32 @__kmpc_omp_reg_task_with_affinity(ptr @[[GLOB1]], i32 [[TMP0]], ptr [[TMP2]], i32 1, ptr [[TMP3]])
|
||||
// CHECK9-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP2]], i32 0, i32 0
|
||||
// CHECK9-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP15]], i32 0, i32 0
|
||||
// CHECK9-NEXT: [[TMP17:%.*]] = load ptr, ptr [[TMP16]], align 8
|
||||
// CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[TMP17]], ptr align 8 [[AGG_CAPTURED]], i64 8, i1 false)
|
||||
// CHECK9-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], ptr [[TMP2]], i32 0, i32 1
|
||||
// CHECK9-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T:%.*]], ptr [[TMP18]], i32 0, i32 0
|
||||
// CHECK9-NEXT: [[TMP20:%.*]] = load ptr, ptr [[A_ADDR]], align 8
|
||||
// CHECK9-NEXT: store ptr [[TMP20]], ptr [[TMP19]], align 8
|
||||
// CHECK9-NEXT: [[TMP21:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB1]], i32 [[TMP0]], ptr [[TMP2]])
|
||||
// CHECK9-NEXT: [[TMP22:%.*]] = call i32 @__kmpc_omp_taskwait(ptr @[[GLOB1]], i32 [[TMP0]])
|
||||
// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[B:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 0
|
||||
// CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 1
|
||||
// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 2
|
||||
// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
|
||||
// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 0
|
||||
// CHECK9-NEXT: store ptr [[B]], ptr [[TMP2]], align 8
|
||||
// CHECK9-NEXT: [[TMP3:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[TMP0]], i32 1, i64 48, i64 8, ptr @.omp_task_entry.)
|
||||
// CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x [[STRUCT_KMP_TASK_AFFINITY_INFO_T]]], ptr [[DOTAFFS_ARR_ADDR]], i64 0, i64 0
|
||||
// CHECK9-NEXT: [[TMP5:%.*]] = load ptr, ptr [[A]], align 8
|
||||
// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds nuw i32, ptr [[TMP5]], i64 0
|
||||
// CHECK9-NEXT: [[TMP6:%.*]] = load ptr, ptr [[A]], align 8
|
||||
// CHECK9-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds nuw i32, ptr [[TMP6]], i64 1023
|
||||
// CHECK9-NEXT: [[TMP7:%.*]] = getelementptr i32, ptr [[ARRAYIDX2]], i32 1
|
||||
// CHECK9-NEXT: [[TMP8:%.*]] = ptrtoaddr ptr [[TMP7]] to i64
|
||||
// CHECK9-NEXT: [[TMP9:%.*]] = ptrtoaddr ptr [[ARRAYIDX]] to i64
|
||||
// CHECK9-NEXT: [[TMP10:%.*]] = sub nuw i64 [[TMP8]], [[TMP9]]
|
||||
// CHECK9-NEXT: [[TMP11:%.*]] = getelementptr [[STRUCT_KMP_TASK_AFFINITY_INFO_T]], ptr [[TMP4]], i64 0
|
||||
// CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_AFFINITY_INFO_T]], ptr [[TMP11]], i32 0, i32 0
|
||||
// CHECK9-NEXT: [[TMP13:%.*]] = ptrtoint ptr [[ARRAYIDX]] to i64
|
||||
// CHECK9-NEXT: store i64 [[TMP13]], ptr [[TMP12]], align 8
|
||||
// CHECK9-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_AFFINITY_INFO_T]], ptr [[TMP11]], i32 0, i32 1
|
||||
// CHECK9-NEXT: store i64 [[TMP10]], ptr [[TMP14]], align 8
|
||||
// CHECK9-NEXT: [[TMP15:%.*]] = call i32 @__kmpc_omp_reg_task_with_affinity(ptr @[[GLOB1]], i32 [[TMP0]], ptr [[TMP3]], i32 1, ptr [[TMP4]])
|
||||
// CHECK9-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP3]], i32 0, i32 0
|
||||
// CHECK9-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP16]], i32 0, i32 0
|
||||
// CHECK9-NEXT: [[TMP18:%.*]] = load ptr, ptr [[TMP17]], align 8
|
||||
// CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[TMP18]], ptr align 8 [[AGG_CAPTURED]], i64 8, i1 false)
|
||||
// CHECK9-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], ptr [[TMP3]], i32 0, i32 1
|
||||
// CHECK9-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T:%.*]], ptr [[TMP19]], i32 0, i32 0
|
||||
// CHECK9-NEXT: [[TMP21:%.*]] = load ptr, ptr [[A]], align 8
|
||||
// CHECK9-NEXT: store ptr [[TMP21]], ptr [[TMP20]], align 8
|
||||
// CHECK9-NEXT: [[TMP22:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB1]], i32 [[TMP0]], ptr [[TMP3]])
|
||||
// CHECK9-NEXT: [[TMP23:%.*]] = call i32 @__kmpc_omp_taskwait(ptr @[[GLOB1]], i32 [[TMP0]])
|
||||
// CHECK9-NEXT: ret void
|
||||
//
|
||||
//
|
||||
@ -760,46 +763,49 @@ int main() {
|
||||
//
|
||||
//
|
||||
// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l44
|
||||
// CHECK11-SAME: (ptr noundef [[B:%.*]], ptr noundef [[A:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK11-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK11-NEXT: entry:
|
||||
// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 4
|
||||
// CHECK11-NEXT: [[DOTAFFS_ARR_ADDR:%.*]] = alloca [1 x [[STRUCT_KMP_TASK_AFFINITY_INFO_T:%.*]]], align 4
|
||||
// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]])
|
||||
// CHECK11-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4
|
||||
// CHECK11-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4
|
||||
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 0
|
||||
// CHECK11-NEXT: store ptr [[B_ADDR]], ptr [[TMP1]], align 4
|
||||
// CHECK11-NEXT: [[TMP2:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[TMP0]], i32 1, i32 24, i32 4, ptr @.omp_task_entry.)
|
||||
// CHECK11-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x [[STRUCT_KMP_TASK_AFFINITY_INFO_T]]], ptr [[DOTAFFS_ARR_ADDR]], i32 0, i32 0
|
||||
// CHECK11-NEXT: [[TMP4:%.*]] = load ptr, ptr [[A_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds nuw i32, ptr [[TMP4]], i32 0
|
||||
// CHECK11-NEXT: [[TMP5:%.*]] = load ptr, ptr [[A_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds nuw i32, ptr [[TMP5]], i32 1023
|
||||
// CHECK11-NEXT: [[TMP6:%.*]] = getelementptr i32, ptr [[ARRAYIDX1]], i32 1
|
||||
// CHECK11-NEXT: [[TMP7:%.*]] = ptrtoaddr ptr [[TMP6]] to i32
|
||||
// CHECK11-NEXT: [[TMP8:%.*]] = ptrtoaddr ptr [[ARRAYIDX]] to i32
|
||||
// CHECK11-NEXT: [[TMP9:%.*]] = sub nuw i32 [[TMP7]], [[TMP8]]
|
||||
// CHECK11-NEXT: [[TMP10:%.*]] = getelementptr [[STRUCT_KMP_TASK_AFFINITY_INFO_T]], ptr [[TMP3]], i32 0
|
||||
// CHECK11-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_AFFINITY_INFO_T]], ptr [[TMP10]], i32 0, i32 0
|
||||
// CHECK11-NEXT: [[TMP12:%.*]] = ptrtoint ptr [[ARRAYIDX]] to i32
|
||||
// CHECK11-NEXT: store i32 [[TMP12]], ptr [[TMP11]], align 4
|
||||
// CHECK11-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_AFFINITY_INFO_T]], ptr [[TMP10]], i32 0, i32 1
|
||||
// CHECK11-NEXT: store i32 [[TMP9]], ptr [[TMP13]], align 4
|
||||
// CHECK11-NEXT: [[TMP14:%.*]] = call i32 @__kmpc_omp_reg_task_with_affinity(ptr @[[GLOB1]], i32 [[TMP0]], ptr [[TMP2]], i32 1, ptr [[TMP3]])
|
||||
// CHECK11-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP2]], i32 0, i32 0
|
||||
// CHECK11-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP15]], i32 0, i32 0
|
||||
// CHECK11-NEXT: [[TMP17:%.*]] = load ptr, ptr [[TMP16]], align 4
|
||||
// CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP17]], ptr align 4 [[AGG_CAPTURED]], i32 4, i1 false)
|
||||
// CHECK11-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], ptr [[TMP2]], i32 0, i32 1
|
||||
// CHECK11-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T:%.*]], ptr [[TMP18]], i32 0, i32 0
|
||||
// CHECK11-NEXT: [[TMP20:%.*]] = load ptr, ptr [[A_ADDR]], align 4
|
||||
// CHECK11-NEXT: store ptr [[TMP20]], ptr [[TMP19]], align 4
|
||||
// CHECK11-NEXT: [[TMP21:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB1]], i32 [[TMP0]], ptr [[TMP2]])
|
||||
// CHECK11-NEXT: [[TMP22:%.*]] = call i32 @__kmpc_omp_taskwait(ptr @[[GLOB1]], i32 [[TMP0]])
|
||||
// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[B:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 0
|
||||
// CHECK11-NEXT: [[A:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 1
|
||||
// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 2
|
||||
// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
|
||||
// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 0
|
||||
// CHECK11-NEXT: store ptr [[B]], ptr [[TMP2]], align 4
|
||||
// CHECK11-NEXT: [[TMP3:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[TMP0]], i32 1, i32 24, i32 4, ptr @.omp_task_entry.)
|
||||
// CHECK11-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x [[STRUCT_KMP_TASK_AFFINITY_INFO_T]]], ptr [[DOTAFFS_ARR_ADDR]], i32 0, i32 0
|
||||
// CHECK11-NEXT: [[TMP5:%.*]] = load ptr, ptr [[A]], align 4
|
||||
// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds nuw i32, ptr [[TMP5]], i32 0
|
||||
// CHECK11-NEXT: [[TMP6:%.*]] = load ptr, ptr [[A]], align 4
|
||||
// CHECK11-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds nuw i32, ptr [[TMP6]], i32 1023
|
||||
// CHECK11-NEXT: [[TMP7:%.*]] = getelementptr i32, ptr [[ARRAYIDX2]], i32 1
|
||||
// CHECK11-NEXT: [[TMP8:%.*]] = ptrtoaddr ptr [[TMP7]] to i32
|
||||
// CHECK11-NEXT: [[TMP9:%.*]] = ptrtoaddr ptr [[ARRAYIDX]] to i32
|
||||
// CHECK11-NEXT: [[TMP10:%.*]] = sub nuw i32 [[TMP8]], [[TMP9]]
|
||||
// CHECK11-NEXT: [[TMP11:%.*]] = getelementptr [[STRUCT_KMP_TASK_AFFINITY_INFO_T]], ptr [[TMP4]], i32 0
|
||||
// CHECK11-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_AFFINITY_INFO_T]], ptr [[TMP11]], i32 0, i32 0
|
||||
// CHECK11-NEXT: [[TMP13:%.*]] = ptrtoint ptr [[ARRAYIDX]] to i32
|
||||
// CHECK11-NEXT: store i32 [[TMP13]], ptr [[TMP12]], align 4
|
||||
// CHECK11-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_AFFINITY_INFO_T]], ptr [[TMP11]], i32 0, i32 1
|
||||
// CHECK11-NEXT: store i32 [[TMP10]], ptr [[TMP14]], align 4
|
||||
// CHECK11-NEXT: [[TMP15:%.*]] = call i32 @__kmpc_omp_reg_task_with_affinity(ptr @[[GLOB1]], i32 [[TMP0]], ptr [[TMP3]], i32 1, ptr [[TMP4]])
|
||||
// CHECK11-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP3]], i32 0, i32 0
|
||||
// CHECK11-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP16]], i32 0, i32 0
|
||||
// CHECK11-NEXT: [[TMP18:%.*]] = load ptr, ptr [[TMP17]], align 4
|
||||
// CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP18]], ptr align 4 [[AGG_CAPTURED]], i32 4, i1 false)
|
||||
// CHECK11-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], ptr [[TMP3]], i32 0, i32 1
|
||||
// CHECK11-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T:%.*]], ptr [[TMP19]], i32 0, i32 0
|
||||
// CHECK11-NEXT: [[TMP21:%.*]] = load ptr, ptr [[A]], align 4
|
||||
// CHECK11-NEXT: store ptr [[TMP21]], ptr [[TMP20]], align 4
|
||||
// CHECK11-NEXT: [[TMP22:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB1]], i32 [[TMP0]], ptr [[TMP3]])
|
||||
// CHECK11-NEXT: [[TMP23:%.*]] = call i32 @__kmpc_omp_taskwait(ptr @[[GLOB1]], i32 [[TMP0]])
|
||||
// CHECK11-NEXT: ret void
|
||||
//
|
||||
//
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -3887,25 +3887,36 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103
|
||||
// CHECK9-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_1:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK9-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK9-NEXT: entry:
|
||||
// CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[AA:%.*]] = alloca i16, align 2
|
||||
// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
|
||||
// CHECK9-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
|
||||
// CHECK9-NEXT: [[DYN_PTR2:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2:[0-9]+]])
|
||||
// CHECK9-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8
|
||||
// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8
|
||||
// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], ptr [[DOTCAPTURE_EXPR__ADDR2]], align 8
|
||||
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
|
||||
// CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR2]], align 4
|
||||
// CHECK9-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
|
||||
// CHECK9-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2
|
||||
// CHECK9-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2
|
||||
// CHECK9-NEXT: [[TMP4:%.*]] = load i64, ptr [[AA_CASTED]], align 8
|
||||
// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.omp_outlined, i64 [[TMP4]])
|
||||
// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 0
|
||||
// CHECK9-NEXT: [[TMP3:%.*]] = load i16, ptr [[TMP2]], align 8
|
||||
// CHECK9-NEXT: store i16 [[TMP3]], ptr [[AA]], align 2
|
||||
// CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 1
|
||||
// CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 8
|
||||
// CHECK9-NEXT: store i32 [[TMP5]], ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
// CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 2
|
||||
// CHECK9-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 8
|
||||
// CHECK9-NEXT: store i32 [[TMP7]], ptr [[DOTCAPTURE_EXPR_1]], align 4
|
||||
// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 3
|
||||
// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR2]], align 8
|
||||
// CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
// CHECK9-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
|
||||
// CHECK9-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB2]], i32 [[TMP0]], i32 [[TMP8]], i32 [[TMP9]])
|
||||
// CHECK9-NEXT: [[TMP10:%.*]] = load i16, ptr [[AA]], align 2
|
||||
// CHECK9-NEXT: store i16 [[TMP10]], ptr [[AA_CASTED]], align 2
|
||||
// CHECK9-NEXT: [[TMP11:%.*]] = load i64, ptr [[AA_CASTED]], align 8
|
||||
// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.omp_outlined, i64 [[TMP11]])
|
||||
// CHECK9-NEXT: ret void
|
||||
//
|
||||
//
|
||||
@ -3972,17 +3983,24 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113
|
||||
// CHECK9-SAME: (i64 noundef [[AA:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK9-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK9-NEXT: entry:
|
||||
// CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[AA:%.*]] = alloca i16, align 2
|
||||
// CHECK9-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8
|
||||
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP0:%.*]] = load i16, ptr [[AA_ADDR]], align 2
|
||||
// CHECK9-NEXT: store i16 [[TMP0]], ptr [[AA_CASTED]], align 2
|
||||
// CHECK9-NEXT: [[TMP1:%.*]] = load i64, ptr [[AA_CASTED]], align 8
|
||||
// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113.omp_outlined, i64 [[TMP1]])
|
||||
// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
|
||||
// CHECK9-NEXT: [[TMP2:%.*]] = load i16, ptr [[TMP1]], align 8
|
||||
// CHECK9-NEXT: store i16 [[TMP2]], ptr [[AA]], align 2
|
||||
// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
|
||||
// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
|
||||
// CHECK9-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA]], align 2
|
||||
// CHECK9-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2
|
||||
// CHECK9-NEXT: [[TMP4:%.*]] = load i64, ptr [[AA_CASTED]], align 8
|
||||
// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113.omp_outlined, i64 [[TMP4]])
|
||||
// CHECK9-NEXT: ret void
|
||||
//
|
||||
//
|
||||
@ -4054,23 +4072,32 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120
|
||||
// CHECK9-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK9-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK9-NEXT: entry:
|
||||
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[A:%.*]] = alloca i32, align 4
|
||||
// CHECK9-NEXT: [[AA:%.*]] = alloca i16, align 2
|
||||
// CHECK9-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8
|
||||
// CHECK9-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8
|
||||
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
|
||||
// CHECK9-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4
|
||||
// CHECK9-NEXT: [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 8
|
||||
// CHECK9-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 2
|
||||
// CHECK9-NEXT: store i16 [[TMP2]], ptr [[AA_CASTED]], align 2
|
||||
// CHECK9-NEXT: [[TMP3:%.*]] = load i64, ptr [[AA_CASTED]], align 8
|
||||
// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120.omp_outlined, i64 [[TMP1]], i64 [[TMP3]])
|
||||
// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
|
||||
// CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 8
|
||||
// CHECK9-NEXT: store i32 [[TMP2]], ptr [[A]], align 4
|
||||
// CHECK9-NEXT: [[TMP3:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
|
||||
// CHECK9-NEXT: [[TMP4:%.*]] = load i16, ptr [[TMP3]], align 8
|
||||
// CHECK9-NEXT: store i16 [[TMP4]], ptr [[AA]], align 2
|
||||
// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 2
|
||||
// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
|
||||
// CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[A]], align 4
|
||||
// CHECK9-NEXT: store i32 [[TMP5]], ptr [[A_CASTED]], align 4
|
||||
// CHECK9-NEXT: [[TMP6:%.*]] = load i64, ptr [[A_CASTED]], align 8
|
||||
// CHECK9-NEXT: [[TMP7:%.*]] = load i16, ptr [[AA]], align 2
|
||||
// CHECK9-NEXT: store i16 [[TMP7]], ptr [[AA_CASTED]], align 2
|
||||
// CHECK9-NEXT: [[TMP8:%.*]] = load i64, ptr [[AA_CASTED]], align 8
|
||||
// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120.omp_outlined, i64 [[TMP6]], i64 [[TMP8]])
|
||||
// CHECK9-NEXT: ret void
|
||||
//
|
||||
//
|
||||
@ -4147,47 +4174,48 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145
|
||||
// CHECK9-SAME: (i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK9-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK9-NEXT: entry:
|
||||
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[A:%.*]] = alloca i32, align 4
|
||||
// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
|
||||
// CHECK9-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8
|
||||
// CHECK9-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
|
||||
// CHECK9-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8
|
||||
// CHECK9-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 8
|
||||
// CHECK9-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8
|
||||
// CHECK9-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8
|
||||
// CHECK9-NEXT: store i64 [[VLA3]], ptr [[VLA_ADDR4]], align 8
|
||||
// CHECK9-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 8
|
||||
// CHECK9-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8
|
||||
// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8
|
||||
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META19:![0-9]+]], !align [[META20:![0-9]+]]
|
||||
// CHECK9-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 8, !nonnull [[META19]], !align [[META20]]
|
||||
// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !nonnull [[META19]], !align [[META21:![0-9]+]]
|
||||
// CHECK9-NEXT: [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8
|
||||
// CHECK9-NEXT: [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR4]], align 8
|
||||
// CHECK9-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 8, !nonnull [[META19]], !align [[META21]]
|
||||
// CHECK9-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 8, !nonnull [[META19]], !align [[META21]]
|
||||
// CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4
|
||||
// CHECK9-NEXT: store i32 [[TMP8]], ptr [[A_CASTED]], align 4
|
||||
// CHECK9-NEXT: [[TMP9:%.*]] = load i64, ptr [[A_CASTED]], align 8
|
||||
// CHECK9-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
|
||||
// CHECK9-NEXT: store i32 [[TMP10]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 4
|
||||
// CHECK9-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED]], align 8
|
||||
// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 10, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145.omp_outlined, i64 [[TMP9]], ptr [[TMP0]], i64 [[TMP1]], ptr [[TMP2]], ptr [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], ptr [[TMP6]], ptr [[TMP7]], i64 [[TMP11]])
|
||||
// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
|
||||
// CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 8
|
||||
// CHECK9-NEXT: store i32 [[TMP2]], ptr [[A]], align 4
|
||||
// CHECK9-NEXT: [[TMP3:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
|
||||
// CHECK9-NEXT: [[B:%.*]] = load ptr, ptr [[TMP3]], align 8
|
||||
// CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 2
|
||||
// CHECK9-NEXT: [[TMP5:%.*]] = load i64, ptr [[TMP4]], align 8
|
||||
// CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 3
|
||||
// CHECK9-NEXT: [[BN:%.*]] = load ptr, ptr [[TMP6]], align 8
|
||||
// CHECK9-NEXT: [[TMP7:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 4
|
||||
// CHECK9-NEXT: [[C:%.*]] = load ptr, ptr [[TMP7]], align 8
|
||||
// CHECK9-NEXT: [[TMP8:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 5
|
||||
// CHECK9-NEXT: [[TMP9:%.*]] = load i64, ptr [[TMP8]], align 8
|
||||
// CHECK9-NEXT: [[TMP10:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 6
|
||||
// CHECK9-NEXT: [[TMP11:%.*]] = load i64, ptr [[TMP10]], align 8
|
||||
// CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 7
|
||||
// CHECK9-NEXT: [[CN:%.*]] = load ptr, ptr [[TMP12]], align 8
|
||||
// CHECK9-NEXT: [[TMP13:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 8
|
||||
// CHECK9-NEXT: [[D:%.*]] = load ptr, ptr [[TMP13]], align 8
|
||||
// CHECK9-NEXT: [[TMP14:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 9
|
||||
// CHECK9-NEXT: [[TMP15:%.*]] = load i32, ptr [[TMP14]], align 8
|
||||
// CHECK9-NEXT: store i32 [[TMP15]], ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 10
|
||||
// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
|
||||
// CHECK9-NEXT: [[TMP16:%.*]] = load i32, ptr [[A]], align 4
|
||||
// CHECK9-NEXT: store i32 [[TMP16]], ptr [[A_CASTED]], align 4
|
||||
// CHECK9-NEXT: [[TMP17:%.*]] = load i64, ptr [[A_CASTED]], align 8
|
||||
// CHECK9-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
// CHECK9-NEXT: store i32 [[TMP18]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 4
|
||||
// CHECK9-NEXT: [[TMP19:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED]], align 8
|
||||
// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 10, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145.omp_outlined, i64 [[TMP17]], ptr [[B]], i64 [[TMP5]], ptr [[BN]], ptr [[C]], i64 [[TMP9]], i64 [[TMP11]], ptr [[CN]], ptr [[D]], i64 [[TMP19]])
|
||||
// CHECK9-NEXT: ret void
|
||||
//
|
||||
//
|
||||
@ -4225,10 +4253,10 @@ int bar(int n){
|
||||
// CHECK9-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 8
|
||||
// CHECK9-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8
|
||||
// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META19]], !align [[META20]]
|
||||
// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META19:![0-9]+]], !align [[META20:![0-9]+]]
|
||||
// CHECK9-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 8, !nonnull [[META19]], !align [[META20]]
|
||||
// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !nonnull [[META19]], !align [[META21]]
|
||||
// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !nonnull [[META19]], !align [[META21:![0-9]+]]
|
||||
// CHECK9-NEXT: [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8
|
||||
// CHECK9-NEXT: [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR4]], align 8
|
||||
// CHECK9-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 8, !nonnull [[META19]], !align [[META21]]
|
||||
@ -4334,38 +4362,50 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200
|
||||
// CHECK9-SAME: (i64 noundef [[N:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK9-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK9-NEXT: entry:
|
||||
// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[N:%.*]] = alloca i32, align 4
|
||||
// CHECK9-NEXT: [[A:%.*]] = alloca i32, align 4
|
||||
// CHECK9-NEXT: [[AA:%.*]] = alloca i16, align 2
|
||||
// CHECK9-NEXT: [[AAA:%.*]] = alloca i8, align 1
|
||||
// CHECK9-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: store i64 [[N]], ptr [[N_ADDR]], align 8
|
||||
// CHECK9-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8
|
||||
// CHECK9-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8
|
||||
// CHECK9-NEXT: store i64 [[AAA]], ptr [[AAA_ADDR]], align 8
|
||||
// CHECK9-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
|
||||
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META19]], !align [[META20]]
|
||||
// CHECK9-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
|
||||
// CHECK9-NEXT: store i32 [[TMP1]], ptr [[N_CASTED]], align 4
|
||||
// CHECK9-NEXT: [[TMP2:%.*]] = load i64, ptr [[N_CASTED]], align 8
|
||||
// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[A_ADDR]], align 4
|
||||
// CHECK9-NEXT: store i32 [[TMP3]], ptr [[A_CASTED]], align 4
|
||||
// CHECK9-NEXT: [[TMP4:%.*]] = load i64, ptr [[A_CASTED]], align 8
|
||||
// CHECK9-NEXT: [[TMP5:%.*]] = load i16, ptr [[AA_ADDR]], align 2
|
||||
// CHECK9-NEXT: store i16 [[TMP5]], ptr [[AA_CASTED]], align 2
|
||||
// CHECK9-NEXT: [[TMP6:%.*]] = load i64, ptr [[AA_CASTED]], align 8
|
||||
// CHECK9-NEXT: [[TMP7:%.*]] = load i8, ptr [[AAA_ADDR]], align 1
|
||||
// CHECK9-NEXT: store i8 [[TMP7]], ptr [[AAA_CASTED]], align 1
|
||||
// CHECK9-NEXT: [[TMP8:%.*]] = load i64, ptr [[AAA_CASTED]], align 8
|
||||
// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200.omp_outlined, i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP8]], ptr [[TMP0]])
|
||||
// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
|
||||
// CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 8
|
||||
// CHECK9-NEXT: store i32 [[TMP2]], ptr [[N]], align 4
|
||||
// CHECK9-NEXT: [[TMP3:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
|
||||
// CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 8
|
||||
// CHECK9-NEXT: store i32 [[TMP4]], ptr [[A]], align 4
|
||||
// CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 2
|
||||
// CHECK9-NEXT: [[TMP6:%.*]] = load i16, ptr [[TMP5]], align 8
|
||||
// CHECK9-NEXT: store i16 [[TMP6]], ptr [[AA]], align 2
|
||||
// CHECK9-NEXT: [[TMP7:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 3
|
||||
// CHECK9-NEXT: [[TMP8:%.*]] = load i8, ptr [[TMP7]], align 8
|
||||
// CHECK9-NEXT: store i8 [[TMP8]], ptr [[AAA]], align 1
|
||||
// CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 4
|
||||
// CHECK9-NEXT: [[B:%.*]] = load ptr, ptr [[TMP9]], align 8
|
||||
// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 5
|
||||
// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
|
||||
// CHECK9-NEXT: [[TMP10:%.*]] = load i32, ptr [[N]], align 4
|
||||
// CHECK9-NEXT: store i32 [[TMP10]], ptr [[N_CASTED]], align 4
|
||||
// CHECK9-NEXT: [[TMP11:%.*]] = load i64, ptr [[N_CASTED]], align 8
|
||||
// CHECK9-NEXT: [[TMP12:%.*]] = load i32, ptr [[A]], align 4
|
||||
// CHECK9-NEXT: store i32 [[TMP12]], ptr [[A_CASTED]], align 4
|
||||
// CHECK9-NEXT: [[TMP13:%.*]] = load i64, ptr [[A_CASTED]], align 8
|
||||
// CHECK9-NEXT: [[TMP14:%.*]] = load i16, ptr [[AA]], align 2
|
||||
// CHECK9-NEXT: store i16 [[TMP14]], ptr [[AA_CASTED]], align 2
|
||||
// CHECK9-NEXT: [[TMP15:%.*]] = load i64, ptr [[AA_CASTED]], align 8
|
||||
// CHECK9-NEXT: [[TMP16:%.*]] = load i8, ptr [[AAA]], align 1
|
||||
// CHECK9-NEXT: store i8 [[TMP16]], ptr [[AAA_CASTED]], align 1
|
||||
// CHECK9-NEXT: [[TMP17:%.*]] = load i64, ptr [[AAA_CASTED]], align 8
|
||||
// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200.omp_outlined, i64 [[TMP11]], i64 [[TMP13]], i64 [[TMP15]], i64 [[TMP17]], ptr [[B]])
|
||||
// CHECK9-NEXT: ret void
|
||||
//
|
||||
//
|
||||
@ -4490,29 +4530,32 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218
|
||||
// CHECK9-SAME: (ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK9-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK9-NEXT: entry:
|
||||
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[B:%.*]] = alloca i32, align 4
|
||||
// CHECK9-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
|
||||
// CHECK9-NEXT: store i64 [[B]], ptr [[B_ADDR]], align 8
|
||||
// CHECK9-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8
|
||||
// CHECK9-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8
|
||||
// CHECK9-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8
|
||||
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8
|
||||
// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !nonnull [[META19]], !align [[META25:![0-9]+]]
|
||||
// CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[B_ADDR]], align 4
|
||||
// CHECK9-NEXT: store i32 [[TMP4]], ptr [[B_CASTED]], align 4
|
||||
// CHECK9-NEXT: [[TMP5:%.*]] = load i64, ptr [[B_CASTED]], align 8
|
||||
// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218.omp_outlined, ptr [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], ptr [[TMP3]])
|
||||
// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
|
||||
// CHECK9-NEXT: [[THIS:%.*]] = load ptr, ptr [[TMP1]], align 8
|
||||
// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
|
||||
// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 8
|
||||
// CHECK9-NEXT: store i32 [[TMP3]], ptr [[B]], align 4
|
||||
// CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 2
|
||||
// CHECK9-NEXT: [[TMP5:%.*]] = load i64, ptr [[TMP4]], align 8
|
||||
// CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 3
|
||||
// CHECK9-NEXT: [[TMP7:%.*]] = load i64, ptr [[TMP6]], align 8
|
||||
// CHECK9-NEXT: [[TMP8:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 4
|
||||
// CHECK9-NEXT: [[C:%.*]] = load ptr, ptr [[TMP8]], align 8
|
||||
// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 5
|
||||
// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
|
||||
// CHECK9-NEXT: [[TMP9:%.*]] = load i32, ptr [[B]], align 4
|
||||
// CHECK9-NEXT: store i32 [[TMP9]], ptr [[B_CASTED]], align 4
|
||||
// CHECK9-NEXT: [[TMP10:%.*]] = load i64, ptr [[B_CASTED]], align 8
|
||||
// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218.omp_outlined, ptr [[THIS]], i64 [[TMP10]], i64 [[TMP5]], i64 [[TMP7]], ptr [[C]])
|
||||
// CHECK9-NEXT: ret void
|
||||
//
|
||||
//
|
||||
@ -4543,7 +4586,7 @@ int bar(int n){
|
||||
// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8
|
||||
// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !nonnull [[META19]], !align [[META25]]
|
||||
// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !nonnull [[META19]], !align [[META25:![0-9]+]]
|
||||
// CHECK9-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
|
||||
// CHECK9-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4
|
||||
// CHECK9-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
|
||||
@ -4605,26 +4648,34 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183
|
||||
// CHECK9-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK9-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK9-NEXT: entry:
|
||||
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[A:%.*]] = alloca i32, align 4
|
||||
// CHECK9-NEXT: [[AA:%.*]] = alloca i16, align 2
|
||||
// CHECK9-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8
|
||||
// CHECK9-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8
|
||||
// CHECK9-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
|
||||
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META19]], !align [[META20]]
|
||||
// CHECK9-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
|
||||
// CHECK9-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4
|
||||
// CHECK9-NEXT: [[TMP2:%.*]] = load i64, ptr [[A_CASTED]], align 8
|
||||
// CHECK9-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2
|
||||
// CHECK9-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2
|
||||
// CHECK9-NEXT: [[TMP4:%.*]] = load i64, ptr [[AA_CASTED]], align 8
|
||||
// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183.omp_outlined, i64 [[TMP2]], i64 [[TMP4]], ptr [[TMP0]])
|
||||
// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
|
||||
// CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 8
|
||||
// CHECK9-NEXT: store i32 [[TMP2]], ptr [[A]], align 4
|
||||
// CHECK9-NEXT: [[TMP3:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
|
||||
// CHECK9-NEXT: [[TMP4:%.*]] = load i16, ptr [[TMP3]], align 8
|
||||
// CHECK9-NEXT: store i16 [[TMP4]], ptr [[AA]], align 2
|
||||
// CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 2
|
||||
// CHECK9-NEXT: [[B:%.*]] = load ptr, ptr [[TMP5]], align 8
|
||||
// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 3
|
||||
// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
|
||||
// CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[A]], align 4
|
||||
// CHECK9-NEXT: store i32 [[TMP6]], ptr [[A_CASTED]], align 4
|
||||
// CHECK9-NEXT: [[TMP7:%.*]] = load i64, ptr [[A_CASTED]], align 8
|
||||
// CHECK9-NEXT: [[TMP8:%.*]] = load i16, ptr [[AA]], align 2
|
||||
// CHECK9-NEXT: store i16 [[TMP8]], ptr [[AA_CASTED]], align 2
|
||||
// CHECK9-NEXT: [[TMP9:%.*]] = load i64, ptr [[AA_CASTED]], align 8
|
||||
// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183.omp_outlined, i64 [[TMP7]], i64 [[TMP9]], ptr [[B]])
|
||||
// CHECK9-NEXT: ret void
|
||||
//
|
||||
//
|
||||
@ -4708,25 +4759,36 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103
|
||||
// CHECK11-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]], i32 noundef [[DOTCAPTURE_EXPR_1:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK11-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK11-NEXT: entry:
|
||||
// CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[AA:%.*]] = alloca i16, align 2
|
||||
// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[DYN_PTR2:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2:[0-9]+]])
|
||||
// CHECK11-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4
|
||||
// CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
|
||||
// CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], ptr [[DOTCAPTURE_EXPR__ADDR2]], align 4
|
||||
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR2]], align 4
|
||||
// CHECK11-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
|
||||
// CHECK11-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2
|
||||
// CHECK11-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2
|
||||
// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[AA_CASTED]], align 4
|
||||
// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.omp_outlined, i32 [[TMP4]])
|
||||
// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 0
|
||||
// CHECK11-NEXT: [[TMP3:%.*]] = load i16, ptr [[TMP2]], align 4
|
||||
// CHECK11-NEXT: store i16 [[TMP3]], ptr [[AA]], align 2
|
||||
// CHECK11-NEXT: [[TMP4:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 1
|
||||
// CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
|
||||
// CHECK11-NEXT: store i32 [[TMP5]], ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
// CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 2
|
||||
// CHECK11-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4
|
||||
// CHECK11-NEXT: store i32 [[TMP7]], ptr [[DOTCAPTURE_EXPR_1]], align 4
|
||||
// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 3
|
||||
// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR2]], align 4
|
||||
// CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
// CHECK11-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
|
||||
// CHECK11-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB2]], i32 [[TMP0]], i32 [[TMP8]], i32 [[TMP9]])
|
||||
// CHECK11-NEXT: [[TMP10:%.*]] = load i16, ptr [[AA]], align 2
|
||||
// CHECK11-NEXT: store i16 [[TMP10]], ptr [[AA_CASTED]], align 2
|
||||
// CHECK11-NEXT: [[TMP11:%.*]] = load i32, ptr [[AA_CASTED]], align 4
|
||||
// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.omp_outlined, i32 [[TMP11]])
|
||||
// CHECK11-NEXT: ret void
|
||||
//
|
||||
//
|
||||
@ -4793,17 +4855,24 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113
|
||||
// CHECK11-SAME: (i32 noundef [[AA:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK11-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK11-NEXT: entry:
|
||||
// CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[AA:%.*]] = alloca i16, align 2
|
||||
// CHECK11-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4
|
||||
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP0:%.*]] = load i16, ptr [[AA_ADDR]], align 2
|
||||
// CHECK11-NEXT: store i16 [[TMP0]], ptr [[AA_CASTED]], align 2
|
||||
// CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[AA_CASTED]], align 4
|
||||
// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113.omp_outlined, i32 [[TMP1]])
|
||||
// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
|
||||
// CHECK11-NEXT: [[TMP2:%.*]] = load i16, ptr [[TMP1]], align 4
|
||||
// CHECK11-NEXT: store i16 [[TMP2]], ptr [[AA]], align 2
|
||||
// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
|
||||
// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
|
||||
// CHECK11-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA]], align 2
|
||||
// CHECK11-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2
|
||||
// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[AA_CASTED]], align 4
|
||||
// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113.omp_outlined, i32 [[TMP4]])
|
||||
// CHECK11-NEXT: ret void
|
||||
//
|
||||
//
|
||||
@ -4875,23 +4944,32 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120
|
||||
// CHECK11-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK11-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK11-NEXT: entry:
|
||||
// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[A:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[AA:%.*]] = alloca i16, align 2
|
||||
// CHECK11-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
|
||||
// CHECK11-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4
|
||||
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
|
||||
// CHECK11-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4
|
||||
// CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 4
|
||||
// CHECK11-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 2
|
||||
// CHECK11-NEXT: store i16 [[TMP2]], ptr [[AA_CASTED]], align 2
|
||||
// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[AA_CASTED]], align 4
|
||||
// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120.omp_outlined, i32 [[TMP1]], i32 [[TMP3]])
|
||||
// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
|
||||
// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
|
||||
// CHECK11-NEXT: store i32 [[TMP2]], ptr [[A]], align 4
|
||||
// CHECK11-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
|
||||
// CHECK11-NEXT: [[TMP4:%.*]] = load i16, ptr [[TMP3]], align 4
|
||||
// CHECK11-NEXT: store i16 [[TMP4]], ptr [[AA]], align 2
|
||||
// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 2
|
||||
// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
|
||||
// CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[A]], align 4
|
||||
// CHECK11-NEXT: store i32 [[TMP5]], ptr [[A_CASTED]], align 4
|
||||
// CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[A_CASTED]], align 4
|
||||
// CHECK11-NEXT: [[TMP7:%.*]] = load i16, ptr [[AA]], align 2
|
||||
// CHECK11-NEXT: store i16 [[TMP7]], ptr [[AA_CASTED]], align 2
|
||||
// CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[AA_CASTED]], align 4
|
||||
// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120.omp_outlined, i32 [[TMP6]], i32 [[TMP8]])
|
||||
// CHECK11-NEXT: ret void
|
||||
//
|
||||
//
|
||||
@ -4968,47 +5046,48 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145
|
||||
// CHECK11-SAME: (i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK11-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK11-NEXT: entry:
|
||||
// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[A:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
|
||||
// CHECK11-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4
|
||||
// CHECK11-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 4
|
||||
// CHECK11-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 4
|
||||
// CHECK11-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4
|
||||
// CHECK11-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4
|
||||
// CHECK11-NEXT: store i32 [[VLA3]], ptr [[VLA_ADDR4]], align 4
|
||||
// CHECK11-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 4
|
||||
// CHECK11-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4
|
||||
// CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
|
||||
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4, !nonnull [[META20:![0-9]+]], !align [[META21:![0-9]+]]
|
||||
// CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 4, !nonnull [[META20]], !align [[META21]]
|
||||
// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4, !nonnull [[META20]], !align [[META21]]
|
||||
// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4
|
||||
// CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[VLA_ADDR4]], align 4
|
||||
// CHECK11-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 4, !nonnull [[META20]], !align [[META21]]
|
||||
// CHECK11-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 4, !nonnull [[META20]], !align [[META21]]
|
||||
// CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4
|
||||
// CHECK11-NEXT: store i32 [[TMP8]], ptr [[A_CASTED]], align 4
|
||||
// CHECK11-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_CASTED]], align 4
|
||||
// CHECK11-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
|
||||
// CHECK11-NEXT: store i32 [[TMP10]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 4
|
||||
// CHECK11-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__CASTED]], align 4
|
||||
// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 10, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145.omp_outlined, i32 [[TMP9]], ptr [[TMP0]], i32 [[TMP1]], ptr [[TMP2]], ptr [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], ptr [[TMP6]], ptr [[TMP7]], i32 [[TMP11]])
|
||||
// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
|
||||
// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
|
||||
// CHECK11-NEXT: store i32 [[TMP2]], ptr [[A]], align 4
|
||||
// CHECK11-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
|
||||
// CHECK11-NEXT: [[B:%.*]] = load ptr, ptr [[TMP3]], align 4
|
||||
// CHECK11-NEXT: [[TMP4:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 2
|
||||
// CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
|
||||
// CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 3
|
||||
// CHECK11-NEXT: [[BN:%.*]] = load ptr, ptr [[TMP6]], align 4
|
||||
// CHECK11-NEXT: [[TMP7:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 4
|
||||
// CHECK11-NEXT: [[C:%.*]] = load ptr, ptr [[TMP7]], align 4
|
||||
// CHECK11-NEXT: [[TMP8:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 5
|
||||
// CHECK11-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP8]], align 4
|
||||
// CHECK11-NEXT: [[TMP10:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 6
|
||||
// CHECK11-NEXT: [[TMP11:%.*]] = load i32, ptr [[TMP10]], align 4
|
||||
// CHECK11-NEXT: [[TMP12:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 7
|
||||
// CHECK11-NEXT: [[CN:%.*]] = load ptr, ptr [[TMP12]], align 4
|
||||
// CHECK11-NEXT: [[TMP13:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 8
|
||||
// CHECK11-NEXT: [[D:%.*]] = load ptr, ptr [[TMP13]], align 4
|
||||
// CHECK11-NEXT: [[TMP14:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 9
|
||||
// CHECK11-NEXT: [[TMP15:%.*]] = load i32, ptr [[TMP14]], align 4
|
||||
// CHECK11-NEXT: store i32 [[TMP15]], ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 10
|
||||
// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
|
||||
// CHECK11-NEXT: [[TMP16:%.*]] = load i32, ptr [[A]], align 4
|
||||
// CHECK11-NEXT: store i32 [[TMP16]], ptr [[A_CASTED]], align 4
|
||||
// CHECK11-NEXT: [[TMP17:%.*]] = load i32, ptr [[A_CASTED]], align 4
|
||||
// CHECK11-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
// CHECK11-NEXT: store i32 [[TMP18]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 4
|
||||
// CHECK11-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__CASTED]], align 4
|
||||
// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 10, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145.omp_outlined, i32 [[TMP17]], ptr [[B]], i32 [[TMP5]], ptr [[BN]], ptr [[C]], i32 [[TMP9]], i32 [[TMP11]], ptr [[CN]], ptr [[D]], i32 [[TMP19]])
|
||||
// CHECK11-NEXT: ret void
|
||||
//
|
||||
//
|
||||
@ -5046,7 +5125,7 @@ int bar(int n){
|
||||
// CHECK11-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 4
|
||||
// CHECK11-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4
|
||||
// CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4, !nonnull [[META20]], !align [[META21]]
|
||||
// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4, !nonnull [[META20:![0-9]+]], !align [[META21:![0-9]+]]
|
||||
// CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 4, !nonnull [[META20]], !align [[META21]]
|
||||
// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4, !nonnull [[META20]], !align [[META21]]
|
||||
@ -5155,38 +5234,50 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200
|
||||
// CHECK11-SAME: (i32 noundef [[N:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK11-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK11-NEXT: entry:
|
||||
// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[N:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[A:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[AA:%.*]] = alloca i16, align 2
|
||||
// CHECK11-NEXT: [[AAA:%.*]] = alloca i8, align 1
|
||||
// CHECK11-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
|
||||
// CHECK11-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
|
||||
// CHECK11-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4
|
||||
// CHECK11-NEXT: store i32 [[AAA]], ptr [[AAA_ADDR]], align 4
|
||||
// CHECK11-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4
|
||||
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4, !nonnull [[META20]], !align [[META21]]
|
||||
// CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
|
||||
// CHECK11-NEXT: store i32 [[TMP1]], ptr [[N_CASTED]], align 4
|
||||
// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_CASTED]], align 4
|
||||
// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[A_ADDR]], align 4
|
||||
// CHECK11-NEXT: store i32 [[TMP3]], ptr [[A_CASTED]], align 4
|
||||
// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[A_CASTED]], align 4
|
||||
// CHECK11-NEXT: [[TMP5:%.*]] = load i16, ptr [[AA_ADDR]], align 2
|
||||
// CHECK11-NEXT: store i16 [[TMP5]], ptr [[AA_CASTED]], align 2
|
||||
// CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[AA_CASTED]], align 4
|
||||
// CHECK11-NEXT: [[TMP7:%.*]] = load i8, ptr [[AAA_ADDR]], align 1
|
||||
// CHECK11-NEXT: store i8 [[TMP7]], ptr [[AAA_CASTED]], align 1
|
||||
// CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[AAA_CASTED]], align 4
|
||||
// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200.omp_outlined, i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP8]], ptr [[TMP0]])
|
||||
// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
|
||||
// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
|
||||
// CHECK11-NEXT: store i32 [[TMP2]], ptr [[N]], align 4
|
||||
// CHECK11-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
|
||||
// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4
|
||||
// CHECK11-NEXT: store i32 [[TMP4]], ptr [[A]], align 4
|
||||
// CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 2
|
||||
// CHECK11-NEXT: [[TMP6:%.*]] = load i16, ptr [[TMP5]], align 4
|
||||
// CHECK11-NEXT: store i16 [[TMP6]], ptr [[AA]], align 2
|
||||
// CHECK11-NEXT: [[TMP7:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 3
|
||||
// CHECK11-NEXT: [[TMP8:%.*]] = load i8, ptr [[TMP7]], align 4
|
||||
// CHECK11-NEXT: store i8 [[TMP8]], ptr [[AAA]], align 1
|
||||
// CHECK11-NEXT: [[TMP9:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 4
|
||||
// CHECK11-NEXT: [[B:%.*]] = load ptr, ptr [[TMP9]], align 4
|
||||
// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 5
|
||||
// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
|
||||
// CHECK11-NEXT: [[TMP10:%.*]] = load i32, ptr [[N]], align 4
|
||||
// CHECK11-NEXT: store i32 [[TMP10]], ptr [[N_CASTED]], align 4
|
||||
// CHECK11-NEXT: [[TMP11:%.*]] = load i32, ptr [[N_CASTED]], align 4
|
||||
// CHECK11-NEXT: [[TMP12:%.*]] = load i32, ptr [[A]], align 4
|
||||
// CHECK11-NEXT: store i32 [[TMP12]], ptr [[A_CASTED]], align 4
|
||||
// CHECK11-NEXT: [[TMP13:%.*]] = load i32, ptr [[A_CASTED]], align 4
|
||||
// CHECK11-NEXT: [[TMP14:%.*]] = load i16, ptr [[AA]], align 2
|
||||
// CHECK11-NEXT: store i16 [[TMP14]], ptr [[AA_CASTED]], align 2
|
||||
// CHECK11-NEXT: [[TMP15:%.*]] = load i32, ptr [[AA_CASTED]], align 4
|
||||
// CHECK11-NEXT: [[TMP16:%.*]] = load i8, ptr [[AAA]], align 1
|
||||
// CHECK11-NEXT: store i8 [[TMP16]], ptr [[AAA_CASTED]], align 1
|
||||
// CHECK11-NEXT: [[TMP17:%.*]] = load i32, ptr [[AAA_CASTED]], align 4
|
||||
// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200.omp_outlined, i32 [[TMP11]], i32 [[TMP13]], i32 [[TMP15]], i32 [[TMP17]], ptr [[B]])
|
||||
// CHECK11-NEXT: ret void
|
||||
//
|
||||
//
|
||||
@ -5311,29 +5402,32 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218
|
||||
// CHECK11-SAME: (ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK11-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK11-NEXT: entry:
|
||||
// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[B:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
|
||||
// CHECK11-NEXT: store i32 [[B]], ptr [[B_ADDR]], align 4
|
||||
// CHECK11-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 4
|
||||
// CHECK11-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4
|
||||
// CHECK11-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4
|
||||
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4
|
||||
// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4, !nonnull [[META20]], !align [[META25:![0-9]+]]
|
||||
// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[B_ADDR]], align 4
|
||||
// CHECK11-NEXT: store i32 [[TMP4]], ptr [[B_CASTED]], align 4
|
||||
// CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[B_CASTED]], align 4
|
||||
// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218.omp_outlined, ptr [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], ptr [[TMP3]])
|
||||
// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
|
||||
// CHECK11-NEXT: [[THIS:%.*]] = load ptr, ptr [[TMP1]], align 4
|
||||
// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
|
||||
// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
|
||||
// CHECK11-NEXT: store i32 [[TMP3]], ptr [[B]], align 4
|
||||
// CHECK11-NEXT: [[TMP4:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 2
|
||||
// CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
|
||||
// CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 3
|
||||
// CHECK11-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4
|
||||
// CHECK11-NEXT: [[TMP8:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 4
|
||||
// CHECK11-NEXT: [[C:%.*]] = load ptr, ptr [[TMP8]], align 4
|
||||
// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 5
|
||||
// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
|
||||
// CHECK11-NEXT: [[TMP9:%.*]] = load i32, ptr [[B]], align 4
|
||||
// CHECK11-NEXT: store i32 [[TMP9]], ptr [[B_CASTED]], align 4
|
||||
// CHECK11-NEXT: [[TMP10:%.*]] = load i32, ptr [[B_CASTED]], align 4
|
||||
// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218.omp_outlined, ptr [[THIS]], i32 [[TMP10]], i32 [[TMP5]], i32 [[TMP7]], ptr [[C]])
|
||||
// CHECK11-NEXT: ret void
|
||||
//
|
||||
//
|
||||
@ -5364,7 +5458,7 @@ int bar(int n){
|
||||
// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4
|
||||
// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4, !nonnull [[META20]], !align [[META25]]
|
||||
// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4, !nonnull [[META20]], !align [[META25:![0-9]+]]
|
||||
// CHECK11-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
|
||||
// CHECK11-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4
|
||||
// CHECK11-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
|
||||
@ -5426,26 +5520,34 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183
|
||||
// CHECK11-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK11-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK11-NEXT: entry:
|
||||
// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[A:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[AA:%.*]] = alloca i16, align 2
|
||||
// CHECK11-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
|
||||
// CHECK11-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4
|
||||
// CHECK11-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4
|
||||
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4, !nonnull [[META20]], !align [[META21]]
|
||||
// CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
|
||||
// CHECK11-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4
|
||||
// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 4
|
||||
// CHECK11-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2
|
||||
// CHECK11-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2
|
||||
// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[AA_CASTED]], align 4
|
||||
// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183.omp_outlined, i32 [[TMP2]], i32 [[TMP4]], ptr [[TMP0]])
|
||||
// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
|
||||
// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
|
||||
// CHECK11-NEXT: store i32 [[TMP2]], ptr [[A]], align 4
|
||||
// CHECK11-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
|
||||
// CHECK11-NEXT: [[TMP4:%.*]] = load i16, ptr [[TMP3]], align 4
|
||||
// CHECK11-NEXT: store i16 [[TMP4]], ptr [[AA]], align 2
|
||||
// CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 2
|
||||
// CHECK11-NEXT: [[B:%.*]] = load ptr, ptr [[TMP5]], align 4
|
||||
// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 3
|
||||
// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
|
||||
// CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[A]], align 4
|
||||
// CHECK11-NEXT: store i32 [[TMP6]], ptr [[A_CASTED]], align 4
|
||||
// CHECK11-NEXT: [[TMP7:%.*]] = load i32, ptr [[A_CASTED]], align 4
|
||||
// CHECK11-NEXT: [[TMP8:%.*]] = load i16, ptr [[AA]], align 2
|
||||
// CHECK11-NEXT: store i16 [[TMP8]], ptr [[AA_CASTED]], align 2
|
||||
// CHECK11-NEXT: [[TMP9:%.*]] = load i32, ptr [[AA_CASTED]], align 4
|
||||
// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183.omp_outlined, i32 [[TMP7]], i32 [[TMP9]], ptr [[B]])
|
||||
// CHECK11-NEXT: ret void
|
||||
//
|
||||
//
|
||||
|
||||
@ -1876,28 +1876,38 @@ int target_teams_fun(int *g){
|
||||
//
|
||||
//
|
||||
// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l51
|
||||
// CHECK10-SAME: (i64 noundef [[N:%.*]], ptr noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_1:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK10-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK10-NEXT: entry:
|
||||
// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8
|
||||
// CHECK10-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK10-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK10-NEXT: [[N:%.*]] = alloca i32, align 4
|
||||
// CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
|
||||
// CHECK10-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
|
||||
// CHECK10-NEXT: [[DYN_PTR2:%.*]] = alloca ptr, align 8
|
||||
// CHECK10-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8
|
||||
// CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB3:[0-9]+]])
|
||||
// CHECK10-NEXT: store i64 [[N]], ptr [[N_ADDR]], align 8
|
||||
// CHECK10-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8
|
||||
// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8
|
||||
// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], ptr [[DOTCAPTURE_EXPR__ADDR2]], align 8
|
||||
// CHECK10-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK10-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !nonnull [[META7:![0-9]+]], !align [[META8:![0-9]+]]
|
||||
// CHECK10-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
|
||||
// CHECK10-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR2]], align 4
|
||||
// CHECK10-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB3]], i32 [[TMP0]], i32 [[TMP2]], i32 [[TMP3]])
|
||||
// CHECK10-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4
|
||||
// CHECK10-NEXT: store i32 [[TMP4]], ptr [[N_CASTED]], align 4
|
||||
// CHECK10-NEXT: [[TMP5:%.*]] = load i64, ptr [[N_CASTED]], align 8
|
||||
// CHECK10-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l51.omp_outlined, i64 [[TMP5]], ptr [[TMP1]])
|
||||
// CHECK10-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK10-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK10-NEXT: [[TMP2:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 0
|
||||
// CHECK10-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 8
|
||||
// CHECK10-NEXT: store i32 [[TMP3]], ptr [[N]], align 4
|
||||
// CHECK10-NEXT: [[TMP4:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 1
|
||||
// CHECK10-NEXT: [[A:%.*]] = load ptr, ptr [[TMP4]], align 8
|
||||
// CHECK10-NEXT: [[TMP5:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 2
|
||||
// CHECK10-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 8
|
||||
// CHECK10-NEXT: store i32 [[TMP6]], ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
// CHECK10-NEXT: [[TMP7:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 3
|
||||
// CHECK10-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 8
|
||||
// CHECK10-NEXT: store i32 [[TMP8]], ptr [[DOTCAPTURE_EXPR_1]], align 4
|
||||
// CHECK10-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 4
|
||||
// CHECK10-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK10-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR2]], align 8
|
||||
// CHECK10-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
// CHECK10-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
|
||||
// CHECK10-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB3]], i32 [[TMP0]], i32 [[TMP9]], i32 [[TMP10]])
|
||||
// CHECK10-NEXT: [[TMP11:%.*]] = load i32, ptr [[N]], align 4
|
||||
// CHECK10-NEXT: store i32 [[TMP11]], ptr [[N_CASTED]], align 4
|
||||
// CHECK10-NEXT: [[TMP12:%.*]] = load i64, ptr [[N_CASTED]], align 8
|
||||
// CHECK10-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l51.omp_outlined, i64 [[TMP12]], ptr [[A]])
|
||||
// CHECK10-NEXT: ret void
|
||||
//
|
||||
//
|
||||
@ -1923,7 +1933,7 @@ int target_teams_fun(int *g){
|
||||
// CHECK10-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
|
||||
// CHECK10-NEXT: store i64 [[N]], ptr [[N_ADDR]], align 8
|
||||
// CHECK10-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8
|
||||
// CHECK10-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !nonnull [[META7]], !align [[META8]]
|
||||
// CHECK10-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !nonnull [[META7:![0-9]+]], !align [[META8:![0-9]+]]
|
||||
// CHECK10-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
|
||||
// CHECK10-NEXT: store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
// CHECK10-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
@ -2109,23 +2119,28 @@ int target_teams_fun(int *g){
|
||||
//
|
||||
//
|
||||
// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l58
|
||||
// CHECK10-SAME: (i64 noundef [[N:%.*]], ptr noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], ptr noundef [[G:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK10-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK10-NEXT: entry:
|
||||
// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK10-NEXT: [[G_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK10-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK10-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK10-NEXT: [[N:%.*]] = alloca i32, align 4
|
||||
// CHECK10-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
|
||||
// CHECK10-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8
|
||||
// CHECK10-NEXT: store i64 [[N]], ptr [[N_ADDR]], align 8
|
||||
// CHECK10-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8
|
||||
// CHECK10-NEXT: store ptr [[G]], ptr [[G_ADDR]], align 8
|
||||
// CHECK10-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK10-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !nonnull [[META7]], !align [[META8]]
|
||||
// CHECK10-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
|
||||
// CHECK10-NEXT: store i32 [[TMP1]], ptr [[N_CASTED]], align 4
|
||||
// CHECK10-NEXT: [[TMP2:%.*]] = load i64, ptr [[N_CASTED]], align 8
|
||||
// CHECK10-NEXT: [[TMP3:%.*]] = load ptr, ptr [[G_ADDR]], align 8
|
||||
// CHECK10-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l58.omp_outlined, i64 [[TMP2]], ptr [[TMP0]], ptr [[TMP3]])
|
||||
// CHECK10-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK10-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK10-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
|
||||
// CHECK10-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 8
|
||||
// CHECK10-NEXT: store i32 [[TMP2]], ptr [[N]], align 4
|
||||
// CHECK10-NEXT: [[TMP3:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
|
||||
// CHECK10-NEXT: [[A:%.*]] = load ptr, ptr [[TMP3]], align 8
|
||||
// CHECK10-NEXT: [[G:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 2
|
||||
// CHECK10-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 3
|
||||
// CHECK10-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK10-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
|
||||
// CHECK10-NEXT: [[TMP4:%.*]] = load i32, ptr [[N]], align 4
|
||||
// CHECK10-NEXT: store i32 [[TMP4]], ptr [[N_CASTED]], align 4
|
||||
// CHECK10-NEXT: [[TMP5:%.*]] = load i64, ptr [[N_CASTED]], align 8
|
||||
// CHECK10-NEXT: [[TMP6:%.*]] = load ptr, ptr [[G]], align 8
|
||||
// CHECK10-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l58.omp_outlined, i64 [[TMP5]], ptr [[A]], ptr [[TMP6]])
|
||||
// CHECK10-NEXT: ret void
|
||||
//
|
||||
//
|
||||
@ -2330,28 +2345,38 @@ int target_teams_fun(int *g){
|
||||
//
|
||||
//
|
||||
// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l51
|
||||
// CHECK12-SAME: (i32 noundef [[N:%.*]], ptr noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]], i32 noundef [[DOTCAPTURE_EXPR_1:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK12-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK12-NEXT: entry:
|
||||
// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4
|
||||
// CHECK12-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK12-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK12-NEXT: [[N:%.*]] = alloca i32, align 4
|
||||
// CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
|
||||
// CHECK12-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
|
||||
// CHECK12-NEXT: [[DYN_PTR2:%.*]] = alloca ptr, align 4
|
||||
// CHECK12-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4
|
||||
// CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB3:[0-9]+]])
|
||||
// CHECK12-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
|
||||
// CHECK12-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4
|
||||
// CHECK12-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
|
||||
// CHECK12-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], ptr [[DOTCAPTURE_EXPR__ADDR2]], align 4
|
||||
// CHECK12-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK12-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 4, !nonnull [[META8:![0-9]+]], !align [[META9:![0-9]+]]
|
||||
// CHECK12-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
|
||||
// CHECK12-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR2]], align 4
|
||||
// CHECK12-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB3]], i32 [[TMP0]], i32 [[TMP2]], i32 [[TMP3]])
|
||||
// CHECK12-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4
|
||||
// CHECK12-NEXT: store i32 [[TMP4]], ptr [[N_CASTED]], align 4
|
||||
// CHECK12-NEXT: [[TMP5:%.*]] = load i32, ptr [[N_CASTED]], align 4
|
||||
// CHECK12-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l51.omp_outlined, i32 [[TMP5]], ptr [[TMP1]])
|
||||
// CHECK12-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK12-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK12-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 0
|
||||
// CHECK12-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
|
||||
// CHECK12-NEXT: store i32 [[TMP3]], ptr [[N]], align 4
|
||||
// CHECK12-NEXT: [[TMP4:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 1
|
||||
// CHECK12-NEXT: [[A:%.*]] = load ptr, ptr [[TMP4]], align 4
|
||||
// CHECK12-NEXT: [[TMP5:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 2
|
||||
// CHECK12-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4
|
||||
// CHECK12-NEXT: store i32 [[TMP6]], ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
// CHECK12-NEXT: [[TMP7:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 3
|
||||
// CHECK12-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4
|
||||
// CHECK12-NEXT: store i32 [[TMP8]], ptr [[DOTCAPTURE_EXPR_1]], align 4
|
||||
// CHECK12-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 4
|
||||
// CHECK12-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK12-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR2]], align 4
|
||||
// CHECK12-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
// CHECK12-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
|
||||
// CHECK12-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB3]], i32 [[TMP0]], i32 [[TMP9]], i32 [[TMP10]])
|
||||
// CHECK12-NEXT: [[TMP11:%.*]] = load i32, ptr [[N]], align 4
|
||||
// CHECK12-NEXT: store i32 [[TMP11]], ptr [[N_CASTED]], align 4
|
||||
// CHECK12-NEXT: [[TMP12:%.*]] = load i32, ptr [[N_CASTED]], align 4
|
||||
// CHECK12-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l51.omp_outlined, i32 [[TMP12]], ptr [[A]])
|
||||
// CHECK12-NEXT: ret void
|
||||
//
|
||||
//
|
||||
@ -2377,7 +2402,7 @@ int target_teams_fun(int *g){
|
||||
// CHECK12-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
|
||||
// CHECK12-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
|
||||
// CHECK12-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4
|
||||
// CHECK12-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4, !nonnull [[META8]], !align [[META9]]
|
||||
// CHECK12-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4, !nonnull [[META8:![0-9]+]], !align [[META9:![0-9]+]]
|
||||
// CHECK12-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
|
||||
// CHECK12-NEXT: store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
// CHECK12-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
@ -2558,23 +2583,28 @@ int target_teams_fun(int *g){
|
||||
//
|
||||
//
|
||||
// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l58
|
||||
// CHECK12-SAME: (i32 noundef [[N:%.*]], ptr noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], ptr noundef [[G:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK12-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK12-NEXT: entry:
|
||||
// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK12-NEXT: [[G_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK12-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK12-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK12-NEXT: [[N:%.*]] = alloca i32, align 4
|
||||
// CHECK12-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 4
|
||||
// CHECK12-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4
|
||||
// CHECK12-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
|
||||
// CHECK12-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4
|
||||
// CHECK12-NEXT: store ptr [[G]], ptr [[G_ADDR]], align 4
|
||||
// CHECK12-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK12-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4, !nonnull [[META8]], !align [[META9]]
|
||||
// CHECK12-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
|
||||
// CHECK12-NEXT: store i32 [[TMP1]], ptr [[N_CASTED]], align 4
|
||||
// CHECK12-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_CASTED]], align 4
|
||||
// CHECK12-NEXT: [[TMP3:%.*]] = load ptr, ptr [[G_ADDR]], align 4
|
||||
// CHECK12-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l58.omp_outlined, i32 [[TMP2]], ptr [[TMP0]], ptr [[TMP3]])
|
||||
// CHECK12-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK12-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK12-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
|
||||
// CHECK12-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
|
||||
// CHECK12-NEXT: store i32 [[TMP2]], ptr [[N]], align 4
|
||||
// CHECK12-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
|
||||
// CHECK12-NEXT: [[A:%.*]] = load ptr, ptr [[TMP3]], align 4
|
||||
// CHECK12-NEXT: [[G:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 2
|
||||
// CHECK12-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 3
|
||||
// CHECK12-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK12-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
|
||||
// CHECK12-NEXT: [[TMP4:%.*]] = load i32, ptr [[N]], align 4
|
||||
// CHECK12-NEXT: store i32 [[TMP4]], ptr [[N_CASTED]], align 4
|
||||
// CHECK12-NEXT: [[TMP5:%.*]] = load i32, ptr [[N_CASTED]], align 4
|
||||
// CHECK12-NEXT: [[TMP6:%.*]] = load ptr, ptr [[G]], align 4
|
||||
// CHECK12-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l58.omp_outlined, i32 [[TMP5]], ptr [[A]], ptr [[TMP6]])
|
||||
// CHECK12-NEXT: ret void
|
||||
//
|
||||
//
|
||||
|
||||
@ -2677,32 +2677,38 @@ int main() {
|
||||
//
|
||||
//
|
||||
// CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l122
|
||||
// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SIVAR:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK13-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK13-NEXT: entry:
|
||||
// CHECK13-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK13-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK13-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK13-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK13-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK13-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK13-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK13-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
|
||||
// CHECK13-NEXT: [[SIVAR:%.*]] = alloca i32, align 4
|
||||
// CHECK13-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
|
||||
// CHECK13-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8
|
||||
// CHECK13-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8
|
||||
// CHECK13-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 8
|
||||
// CHECK13-NEXT: store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8
|
||||
// CHECK13-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8
|
||||
// CHECK13-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8
|
||||
// CHECK13-NEXT: store i64 [[SIVAR]], ptr [[SIVAR_ADDR]], align 8
|
||||
// CHECK13-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK13-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8, !nonnull [[META7:![0-9]+]], !align [[META8:![0-9]+]]
|
||||
// CHECK13-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]]
|
||||
// CHECK13-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]]
|
||||
// CHECK13-NEXT: [[TMP3:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4
|
||||
// CHECK13-NEXT: store i32 [[TMP3]], ptr [[T_VAR_CASTED]], align 4
|
||||
// CHECK13-NEXT: [[TMP4:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8
|
||||
// CHECK13-NEXT: [[TMP5:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 4
|
||||
// CHECK13-NEXT: store i32 [[TMP5]], ptr [[SIVAR_CASTED]], align 4
|
||||
// CHECK13-NEXT: [[TMP6:%.*]] = load i64, ptr [[SIVAR_CASTED]], align 8
|
||||
// CHECK13-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3:[0-9]+]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l122.omp_outlined, ptr [[TMP0]], i64 [[TMP4]], ptr [[TMP1]], ptr [[TMP2]], i64 [[TMP6]])
|
||||
// CHECK13-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK13-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK13-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
|
||||
// CHECK13-NEXT: [[VEC:%.*]] = load ptr, ptr [[TMP1]], align 8
|
||||
// CHECK13-NEXT: [[TMP2:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
|
||||
// CHECK13-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 8
|
||||
// CHECK13-NEXT: store i32 [[TMP3]], ptr [[T_VAR]], align 4
|
||||
// CHECK13-NEXT: [[TMP4:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 2
|
||||
// CHECK13-NEXT: [[S_ARR:%.*]] = load ptr, ptr [[TMP4]], align 8
|
||||
// CHECK13-NEXT: [[TMP5:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 3
|
||||
// CHECK13-NEXT: [[VAR:%.*]] = load ptr, ptr [[TMP5]], align 8
|
||||
// CHECK13-NEXT: [[TMP6:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 4
|
||||
// CHECK13-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 8
|
||||
// CHECK13-NEXT: store i32 [[TMP7]], ptr [[SIVAR]], align 4
|
||||
// CHECK13-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 5
|
||||
// CHECK13-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK13-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
|
||||
// CHECK13-NEXT: [[TMP8:%.*]] = load i32, ptr [[T_VAR]], align 4
|
||||
// CHECK13-NEXT: store i32 [[TMP8]], ptr [[T_VAR_CASTED]], align 4
|
||||
// CHECK13-NEXT: [[TMP9:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8
|
||||
// CHECK13-NEXT: [[TMP10:%.*]] = load i32, ptr [[SIVAR]], align 4
|
||||
// CHECK13-NEXT: store i32 [[TMP10]], ptr [[SIVAR_CASTED]], align 4
|
||||
// CHECK13-NEXT: [[TMP11:%.*]] = load i64, ptr [[SIVAR_CASTED]], align 8
|
||||
// CHECK13-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3:[0-9]+]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l122.omp_outlined, ptr [[VEC]], i64 [[TMP9]], ptr [[S_ARR]], ptr [[VAR]], i64 [[TMP11]])
|
||||
// CHECK13-NEXT: ret void
|
||||
//
|
||||
//
|
||||
@ -2737,7 +2743,7 @@ int main() {
|
||||
// CHECK13-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8
|
||||
// CHECK13-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8
|
||||
// CHECK13-NEXT: store i64 [[SIVAR]], ptr [[SIVAR_ADDR]], align 8
|
||||
// CHECK13-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8, !nonnull [[META7]], !align [[META8]]
|
||||
// CHECK13-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8, !nonnull [[META7:![0-9]+]], !align [[META8:![0-9]+]]
|
||||
// CHECK13-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]]
|
||||
// CHECK13-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]]
|
||||
// CHECK13-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4
|
||||
@ -3007,29 +3013,33 @@ int main() {
|
||||
//
|
||||
//
|
||||
// CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81
|
||||
// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK13-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK13-NEXT: entry:
|
||||
// CHECK13-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK13-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK13-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK13-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK13-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK13-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK13-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
|
||||
// CHECK13-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
|
||||
// CHECK13-NEXT: [[TMP:%.*]] = alloca ptr, align 8
|
||||
// CHECK13-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8
|
||||
// CHECK13-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 8
|
||||
// CHECK13-NEXT: store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8
|
||||
// CHECK13-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8
|
||||
// CHECK13-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8
|
||||
// CHECK13-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK13-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8, !nonnull [[META7]], !align [[META8]]
|
||||
// CHECK13-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]]
|
||||
// CHECK13-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]]
|
||||
// CHECK13-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 8
|
||||
// CHECK13-NEXT: [[TMP3:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4
|
||||
// CHECK13-NEXT: store i32 [[TMP3]], ptr [[T_VAR_CASTED]], align 4
|
||||
// CHECK13-NEXT: [[TMP4:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8
|
||||
// CHECK13-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META7]], !align [[META8]]
|
||||
// CHECK13-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81.omp_outlined, ptr [[TMP0]], i64 [[TMP4]], ptr [[TMP1]], ptr [[TMP5]])
|
||||
// CHECK13-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK13-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK13-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
|
||||
// CHECK13-NEXT: [[VEC:%.*]] = load ptr, ptr [[TMP1]], align 8
|
||||
// CHECK13-NEXT: [[TMP2:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
|
||||
// CHECK13-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 8
|
||||
// CHECK13-NEXT: store i32 [[TMP3]], ptr [[T_VAR]], align 4
|
||||
// CHECK13-NEXT: [[TMP4:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 2
|
||||
// CHECK13-NEXT: [[S_ARR:%.*]] = load ptr, ptr [[TMP4]], align 8
|
||||
// CHECK13-NEXT: [[TMP5:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 3
|
||||
// CHECK13-NEXT: [[VAR:%.*]] = load ptr, ptr [[TMP5]], align 8
|
||||
// CHECK13-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 4
|
||||
// CHECK13-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK13-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
|
||||
// CHECK13-NEXT: store ptr [[VAR]], ptr [[TMP]], align 8
|
||||
// CHECK13-NEXT: [[TMP6:%.*]] = load i32, ptr [[T_VAR]], align 4
|
||||
// CHECK13-NEXT: store i32 [[TMP6]], ptr [[T_VAR_CASTED]], align 4
|
||||
// CHECK13-NEXT: [[TMP7:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8
|
||||
// CHECK13-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META7]], !align [[META8]]
|
||||
// CHECK13-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81.omp_outlined, ptr [[VEC]], i64 [[TMP7]], ptr [[S_ARR]], ptr [[TMP8]])
|
||||
// CHECK13-NEXT: ret void
|
||||
//
|
||||
//
|
||||
@ -3397,32 +3407,38 @@ int main() {
|
||||
//
|
||||
//
|
||||
// CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l122
|
||||
// CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SIVAR:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK15-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK15-NEXT: entry:
|
||||
// CHECK15-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK15-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK15-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK15-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK15-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK15-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK15-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK15-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
|
||||
// CHECK15-NEXT: [[SIVAR:%.*]] = alloca i32, align 4
|
||||
// CHECK15-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 4
|
||||
// CHECK15-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4
|
||||
// CHECK15-NEXT: [[SIVAR_CASTED:%.*]] = alloca i32, align 4
|
||||
// CHECK15-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 4
|
||||
// CHECK15-NEXT: store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 4
|
||||
// CHECK15-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4
|
||||
// CHECK15-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 4
|
||||
// CHECK15-NEXT: store i32 [[SIVAR]], ptr [[SIVAR_ADDR]], align 4
|
||||
// CHECK15-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK15-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4, !nonnull [[META8:![0-9]+]], !align [[META9:![0-9]+]]
|
||||
// CHECK15-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]]
|
||||
// CHECK15-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]]
|
||||
// CHECK15-NEXT: [[TMP3:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4
|
||||
// CHECK15-NEXT: store i32 [[TMP3]], ptr [[T_VAR_CASTED]], align 4
|
||||
// CHECK15-NEXT: [[TMP4:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 4
|
||||
// CHECK15-NEXT: [[TMP5:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 4
|
||||
// CHECK15-NEXT: store i32 [[TMP5]], ptr [[SIVAR_CASTED]], align 4
|
||||
// CHECK15-NEXT: [[TMP6:%.*]] = load i32, ptr [[SIVAR_CASTED]], align 4
|
||||
// CHECK15-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3:[0-9]+]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l122.omp_outlined, ptr [[TMP0]], i32 [[TMP4]], ptr [[TMP1]], ptr [[TMP2]], i32 [[TMP6]])
|
||||
// CHECK15-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK15-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK15-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
|
||||
// CHECK15-NEXT: [[VEC:%.*]] = load ptr, ptr [[TMP1]], align 4
|
||||
// CHECK15-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
|
||||
// CHECK15-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
|
||||
// CHECK15-NEXT: store i32 [[TMP3]], ptr [[T_VAR]], align 4
|
||||
// CHECK15-NEXT: [[TMP4:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 2
|
||||
// CHECK15-NEXT: [[S_ARR:%.*]] = load ptr, ptr [[TMP4]], align 4
|
||||
// CHECK15-NEXT: [[TMP5:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 3
|
||||
// CHECK15-NEXT: [[VAR:%.*]] = load ptr, ptr [[TMP5]], align 4
|
||||
// CHECK15-NEXT: [[TMP6:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 4
|
||||
// CHECK15-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4
|
||||
// CHECK15-NEXT: store i32 [[TMP7]], ptr [[SIVAR]], align 4
|
||||
// CHECK15-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 5
|
||||
// CHECK15-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK15-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
|
||||
// CHECK15-NEXT: [[TMP8:%.*]] = load i32, ptr [[T_VAR]], align 4
|
||||
// CHECK15-NEXT: store i32 [[TMP8]], ptr [[T_VAR_CASTED]], align 4
|
||||
// CHECK15-NEXT: [[TMP9:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 4
|
||||
// CHECK15-NEXT: [[TMP10:%.*]] = load i32, ptr [[SIVAR]], align 4
|
||||
// CHECK15-NEXT: store i32 [[TMP10]], ptr [[SIVAR_CASTED]], align 4
|
||||
// CHECK15-NEXT: [[TMP11:%.*]] = load i32, ptr [[SIVAR_CASTED]], align 4
|
||||
// CHECK15-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3:[0-9]+]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l122.omp_outlined, ptr [[VEC]], i32 [[TMP9]], ptr [[S_ARR]], ptr [[VAR]], i32 [[TMP11]])
|
||||
// CHECK15-NEXT: ret void
|
||||
//
|
||||
//
|
||||
@ -3457,7 +3473,7 @@ int main() {
|
||||
// CHECK15-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4
|
||||
// CHECK15-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 4
|
||||
// CHECK15-NEXT: store i32 [[SIVAR]], ptr [[SIVAR_ADDR]], align 4
|
||||
// CHECK15-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4, !nonnull [[META8]], !align [[META9]]
|
||||
// CHECK15-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4, !nonnull [[META8:![0-9]+]], !align [[META9:![0-9]+]]
|
||||
// CHECK15-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]]
|
||||
// CHECK15-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]]
|
||||
// CHECK15-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4
|
||||
@ -3721,29 +3737,33 @@ int main() {
|
||||
//
|
||||
//
|
||||
// CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81
|
||||
// CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK15-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK15-NEXT: entry:
|
||||
// CHECK15-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK15-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK15-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK15-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK15-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK15-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK15-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
|
||||
// CHECK15-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 4
|
||||
// CHECK15-NEXT: [[TMP:%.*]] = alloca ptr, align 4
|
||||
// CHECK15-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4
|
||||
// CHECK15-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 4
|
||||
// CHECK15-NEXT: store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 4
|
||||
// CHECK15-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4
|
||||
// CHECK15-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 4
|
||||
// CHECK15-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK15-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4, !nonnull [[META8]], !align [[META9]]
|
||||
// CHECK15-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]]
|
||||
// CHECK15-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]]
|
||||
// CHECK15-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 4
|
||||
// CHECK15-NEXT: [[TMP3:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4
|
||||
// CHECK15-NEXT: store i32 [[TMP3]], ptr [[T_VAR_CASTED]], align 4
|
||||
// CHECK15-NEXT: [[TMP4:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 4
|
||||
// CHECK15-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META8]], !align [[META9]]
|
||||
// CHECK15-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81.omp_outlined, ptr [[TMP0]], i32 [[TMP4]], ptr [[TMP1]], ptr [[TMP5]])
|
||||
// CHECK15-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK15-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK15-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
|
||||
// CHECK15-NEXT: [[VEC:%.*]] = load ptr, ptr [[TMP1]], align 4
|
||||
// CHECK15-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
|
||||
// CHECK15-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
|
||||
// CHECK15-NEXT: store i32 [[TMP3]], ptr [[T_VAR]], align 4
|
||||
// CHECK15-NEXT: [[TMP4:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 2
|
||||
// CHECK15-NEXT: [[S_ARR:%.*]] = load ptr, ptr [[TMP4]], align 4
|
||||
// CHECK15-NEXT: [[TMP5:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 3
|
||||
// CHECK15-NEXT: [[VAR:%.*]] = load ptr, ptr [[TMP5]], align 4
|
||||
// CHECK15-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 4
|
||||
// CHECK15-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK15-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
|
||||
// CHECK15-NEXT: store ptr [[VAR]], ptr [[TMP]], align 4
|
||||
// CHECK15-NEXT: [[TMP6:%.*]] = load i32, ptr [[T_VAR]], align 4
|
||||
// CHECK15-NEXT: store i32 [[TMP6]], ptr [[T_VAR_CASTED]], align 4
|
||||
// CHECK15-NEXT: [[TMP7:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 4
|
||||
// CHECK15-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META8]], !align [[META9]]
|
||||
// CHECK15-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81.omp_outlined, ptr [[VEC]], i32 [[TMP7]], ptr [[S_ARR]], ptr [[TMP8]])
|
||||
// CHECK15-NEXT: ret void
|
||||
//
|
||||
//
|
||||
@ -4105,32 +4125,43 @@ int main() {
|
||||
//
|
||||
//
|
||||
// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l99
|
||||
// CHECK17-SAME: (i64 noundef [[G:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SIVAR:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK17-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK17-NEXT: entry:
|
||||
// CHECK17-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK17-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK17-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK17-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK17-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK17-NEXT: [[G:%.*]] = alloca i32, align 4
|
||||
// CHECK17-NEXT: [[G1:%.*]] = alloca i32, align 4
|
||||
// CHECK17-NEXT: [[SIVAR:%.*]] = alloca i32, align 4
|
||||
// CHECK17-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
|
||||
// CHECK17-NEXT: [[TMP:%.*]] = alloca ptr, align 8
|
||||
// CHECK17-NEXT: [[G_CASTED:%.*]] = alloca i64, align 8
|
||||
// CHECK17-NEXT: [[G1_CASTED:%.*]] = alloca i64, align 8
|
||||
// CHECK17-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8
|
||||
// CHECK17-NEXT: store i64 [[G]], ptr [[G_ADDR]], align 8
|
||||
// CHECK17-NEXT: store i64 [[G1]], ptr [[G1_ADDR]], align 8
|
||||
// CHECK17-NEXT: store i64 [[SIVAR]], ptr [[SIVAR_ADDR]], align 8
|
||||
// CHECK17-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK17-NEXT: store ptr [[G1_ADDR]], ptr [[TMP]], align 8
|
||||
// CHECK17-NEXT: [[TMP0:%.*]] = load i32, ptr [[G_ADDR]], align 4
|
||||
// CHECK17-NEXT: store i32 [[TMP0]], ptr [[G_CASTED]], align 4
|
||||
// CHECK17-NEXT: [[TMP1:%.*]] = load i64, ptr [[G_CASTED]], align 8
|
||||
// CHECK17-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META5:![0-9]+]], !align [[META6:![0-9]+]]
|
||||
// CHECK17-NEXT: [[TMP3:%.*]] = load volatile i32, ptr [[TMP2]], align 4
|
||||
// CHECK17-NEXT: store i32 [[TMP3]], ptr [[G1_CASTED]], align 4
|
||||
// CHECK17-NEXT: [[TMP4:%.*]] = load i64, ptr [[G1_CASTED]], align 8
|
||||
// CHECK17-NEXT: [[TMP5:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 4
|
||||
// CHECK17-NEXT: store i32 [[TMP5]], ptr [[SIVAR_CASTED]], align 4
|
||||
// CHECK17-NEXT: [[TMP6:%.*]] = load i64, ptr [[SIVAR_CASTED]], align 8
|
||||
// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3:[0-9]+]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l99.omp_outlined, i64 [[TMP1]], i64 [[TMP4]], i64 [[TMP6]])
|
||||
// CHECK17-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK17-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
|
||||
// CHECK17-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 8
|
||||
// CHECK17-NEXT: store i32 [[TMP2]], ptr [[G]], align 4
|
||||
// CHECK17-NEXT: [[TMP3:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
|
||||
// CHECK17-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 8
|
||||
// CHECK17-NEXT: store i32 [[TMP4]], ptr [[G1]], align 4
|
||||
// CHECK17-NEXT: [[TMP5:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 2
|
||||
// CHECK17-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 8
|
||||
// CHECK17-NEXT: store i32 [[TMP6]], ptr [[SIVAR]], align 4
|
||||
// CHECK17-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 3
|
||||
// CHECK17-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK17-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
|
||||
// CHECK17-NEXT: store ptr [[G1]], ptr [[TMP]], align 8
|
||||
// CHECK17-NEXT: [[TMP7:%.*]] = load i32, ptr [[G]], align 4
|
||||
// CHECK17-NEXT: store i32 [[TMP7]], ptr [[G_CASTED]], align 4
|
||||
// CHECK17-NEXT: [[TMP8:%.*]] = load i64, ptr [[G_CASTED]], align 8
|
||||
// CHECK17-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META5:![0-9]+]], !align [[META6:![0-9]+]]
|
||||
// CHECK17-NEXT: [[TMP10:%.*]] = load volatile i32, ptr [[TMP9]], align 4
|
||||
// CHECK17-NEXT: store i32 [[TMP10]], ptr [[G1_CASTED]], align 4
|
||||
// CHECK17-NEXT: [[TMP11:%.*]] = load i64, ptr [[G1_CASTED]], align 8
|
||||
// CHECK17-NEXT: [[TMP12:%.*]] = load i32, ptr [[SIVAR]], align 4
|
||||
// CHECK17-NEXT: store i32 [[TMP12]], ptr [[SIVAR_CASTED]], align 4
|
||||
// CHECK17-NEXT: [[TMP13:%.*]] = load i64, ptr [[SIVAR_CASTED]], align 8
|
||||
// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3:[0-9]+]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l99.omp_outlined, i64 [[TMP8]], i64 [[TMP11]], i64 [[TMP13]])
|
||||
// CHECK17-NEXT: ret void
|
||||
//
|
||||
//
|
||||
|
||||
@ -1983,10 +1983,15 @@ int main() {
|
||||
//
|
||||
//
|
||||
// CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124
|
||||
// CHECK13-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK13-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK13-NEXT: entry:
|
||||
// CHECK13-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK13-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK13-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK13-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
|
||||
// CHECK13-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK13-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK13-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
|
||||
// CHECK13-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK13-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
|
||||
// CHECK13-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3:[0-9]+]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124.omp_outlined)
|
||||
// CHECK13-NEXT: ret void
|
||||
//
|
||||
@ -2217,10 +2222,15 @@ int main() {
|
||||
//
|
||||
//
|
||||
// CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l80
|
||||
// CHECK13-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK13-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK13-NEXT: entry:
|
||||
// CHECK13-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK13-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK13-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK13-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
|
||||
// CHECK13-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK13-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK13-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
|
||||
// CHECK13-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK13-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
|
||||
// CHECK13-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l80.omp_outlined)
|
||||
// CHECK13-NEXT: ret void
|
||||
//
|
||||
@ -2497,10 +2507,15 @@ int main() {
|
||||
//
|
||||
//
|
||||
// CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124
|
||||
// CHECK15-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK15-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK15-NEXT: entry:
|
||||
// CHECK15-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK15-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK15-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK15-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 4
|
||||
// CHECK15-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK15-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK15-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
|
||||
// CHECK15-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK15-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
|
||||
// CHECK15-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3:[0-9]+]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124.omp_outlined)
|
||||
// CHECK15-NEXT: ret void
|
||||
//
|
||||
@ -2725,10 +2740,15 @@ int main() {
|
||||
//
|
||||
//
|
||||
// CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l80
|
||||
// CHECK15-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK15-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK15-NEXT: entry:
|
||||
// CHECK15-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK15-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK15-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK15-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 4
|
||||
// CHECK15-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK15-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK15-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
|
||||
// CHECK15-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK15-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
|
||||
// CHECK15-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l80.omp_outlined)
|
||||
// CHECK15-NEXT: ret void
|
||||
//
|
||||
@ -2999,10 +3019,15 @@ int main() {
|
||||
//
|
||||
//
|
||||
// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l104
|
||||
// CHECK17-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK17-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK17-NEXT: entry:
|
||||
// CHECK17-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK17-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK17-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK17-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
|
||||
// CHECK17-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK17-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
|
||||
// CHECK17-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK17-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
|
||||
// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3:[0-9]+]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l104.omp_outlined)
|
||||
// CHECK17-NEXT: ret void
|
||||
//
|
||||
|
||||
@ -2371,34 +2371,46 @@ void test_target_teams_atomic() {
|
||||
//
|
||||
//
|
||||
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l50
|
||||
// CHECK9-SAME: (i64 noundef [[I:%.*]], i64 noundef [[N:%.*]], ptr noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_1:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK9-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK9-NEXT: entry:
|
||||
// CHECK9-NEXT: [[I_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4
|
||||
// CHECK9-NEXT: [[N:%.*]] = alloca i32, align 4
|
||||
// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
|
||||
// CHECK9-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
|
||||
// CHECK9-NEXT: [[DYN_PTR2:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[I_CASTED:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB4:[0-9]+]])
|
||||
// CHECK9-NEXT: store i64 [[I]], ptr [[I_ADDR]], align 8
|
||||
// CHECK9-NEXT: store i64 [[N]], ptr [[N_ADDR]], align 8
|
||||
// CHECK9-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8
|
||||
// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8
|
||||
// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], ptr [[DOTCAPTURE_EXPR__ADDR2]], align 8
|
||||
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !nonnull [[META9:![0-9]+]], !align [[META10:![0-9]+]]
|
||||
// CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
|
||||
// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR2]], align 4
|
||||
// CHECK9-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB4]], i32 [[TMP0]], i32 [[TMP2]], i32 [[TMP3]])
|
||||
// CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[I_ADDR]], align 4
|
||||
// CHECK9-NEXT: store i32 [[TMP4]], ptr [[I_CASTED]], align 4
|
||||
// CHECK9-NEXT: [[TMP5:%.*]] = load i64, ptr [[I_CASTED]], align 8
|
||||
// CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 4
|
||||
// CHECK9-NEXT: store i32 [[TMP6]], ptr [[N_CASTED]], align 4
|
||||
// CHECK9-NEXT: [[TMP7:%.*]] = load i64, ptr [[N_CASTED]], align 8
|
||||
// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB4]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l50.omp_outlined, i64 [[TMP5]], i64 [[TMP7]], ptr [[TMP1]])
|
||||
// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 0
|
||||
// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 8
|
||||
// CHECK9-NEXT: store i32 [[TMP3]], ptr [[I]], align 4
|
||||
// CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 1
|
||||
// CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 8
|
||||
// CHECK9-NEXT: store i32 [[TMP5]], ptr [[N]], align 4
|
||||
// CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 2
|
||||
// CHECK9-NEXT: [[A:%.*]] = load ptr, ptr [[TMP6]], align 8
|
||||
// CHECK9-NEXT: [[TMP7:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 3
|
||||
// CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 8
|
||||
// CHECK9-NEXT: store i32 [[TMP8]], ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
// CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 4
|
||||
// CHECK9-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 8
|
||||
// CHECK9-NEXT: store i32 [[TMP10]], ptr [[DOTCAPTURE_EXPR_1]], align 4
|
||||
// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 5
|
||||
// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR2]], align 8
|
||||
// CHECK9-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
// CHECK9-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
|
||||
// CHECK9-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB4]], i32 [[TMP0]], i32 [[TMP11]], i32 [[TMP12]])
|
||||
// CHECK9-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4
|
||||
// CHECK9-NEXT: store i32 [[TMP13]], ptr [[I_CASTED]], align 4
|
||||
// CHECK9-NEXT: [[TMP14:%.*]] = load i64, ptr [[I_CASTED]], align 8
|
||||
// CHECK9-NEXT: [[TMP15:%.*]] = load i32, ptr [[N]], align 4
|
||||
// CHECK9-NEXT: store i32 [[TMP15]], ptr [[N_CASTED]], align 4
|
||||
// CHECK9-NEXT: [[TMP16:%.*]] = load i64, ptr [[N_CASTED]], align 8
|
||||
// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB4]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l50.omp_outlined, i64 [[TMP14]], i64 [[TMP16]], ptr [[A]])
|
||||
// CHECK9-NEXT: ret void
|
||||
//
|
||||
//
|
||||
@ -2427,7 +2439,7 @@ void test_target_teams_atomic() {
|
||||
// CHECK9-NEXT: store i64 [[I]], ptr [[I_ADDR]], align 8
|
||||
// CHECK9-NEXT: store i64 [[N]], ptr [[N_ADDR]], align 8
|
||||
// CHECK9-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !nonnull [[META9]], !align [[META10]]
|
||||
// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !nonnull [[META9:![0-9]+]], !align [[META10:![0-9]+]]
|
||||
// CHECK9-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
|
||||
// CHECK9-NEXT: store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
// CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
@ -2647,23 +2659,28 @@ void test_target_teams_atomic() {
|
||||
//
|
||||
//
|
||||
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l56
|
||||
// CHECK9-SAME: (i64 noundef [[N:%.*]], ptr noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], ptr noundef [[G:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK9-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK9-NEXT: entry:
|
||||
// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[G_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[N:%.*]] = alloca i32, align 4
|
||||
// CHECK9-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: store i64 [[N]], ptr [[N_ADDR]], align 8
|
||||
// CHECK9-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8
|
||||
// CHECK9-NEXT: store ptr [[G]], ptr [[G_ADDR]], align 8
|
||||
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !nonnull [[META9]], !align [[META10]]
|
||||
// CHECK9-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
|
||||
// CHECK9-NEXT: store i32 [[TMP1]], ptr [[N_CASTED]], align 4
|
||||
// CHECK9-NEXT: [[TMP2:%.*]] = load i64, ptr [[N_CASTED]], align 8
|
||||
// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[G_ADDR]], align 8
|
||||
// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB4]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l56.omp_outlined, i64 [[TMP2]], ptr [[TMP0]], ptr [[TMP3]])
|
||||
// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
|
||||
// CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 8
|
||||
// CHECK9-NEXT: store i32 [[TMP2]], ptr [[N]], align 4
|
||||
// CHECK9-NEXT: [[TMP3:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
|
||||
// CHECK9-NEXT: [[A:%.*]] = load ptr, ptr [[TMP3]], align 8
|
||||
// CHECK9-NEXT: [[G:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 2
|
||||
// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 3
|
||||
// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
|
||||
// CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[N]], align 4
|
||||
// CHECK9-NEXT: store i32 [[TMP4]], ptr [[N_CASTED]], align 4
|
||||
// CHECK9-NEXT: [[TMP5:%.*]] = load i64, ptr [[N_CASTED]], align 8
|
||||
// CHECK9-NEXT: [[TMP6:%.*]] = load ptr, ptr [[G]], align 8
|
||||
// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB4]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l56.omp_outlined, i64 [[TMP5]], ptr [[A]], ptr [[TMP6]])
|
||||
// CHECK9-NEXT: ret void
|
||||
//
|
||||
//
|
||||
@ -2892,14 +2909,18 @@ void test_target_teams_atomic() {
|
||||
//
|
||||
//
|
||||
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z24test_target_teams_atomicv_l72
|
||||
// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[X:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK9-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK9-NEXT: entry:
|
||||
// CHECK9-NEXT: [[X_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: store ptr [[X]], ptr [[X_ADDR]], align 8
|
||||
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[X_ADDR]], align 8, !nonnull [[META9]], !align [[META10]]
|
||||
// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB4]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z24test_target_teams_atomicv_l72.omp_outlined, ptr [[TMP0]])
|
||||
// CHECK9-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
|
||||
// CHECK9-NEXT: [[X:%.*]] = load ptr, ptr [[TMP1]], align 8
|
||||
// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
|
||||
// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
|
||||
// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB4]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z24test_target_teams_atomicv_l72.omp_outlined, ptr [[X]])
|
||||
// CHECK9-NEXT: ret void
|
||||
//
|
||||
//
|
||||
@ -3055,34 +3076,46 @@ void test_target_teams_atomic() {
|
||||
//
|
||||
//
|
||||
// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l50
|
||||
// CHECK11-SAME: (i32 noundef [[I:%.*]], i32 noundef [[N:%.*]], ptr noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]], i32 noundef [[DOTCAPTURE_EXPR_1:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK11-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK11-NEXT: entry:
|
||||
// CHECK11-NEXT: [[I_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[N:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[DYN_PTR2:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[I_CASTED:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB4:[0-9]+]])
|
||||
// CHECK11-NEXT: store i32 [[I]], ptr [[I_ADDR]], align 4
|
||||
// CHECK11-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
|
||||
// CHECK11-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4
|
||||
// CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
|
||||
// CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], ptr [[DOTCAPTURE_EXPR__ADDR2]], align 4
|
||||
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 4, !nonnull [[META10:![0-9]+]], !align [[META11:![0-9]+]]
|
||||
// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR2]], align 4
|
||||
// CHECK11-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB4]], i32 [[TMP0]], i32 [[TMP2]], i32 [[TMP3]])
|
||||
// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[I_ADDR]], align 4
|
||||
// CHECK11-NEXT: store i32 [[TMP4]], ptr [[I_CASTED]], align 4
|
||||
// CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[I_CASTED]], align 4
|
||||
// CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 4
|
||||
// CHECK11-NEXT: store i32 [[TMP6]], ptr [[N_CASTED]], align 4
|
||||
// CHECK11-NEXT: [[TMP7:%.*]] = load i32, ptr [[N_CASTED]], align 4
|
||||
// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB4]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l50.omp_outlined, i32 [[TMP5]], i32 [[TMP7]], ptr [[TMP1]])
|
||||
// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 0
|
||||
// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
|
||||
// CHECK11-NEXT: store i32 [[TMP3]], ptr [[I]], align 4
|
||||
// CHECK11-NEXT: [[TMP4:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 1
|
||||
// CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
|
||||
// CHECK11-NEXT: store i32 [[TMP5]], ptr [[N]], align 4
|
||||
// CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 2
|
||||
// CHECK11-NEXT: [[A:%.*]] = load ptr, ptr [[TMP6]], align 4
|
||||
// CHECK11-NEXT: [[TMP7:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 3
|
||||
// CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4
|
||||
// CHECK11-NEXT: store i32 [[TMP8]], ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
// CHECK11-NEXT: [[TMP9:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 4
|
||||
// CHECK11-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4
|
||||
// CHECK11-NEXT: store i32 [[TMP10]], ptr [[DOTCAPTURE_EXPR_1]], align 4
|
||||
// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 5
|
||||
// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR2]], align 4
|
||||
// CHECK11-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
// CHECK11-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
|
||||
// CHECK11-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB4]], i32 [[TMP0]], i32 [[TMP11]], i32 [[TMP12]])
|
||||
// CHECK11-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4
|
||||
// CHECK11-NEXT: store i32 [[TMP13]], ptr [[I_CASTED]], align 4
|
||||
// CHECK11-NEXT: [[TMP14:%.*]] = load i32, ptr [[I_CASTED]], align 4
|
||||
// CHECK11-NEXT: [[TMP15:%.*]] = load i32, ptr [[N]], align 4
|
||||
// CHECK11-NEXT: store i32 [[TMP15]], ptr [[N_CASTED]], align 4
|
||||
// CHECK11-NEXT: [[TMP16:%.*]] = load i32, ptr [[N_CASTED]], align 4
|
||||
// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB4]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l50.omp_outlined, i32 [[TMP14]], i32 [[TMP16]], ptr [[A]])
|
||||
// CHECK11-NEXT: ret void
|
||||
//
|
||||
//
|
||||
@ -3111,7 +3144,7 @@ void test_target_teams_atomic() {
|
||||
// CHECK11-NEXT: store i32 [[I]], ptr [[I_ADDR]], align 4
|
||||
// CHECK11-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
|
||||
// CHECK11-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4, !nonnull [[META10]], !align [[META11]]
|
||||
// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4, !nonnull [[META10:![0-9]+]], !align [[META11:![0-9]+]]
|
||||
// CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
|
||||
// CHECK11-NEXT: store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
@ -3326,23 +3359,28 @@ void test_target_teams_atomic() {
|
||||
//
|
||||
//
|
||||
// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l56
|
||||
// CHECK11-SAME: (i32 noundef [[N:%.*]], ptr noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], ptr noundef [[G:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK11-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK11-NEXT: entry:
|
||||
// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[G_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[N:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
|
||||
// CHECK11-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4
|
||||
// CHECK11-NEXT: store ptr [[G]], ptr [[G_ADDR]], align 4
|
||||
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4, !nonnull [[META10]], !align [[META11]]
|
||||
// CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
|
||||
// CHECK11-NEXT: store i32 [[TMP1]], ptr [[N_CASTED]], align 4
|
||||
// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_CASTED]], align 4
|
||||
// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[G_ADDR]], align 4
|
||||
// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB4]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l56.omp_outlined, i32 [[TMP2]], ptr [[TMP0]], ptr [[TMP3]])
|
||||
// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
|
||||
// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
|
||||
// CHECK11-NEXT: store i32 [[TMP2]], ptr [[N]], align 4
|
||||
// CHECK11-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
|
||||
// CHECK11-NEXT: [[A:%.*]] = load ptr, ptr [[TMP3]], align 4
|
||||
// CHECK11-NEXT: [[G:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 2
|
||||
// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 3
|
||||
// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
|
||||
// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[N]], align 4
|
||||
// CHECK11-NEXT: store i32 [[TMP4]], ptr [[N_CASTED]], align 4
|
||||
// CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[N_CASTED]], align 4
|
||||
// CHECK11-NEXT: [[TMP6:%.*]] = load ptr, ptr [[G]], align 4
|
||||
// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB4]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l56.omp_outlined, i32 [[TMP5]], ptr [[A]], ptr [[TMP6]])
|
||||
// CHECK11-NEXT: ret void
|
||||
//
|
||||
//
|
||||
@ -3566,14 +3604,18 @@ void test_target_teams_atomic() {
|
||||
//
|
||||
//
|
||||
// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z24test_target_teams_atomicv_l72
|
||||
// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[X:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK11-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK11-NEXT: entry:
|
||||
// CHECK11-NEXT: [[X_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: store ptr [[X]], ptr [[X_ADDR]], align 4
|
||||
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[X_ADDR]], align 4, !nonnull [[META10]], !align [[META11]]
|
||||
// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB4]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z24test_target_teams_atomicv_l72.omp_outlined, ptr [[TMP0]])
|
||||
// CHECK11-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
|
||||
// CHECK11-NEXT: [[X:%.*]] = load ptr, ptr [[TMP1]], align 4
|
||||
// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
|
||||
// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
|
||||
// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB4]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z24test_target_teams_atomicv_l72.omp_outlined, ptr [[X]])
|
||||
// CHECK11-NEXT: ret void
|
||||
//
|
||||
//
|
||||
|
||||
@ -3517,32 +3517,38 @@ int main() {
|
||||
//
|
||||
//
|
||||
// CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l122
|
||||
// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SIVAR:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK13-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK13-NEXT: entry:
|
||||
// CHECK13-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK13-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK13-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK13-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK13-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK13-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK13-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK13-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
|
||||
// CHECK13-NEXT: [[SIVAR:%.*]] = alloca i32, align 4
|
||||
// CHECK13-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
|
||||
// CHECK13-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8
|
||||
// CHECK13-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8
|
||||
// CHECK13-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 8
|
||||
// CHECK13-NEXT: store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8
|
||||
// CHECK13-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8
|
||||
// CHECK13-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8
|
||||
// CHECK13-NEXT: store i64 [[SIVAR]], ptr [[SIVAR_ADDR]], align 8
|
||||
// CHECK13-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK13-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8, !nonnull [[META7:![0-9]+]], !align [[META8:![0-9]+]]
|
||||
// CHECK13-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]]
|
||||
// CHECK13-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]]
|
||||
// CHECK13-NEXT: [[TMP3:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4
|
||||
// CHECK13-NEXT: store i32 [[TMP3]], ptr [[T_VAR_CASTED]], align 4
|
||||
// CHECK13-NEXT: [[TMP4:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8
|
||||
// CHECK13-NEXT: [[TMP5:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 4
|
||||
// CHECK13-NEXT: store i32 [[TMP5]], ptr [[SIVAR_CASTED]], align 4
|
||||
// CHECK13-NEXT: [[TMP6:%.*]] = load i64, ptr [[SIVAR_CASTED]], align 8
|
||||
// CHECK13-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3:[0-9]+]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l122.omp_outlined, ptr [[TMP0]], i64 [[TMP4]], ptr [[TMP1]], ptr [[TMP2]], i64 [[TMP6]])
|
||||
// CHECK13-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK13-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK13-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
|
||||
// CHECK13-NEXT: [[VEC:%.*]] = load ptr, ptr [[TMP1]], align 8
|
||||
// CHECK13-NEXT: [[TMP2:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
|
||||
// CHECK13-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 8
|
||||
// CHECK13-NEXT: store i32 [[TMP3]], ptr [[T_VAR]], align 4
|
||||
// CHECK13-NEXT: [[TMP4:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 2
|
||||
// CHECK13-NEXT: [[S_ARR:%.*]] = load ptr, ptr [[TMP4]], align 8
|
||||
// CHECK13-NEXT: [[TMP5:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 3
|
||||
// CHECK13-NEXT: [[VAR:%.*]] = load ptr, ptr [[TMP5]], align 8
|
||||
// CHECK13-NEXT: [[TMP6:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 4
|
||||
// CHECK13-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 8
|
||||
// CHECK13-NEXT: store i32 [[TMP7]], ptr [[SIVAR]], align 4
|
||||
// CHECK13-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 5
|
||||
// CHECK13-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK13-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
|
||||
// CHECK13-NEXT: [[TMP8:%.*]] = load i32, ptr [[T_VAR]], align 4
|
||||
// CHECK13-NEXT: store i32 [[TMP8]], ptr [[T_VAR_CASTED]], align 4
|
||||
// CHECK13-NEXT: [[TMP9:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8
|
||||
// CHECK13-NEXT: [[TMP10:%.*]] = load i32, ptr [[SIVAR]], align 4
|
||||
// CHECK13-NEXT: store i32 [[TMP10]], ptr [[SIVAR_CASTED]], align 4
|
||||
// CHECK13-NEXT: [[TMP11:%.*]] = load i64, ptr [[SIVAR_CASTED]], align 8
|
||||
// CHECK13-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3:[0-9]+]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l122.omp_outlined, ptr [[VEC]], i64 [[TMP9]], ptr [[S_ARR]], ptr [[VAR]], i64 [[TMP11]])
|
||||
// CHECK13-NEXT: ret void
|
||||
//
|
||||
//
|
||||
@ -3577,7 +3583,7 @@ int main() {
|
||||
// CHECK13-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8
|
||||
// CHECK13-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8
|
||||
// CHECK13-NEXT: store i64 [[SIVAR]], ptr [[SIVAR_ADDR]], align 8
|
||||
// CHECK13-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8, !nonnull [[META7]], !align [[META8]]
|
||||
// CHECK13-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8, !nonnull [[META7:![0-9]+]], !align [[META8:![0-9]+]]
|
||||
// CHECK13-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]]
|
||||
// CHECK13-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]]
|
||||
// CHECK13-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4
|
||||
@ -3861,29 +3867,33 @@ int main() {
|
||||
//
|
||||
//
|
||||
// CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81
|
||||
// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK13-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK13-NEXT: entry:
|
||||
// CHECK13-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK13-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK13-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK13-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK13-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK13-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK13-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
|
||||
// CHECK13-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
|
||||
// CHECK13-NEXT: [[TMP:%.*]] = alloca ptr, align 8
|
||||
// CHECK13-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8
|
||||
// CHECK13-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 8
|
||||
// CHECK13-NEXT: store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8
|
||||
// CHECK13-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8
|
||||
// CHECK13-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8
|
||||
// CHECK13-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK13-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8, !nonnull [[META7]], !align [[META8]]
|
||||
// CHECK13-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]]
|
||||
// CHECK13-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]]
|
||||
// CHECK13-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 8
|
||||
// CHECK13-NEXT: [[TMP3:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4
|
||||
// CHECK13-NEXT: store i32 [[TMP3]], ptr [[T_VAR_CASTED]], align 4
|
||||
// CHECK13-NEXT: [[TMP4:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8
|
||||
// CHECK13-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META7]], !align [[META8]]
|
||||
// CHECK13-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81.omp_outlined, ptr [[TMP0]], i64 [[TMP4]], ptr [[TMP1]], ptr [[TMP5]])
|
||||
// CHECK13-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK13-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK13-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
|
||||
// CHECK13-NEXT: [[VEC:%.*]] = load ptr, ptr [[TMP1]], align 8
|
||||
// CHECK13-NEXT: [[TMP2:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
|
||||
// CHECK13-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 8
|
||||
// CHECK13-NEXT: store i32 [[TMP3]], ptr [[T_VAR]], align 4
|
||||
// CHECK13-NEXT: [[TMP4:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 2
|
||||
// CHECK13-NEXT: [[S_ARR:%.*]] = load ptr, ptr [[TMP4]], align 8
|
||||
// CHECK13-NEXT: [[TMP5:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 3
|
||||
// CHECK13-NEXT: [[VAR:%.*]] = load ptr, ptr [[TMP5]], align 8
|
||||
// CHECK13-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 4
|
||||
// CHECK13-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK13-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
|
||||
// CHECK13-NEXT: store ptr [[VAR]], ptr [[TMP]], align 8
|
||||
// CHECK13-NEXT: [[TMP6:%.*]] = load i32, ptr [[T_VAR]], align 4
|
||||
// CHECK13-NEXT: store i32 [[TMP6]], ptr [[T_VAR_CASTED]], align 4
|
||||
// CHECK13-NEXT: [[TMP7:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8
|
||||
// CHECK13-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META7]], !align [[META8]]
|
||||
// CHECK13-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81.omp_outlined, ptr [[VEC]], i64 [[TMP7]], ptr [[S_ARR]], ptr [[TMP8]])
|
||||
// CHECK13-NEXT: ret void
|
||||
//
|
||||
//
|
||||
@ -4265,32 +4275,38 @@ int main() {
|
||||
//
|
||||
//
|
||||
// CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l122
|
||||
// CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SIVAR:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK15-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK15-NEXT: entry:
|
||||
// CHECK15-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK15-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK15-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK15-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK15-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK15-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK15-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK15-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
|
||||
// CHECK15-NEXT: [[SIVAR:%.*]] = alloca i32, align 4
|
||||
// CHECK15-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 4
|
||||
// CHECK15-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4
|
||||
// CHECK15-NEXT: [[SIVAR_CASTED:%.*]] = alloca i32, align 4
|
||||
// CHECK15-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 4
|
||||
// CHECK15-NEXT: store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 4
|
||||
// CHECK15-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4
|
||||
// CHECK15-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 4
|
||||
// CHECK15-NEXT: store i32 [[SIVAR]], ptr [[SIVAR_ADDR]], align 4
|
||||
// CHECK15-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK15-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4, !nonnull [[META8:![0-9]+]], !align [[META9:![0-9]+]]
|
||||
// CHECK15-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]]
|
||||
// CHECK15-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]]
|
||||
// CHECK15-NEXT: [[TMP3:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4
|
||||
// CHECK15-NEXT: store i32 [[TMP3]], ptr [[T_VAR_CASTED]], align 4
|
||||
// CHECK15-NEXT: [[TMP4:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 4
|
||||
// CHECK15-NEXT: [[TMP5:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 4
|
||||
// CHECK15-NEXT: store i32 [[TMP5]], ptr [[SIVAR_CASTED]], align 4
|
||||
// CHECK15-NEXT: [[TMP6:%.*]] = load i32, ptr [[SIVAR_CASTED]], align 4
|
||||
// CHECK15-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3:[0-9]+]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l122.omp_outlined, ptr [[TMP0]], i32 [[TMP4]], ptr [[TMP1]], ptr [[TMP2]], i32 [[TMP6]])
|
||||
// CHECK15-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK15-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK15-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
|
||||
// CHECK15-NEXT: [[VEC:%.*]] = load ptr, ptr [[TMP1]], align 4
|
||||
// CHECK15-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
|
||||
// CHECK15-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
|
||||
// CHECK15-NEXT: store i32 [[TMP3]], ptr [[T_VAR]], align 4
|
||||
// CHECK15-NEXT: [[TMP4:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 2
|
||||
// CHECK15-NEXT: [[S_ARR:%.*]] = load ptr, ptr [[TMP4]], align 4
|
||||
// CHECK15-NEXT: [[TMP5:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 3
|
||||
// CHECK15-NEXT: [[VAR:%.*]] = load ptr, ptr [[TMP5]], align 4
|
||||
// CHECK15-NEXT: [[TMP6:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 4
|
||||
// CHECK15-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4
|
||||
// CHECK15-NEXT: store i32 [[TMP7]], ptr [[SIVAR]], align 4
|
||||
// CHECK15-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 5
|
||||
// CHECK15-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK15-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
|
||||
// CHECK15-NEXT: [[TMP8:%.*]] = load i32, ptr [[T_VAR]], align 4
|
||||
// CHECK15-NEXT: store i32 [[TMP8]], ptr [[T_VAR_CASTED]], align 4
|
||||
// CHECK15-NEXT: [[TMP9:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 4
|
||||
// CHECK15-NEXT: [[TMP10:%.*]] = load i32, ptr [[SIVAR]], align 4
|
||||
// CHECK15-NEXT: store i32 [[TMP10]], ptr [[SIVAR_CASTED]], align 4
|
||||
// CHECK15-NEXT: [[TMP11:%.*]] = load i32, ptr [[SIVAR_CASTED]], align 4
|
||||
// CHECK15-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3:[0-9]+]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l122.omp_outlined, ptr [[VEC]], i32 [[TMP9]], ptr [[S_ARR]], ptr [[VAR]], i32 [[TMP11]])
|
||||
// CHECK15-NEXT: ret void
|
||||
//
|
||||
//
|
||||
@ -4325,7 +4341,7 @@ int main() {
|
||||
// CHECK15-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4
|
||||
// CHECK15-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 4
|
||||
// CHECK15-NEXT: store i32 [[SIVAR]], ptr [[SIVAR_ADDR]], align 4
|
||||
// CHECK15-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4, !nonnull [[META8]], !align [[META9]]
|
||||
// CHECK15-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4, !nonnull [[META8:![0-9]+]], !align [[META9:![0-9]+]]
|
||||
// CHECK15-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]]
|
||||
// CHECK15-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]]
|
||||
// CHECK15-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4
|
||||
@ -4603,29 +4619,33 @@ int main() {
|
||||
//
|
||||
//
|
||||
// CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81
|
||||
// CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK15-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK15-NEXT: entry:
|
||||
// CHECK15-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK15-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK15-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK15-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK15-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK15-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK15-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
|
||||
// CHECK15-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 4
|
||||
// CHECK15-NEXT: [[TMP:%.*]] = alloca ptr, align 4
|
||||
// CHECK15-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4
|
||||
// CHECK15-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 4
|
||||
// CHECK15-NEXT: store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 4
|
||||
// CHECK15-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4
|
||||
// CHECK15-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 4
|
||||
// CHECK15-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK15-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4, !nonnull [[META8]], !align [[META9]]
|
||||
// CHECK15-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]]
|
||||
// CHECK15-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]]
|
||||
// CHECK15-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 4
|
||||
// CHECK15-NEXT: [[TMP3:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4
|
||||
// CHECK15-NEXT: store i32 [[TMP3]], ptr [[T_VAR_CASTED]], align 4
|
||||
// CHECK15-NEXT: [[TMP4:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 4
|
||||
// CHECK15-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META8]], !align [[META9]]
|
||||
// CHECK15-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81.omp_outlined, ptr [[TMP0]], i32 [[TMP4]], ptr [[TMP1]], ptr [[TMP5]])
|
||||
// CHECK15-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK15-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK15-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
|
||||
// CHECK15-NEXT: [[VEC:%.*]] = load ptr, ptr [[TMP1]], align 4
|
||||
// CHECK15-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
|
||||
// CHECK15-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
|
||||
// CHECK15-NEXT: store i32 [[TMP3]], ptr [[T_VAR]], align 4
|
||||
// CHECK15-NEXT: [[TMP4:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 2
|
||||
// CHECK15-NEXT: [[S_ARR:%.*]] = load ptr, ptr [[TMP4]], align 4
|
||||
// CHECK15-NEXT: [[TMP5:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 3
|
||||
// CHECK15-NEXT: [[VAR:%.*]] = load ptr, ptr [[TMP5]], align 4
|
||||
// CHECK15-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 4
|
||||
// CHECK15-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK15-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
|
||||
// CHECK15-NEXT: store ptr [[VAR]], ptr [[TMP]], align 4
|
||||
// CHECK15-NEXT: [[TMP6:%.*]] = load i32, ptr [[T_VAR]], align 4
|
||||
// CHECK15-NEXT: store i32 [[TMP6]], ptr [[T_VAR_CASTED]], align 4
|
||||
// CHECK15-NEXT: [[TMP7:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 4
|
||||
// CHECK15-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META8]], !align [[META9]]
|
||||
// CHECK15-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81.omp_outlined, ptr [[VEC]], i32 [[TMP7]], ptr [[S_ARR]], ptr [[TMP8]])
|
||||
// CHECK15-NEXT: ret void
|
||||
//
|
||||
//
|
||||
@ -5001,32 +5021,43 @@ int main() {
|
||||
//
|
||||
//
|
||||
// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l99
|
||||
// CHECK17-SAME: (i64 noundef [[G:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SIVAR:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK17-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK17-NEXT: entry:
|
||||
// CHECK17-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK17-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK17-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK17-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK17-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK17-NEXT: [[G:%.*]] = alloca i32, align 4
|
||||
// CHECK17-NEXT: [[G1:%.*]] = alloca i32, align 4
|
||||
// CHECK17-NEXT: [[SIVAR:%.*]] = alloca i32, align 4
|
||||
// CHECK17-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
|
||||
// CHECK17-NEXT: [[TMP:%.*]] = alloca ptr, align 8
|
||||
// CHECK17-NEXT: [[G_CASTED:%.*]] = alloca i64, align 8
|
||||
// CHECK17-NEXT: [[G1_CASTED:%.*]] = alloca i64, align 8
|
||||
// CHECK17-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8
|
||||
// CHECK17-NEXT: store i64 [[G]], ptr [[G_ADDR]], align 8
|
||||
// CHECK17-NEXT: store i64 [[G1]], ptr [[G1_ADDR]], align 8
|
||||
// CHECK17-NEXT: store i64 [[SIVAR]], ptr [[SIVAR_ADDR]], align 8
|
||||
// CHECK17-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK17-NEXT: store ptr [[G1_ADDR]], ptr [[TMP]], align 8
|
||||
// CHECK17-NEXT: [[TMP0:%.*]] = load i32, ptr [[G_ADDR]], align 4
|
||||
// CHECK17-NEXT: store i32 [[TMP0]], ptr [[G_CASTED]], align 4
|
||||
// CHECK17-NEXT: [[TMP1:%.*]] = load i64, ptr [[G_CASTED]], align 8
|
||||
// CHECK17-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META5:![0-9]+]], !align [[META6:![0-9]+]]
|
||||
// CHECK17-NEXT: [[TMP3:%.*]] = load volatile i32, ptr [[TMP2]], align 4
|
||||
// CHECK17-NEXT: store i32 [[TMP3]], ptr [[G1_CASTED]], align 4
|
||||
// CHECK17-NEXT: [[TMP4:%.*]] = load i64, ptr [[G1_CASTED]], align 8
|
||||
// CHECK17-NEXT: [[TMP5:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 4
|
||||
// CHECK17-NEXT: store i32 [[TMP5]], ptr [[SIVAR_CASTED]], align 4
|
||||
// CHECK17-NEXT: [[TMP6:%.*]] = load i64, ptr [[SIVAR_CASTED]], align 8
|
||||
// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3:[0-9]+]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l99.omp_outlined, i64 [[TMP1]], i64 [[TMP4]], i64 [[TMP6]])
|
||||
// CHECK17-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK17-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
|
||||
// CHECK17-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 8
|
||||
// CHECK17-NEXT: store i32 [[TMP2]], ptr [[G]], align 4
|
||||
// CHECK17-NEXT: [[TMP3:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
|
||||
// CHECK17-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 8
|
||||
// CHECK17-NEXT: store i32 [[TMP4]], ptr [[G1]], align 4
|
||||
// CHECK17-NEXT: [[TMP5:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 2
|
||||
// CHECK17-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 8
|
||||
// CHECK17-NEXT: store i32 [[TMP6]], ptr [[SIVAR]], align 4
|
||||
// CHECK17-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 3
|
||||
// CHECK17-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK17-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
|
||||
// CHECK17-NEXT: store ptr [[G1]], ptr [[TMP]], align 8
|
||||
// CHECK17-NEXT: [[TMP7:%.*]] = load i32, ptr [[G]], align 4
|
||||
// CHECK17-NEXT: store i32 [[TMP7]], ptr [[G_CASTED]], align 4
|
||||
// CHECK17-NEXT: [[TMP8:%.*]] = load i64, ptr [[G_CASTED]], align 8
|
||||
// CHECK17-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META5:![0-9]+]], !align [[META6:![0-9]+]]
|
||||
// CHECK17-NEXT: [[TMP10:%.*]] = load volatile i32, ptr [[TMP9]], align 4
|
||||
// CHECK17-NEXT: store i32 [[TMP10]], ptr [[G1_CASTED]], align 4
|
||||
// CHECK17-NEXT: [[TMP11:%.*]] = load i64, ptr [[G1_CASTED]], align 8
|
||||
// CHECK17-NEXT: [[TMP12:%.*]] = load i32, ptr [[SIVAR]], align 4
|
||||
// CHECK17-NEXT: store i32 [[TMP12]], ptr [[SIVAR_CASTED]], align 4
|
||||
// CHECK17-NEXT: [[TMP13:%.*]] = load i64, ptr [[SIVAR_CASTED]], align 8
|
||||
// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3:[0-9]+]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l99.omp_outlined, i64 [[TMP8]], i64 [[TMP11]], i64 [[TMP13]])
|
||||
// CHECK17-NEXT: ret void
|
||||
//
|
||||
//
|
||||
|
||||
@ -2935,10 +2935,15 @@ int main() {
|
||||
//
|
||||
//
|
||||
// CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124
|
||||
// CHECK13-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK13-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK13-NEXT: entry:
|
||||
// CHECK13-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK13-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK13-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK13-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
|
||||
// CHECK13-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK13-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK13-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
|
||||
// CHECK13-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK13-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
|
||||
// CHECK13-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3:[0-9]+]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124.omp_outlined)
|
||||
// CHECK13-NEXT: ret void
|
||||
//
|
||||
@ -3183,10 +3188,15 @@ int main() {
|
||||
//
|
||||
//
|
||||
// CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l80
|
||||
// CHECK13-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK13-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK13-NEXT: entry:
|
||||
// CHECK13-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK13-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK13-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK13-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
|
||||
// CHECK13-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK13-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK13-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
|
||||
// CHECK13-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK13-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
|
||||
// CHECK13-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l80.omp_outlined)
|
||||
// CHECK13-NEXT: ret void
|
||||
//
|
||||
@ -3477,10 +3487,15 @@ int main() {
|
||||
//
|
||||
//
|
||||
// CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124
|
||||
// CHECK15-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK15-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK15-NEXT: entry:
|
||||
// CHECK15-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK15-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK15-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK15-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 4
|
||||
// CHECK15-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK15-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK15-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
|
||||
// CHECK15-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK15-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
|
||||
// CHECK15-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3:[0-9]+]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124.omp_outlined)
|
||||
// CHECK15-NEXT: ret void
|
||||
//
|
||||
@ -3719,10 +3734,15 @@ int main() {
|
||||
//
|
||||
//
|
||||
// CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l80
|
||||
// CHECK15-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK15-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK15-NEXT: entry:
|
||||
// CHECK15-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK15-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK15-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK15-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 4
|
||||
// CHECK15-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK15-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK15-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
|
||||
// CHECK15-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK15-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
|
||||
// CHECK15-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l80.omp_outlined)
|
||||
// CHECK15-NEXT: ret void
|
||||
//
|
||||
@ -4007,10 +4027,15 @@ int main() {
|
||||
//
|
||||
//
|
||||
// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l104
|
||||
// CHECK17-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK17-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK17-NEXT: entry:
|
||||
// CHECK17-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK17-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK17-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK17-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
|
||||
// CHECK17-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK17-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
|
||||
// CHECK17-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK17-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
|
||||
// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3:[0-9]+]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l104.omp_outlined)
|
||||
// CHECK17-NEXT: ret void
|
||||
//
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -1826,28 +1826,38 @@ int target_teams_fun(int *g){
|
||||
//
|
||||
//
|
||||
// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l51
|
||||
// CHECK10-SAME: (i64 noundef [[N:%.*]], ptr noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_1:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK10-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK10-NEXT: entry:
|
||||
// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8
|
||||
// CHECK10-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK10-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK10-NEXT: [[N:%.*]] = alloca i32, align 4
|
||||
// CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
|
||||
// CHECK10-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
|
||||
// CHECK10-NEXT: [[DYN_PTR2:%.*]] = alloca ptr, align 8
|
||||
// CHECK10-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8
|
||||
// CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB3:[0-9]+]])
|
||||
// CHECK10-NEXT: store i64 [[N]], ptr [[N_ADDR]], align 8
|
||||
// CHECK10-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8
|
||||
// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8
|
||||
// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], ptr [[DOTCAPTURE_EXPR__ADDR2]], align 8
|
||||
// CHECK10-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK10-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !nonnull [[META7:![0-9]+]], !align [[META8:![0-9]+]]
|
||||
// CHECK10-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
|
||||
// CHECK10-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR2]], align 4
|
||||
// CHECK10-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB3]], i32 [[TMP0]], i32 [[TMP2]], i32 [[TMP3]])
|
||||
// CHECK10-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4
|
||||
// CHECK10-NEXT: store i32 [[TMP4]], ptr [[N_CASTED]], align 4
|
||||
// CHECK10-NEXT: [[TMP5:%.*]] = load i64, ptr [[N_CASTED]], align 8
|
||||
// CHECK10-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l51.omp_outlined, i64 [[TMP5]], ptr [[TMP1]])
|
||||
// CHECK10-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK10-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK10-NEXT: [[TMP2:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 0
|
||||
// CHECK10-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 8
|
||||
// CHECK10-NEXT: store i32 [[TMP3]], ptr [[N]], align 4
|
||||
// CHECK10-NEXT: [[TMP4:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 1
|
||||
// CHECK10-NEXT: [[A:%.*]] = load ptr, ptr [[TMP4]], align 8
|
||||
// CHECK10-NEXT: [[TMP5:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 2
|
||||
// CHECK10-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 8
|
||||
// CHECK10-NEXT: store i32 [[TMP6]], ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
// CHECK10-NEXT: [[TMP7:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 3
|
||||
// CHECK10-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 8
|
||||
// CHECK10-NEXT: store i32 [[TMP8]], ptr [[DOTCAPTURE_EXPR_1]], align 4
|
||||
// CHECK10-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 4
|
||||
// CHECK10-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK10-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR2]], align 8
|
||||
// CHECK10-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
// CHECK10-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
|
||||
// CHECK10-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB3]], i32 [[TMP0]], i32 [[TMP9]], i32 [[TMP10]])
|
||||
// CHECK10-NEXT: [[TMP11:%.*]] = load i32, ptr [[N]], align 4
|
||||
// CHECK10-NEXT: store i32 [[TMP11]], ptr [[N_CASTED]], align 4
|
||||
// CHECK10-NEXT: [[TMP12:%.*]] = load i64, ptr [[N_CASTED]], align 8
|
||||
// CHECK10-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l51.omp_outlined, i64 [[TMP12]], ptr [[A]])
|
||||
// CHECK10-NEXT: ret void
|
||||
//
|
||||
//
|
||||
@ -1873,7 +1883,7 @@ int target_teams_fun(int *g){
|
||||
// CHECK10-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
|
||||
// CHECK10-NEXT: store i64 [[N]], ptr [[N_ADDR]], align 8
|
||||
// CHECK10-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8
|
||||
// CHECK10-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !nonnull [[META7]], !align [[META8]]
|
||||
// CHECK10-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !nonnull [[META7:![0-9]+]], !align [[META8:![0-9]+]]
|
||||
// CHECK10-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
|
||||
// CHECK10-NEXT: store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
// CHECK10-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
@ -2044,23 +2054,28 @@ int target_teams_fun(int *g){
|
||||
//
|
||||
//
|
||||
// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l57
|
||||
// CHECK10-SAME: (i64 noundef [[N:%.*]], ptr noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], ptr noundef [[G:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK10-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK10-NEXT: entry:
|
||||
// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK10-NEXT: [[G_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK10-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK10-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK10-NEXT: [[N:%.*]] = alloca i32, align 4
|
||||
// CHECK10-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
|
||||
// CHECK10-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8
|
||||
// CHECK10-NEXT: store i64 [[N]], ptr [[N_ADDR]], align 8
|
||||
// CHECK10-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8
|
||||
// CHECK10-NEXT: store ptr [[G]], ptr [[G_ADDR]], align 8
|
||||
// CHECK10-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK10-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !nonnull [[META7]], !align [[META8]]
|
||||
// CHECK10-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
|
||||
// CHECK10-NEXT: store i32 [[TMP1]], ptr [[N_CASTED]], align 4
|
||||
// CHECK10-NEXT: [[TMP2:%.*]] = load i64, ptr [[N_CASTED]], align 8
|
||||
// CHECK10-NEXT: [[TMP3:%.*]] = load ptr, ptr [[G_ADDR]], align 8
|
||||
// CHECK10-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l57.omp_outlined, i64 [[TMP2]], ptr [[TMP0]], ptr [[TMP3]])
|
||||
// CHECK10-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK10-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK10-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
|
||||
// CHECK10-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 8
|
||||
// CHECK10-NEXT: store i32 [[TMP2]], ptr [[N]], align 4
|
||||
// CHECK10-NEXT: [[TMP3:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
|
||||
// CHECK10-NEXT: [[A:%.*]] = load ptr, ptr [[TMP3]], align 8
|
||||
// CHECK10-NEXT: [[G:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 2
|
||||
// CHECK10-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 3
|
||||
// CHECK10-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK10-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
|
||||
// CHECK10-NEXT: [[TMP4:%.*]] = load i32, ptr [[N]], align 4
|
||||
// CHECK10-NEXT: store i32 [[TMP4]], ptr [[N_CASTED]], align 4
|
||||
// CHECK10-NEXT: [[TMP5:%.*]] = load i64, ptr [[N_CASTED]], align 8
|
||||
// CHECK10-NEXT: [[TMP6:%.*]] = load ptr, ptr [[G]], align 8
|
||||
// CHECK10-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l57.omp_outlined, i64 [[TMP5]], ptr [[A]], ptr [[TMP6]])
|
||||
// CHECK10-NEXT: ret void
|
||||
//
|
||||
//
|
||||
@ -2265,28 +2280,38 @@ int target_teams_fun(int *g){
|
||||
//
|
||||
//
|
||||
// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l51
|
||||
// CHECK12-SAME: (i32 noundef [[N:%.*]], ptr noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]], i32 noundef [[DOTCAPTURE_EXPR_1:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK12-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK12-NEXT: entry:
|
||||
// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4
|
||||
// CHECK12-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK12-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK12-NEXT: [[N:%.*]] = alloca i32, align 4
|
||||
// CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
|
||||
// CHECK12-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
|
||||
// CHECK12-NEXT: [[DYN_PTR2:%.*]] = alloca ptr, align 4
|
||||
// CHECK12-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4
|
||||
// CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB3:[0-9]+]])
|
||||
// CHECK12-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
|
||||
// CHECK12-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4
|
||||
// CHECK12-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
|
||||
// CHECK12-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], ptr [[DOTCAPTURE_EXPR__ADDR2]], align 4
|
||||
// CHECK12-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK12-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 4, !nonnull [[META8:![0-9]+]], !align [[META9:![0-9]+]]
|
||||
// CHECK12-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
|
||||
// CHECK12-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR2]], align 4
|
||||
// CHECK12-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB3]], i32 [[TMP0]], i32 [[TMP2]], i32 [[TMP3]])
|
||||
// CHECK12-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4
|
||||
// CHECK12-NEXT: store i32 [[TMP4]], ptr [[N_CASTED]], align 4
|
||||
// CHECK12-NEXT: [[TMP5:%.*]] = load i32, ptr [[N_CASTED]], align 4
|
||||
// CHECK12-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l51.omp_outlined, i32 [[TMP5]], ptr [[TMP1]])
|
||||
// CHECK12-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK12-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK12-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 0
|
||||
// CHECK12-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
|
||||
// CHECK12-NEXT: store i32 [[TMP3]], ptr [[N]], align 4
|
||||
// CHECK12-NEXT: [[TMP4:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 1
|
||||
// CHECK12-NEXT: [[A:%.*]] = load ptr, ptr [[TMP4]], align 4
|
||||
// CHECK12-NEXT: [[TMP5:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 2
|
||||
// CHECK12-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4
|
||||
// CHECK12-NEXT: store i32 [[TMP6]], ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
// CHECK12-NEXT: [[TMP7:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 3
|
||||
// CHECK12-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4
|
||||
// CHECK12-NEXT: store i32 [[TMP8]], ptr [[DOTCAPTURE_EXPR_1]], align 4
|
||||
// CHECK12-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 4
|
||||
// CHECK12-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK12-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR2]], align 4
|
||||
// CHECK12-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
// CHECK12-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
|
||||
// CHECK12-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB3]], i32 [[TMP0]], i32 [[TMP9]], i32 [[TMP10]])
|
||||
// CHECK12-NEXT: [[TMP11:%.*]] = load i32, ptr [[N]], align 4
|
||||
// CHECK12-NEXT: store i32 [[TMP11]], ptr [[N_CASTED]], align 4
|
||||
// CHECK12-NEXT: [[TMP12:%.*]] = load i32, ptr [[N_CASTED]], align 4
|
||||
// CHECK12-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l51.omp_outlined, i32 [[TMP12]], ptr [[A]])
|
||||
// CHECK12-NEXT: ret void
|
||||
//
|
||||
//
|
||||
@ -2312,7 +2337,7 @@ int target_teams_fun(int *g){
|
||||
// CHECK12-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
|
||||
// CHECK12-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
|
||||
// CHECK12-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4
|
||||
// CHECK12-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4, !nonnull [[META8]], !align [[META9]]
|
||||
// CHECK12-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4, !nonnull [[META8:![0-9]+]], !align [[META9:![0-9]+]]
|
||||
// CHECK12-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
|
||||
// CHECK12-NEXT: store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
// CHECK12-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
@ -2478,23 +2503,28 @@ int target_teams_fun(int *g){
|
||||
//
|
||||
//
|
||||
// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l57
|
||||
// CHECK12-SAME: (i32 noundef [[N:%.*]], ptr noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], ptr noundef [[G:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK12-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK12-NEXT: entry:
|
||||
// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK12-NEXT: [[G_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK12-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK12-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK12-NEXT: [[N:%.*]] = alloca i32, align 4
|
||||
// CHECK12-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 4
|
||||
// CHECK12-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4
|
||||
// CHECK12-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
|
||||
// CHECK12-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4
|
||||
// CHECK12-NEXT: store ptr [[G]], ptr [[G_ADDR]], align 4
|
||||
// CHECK12-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK12-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4, !nonnull [[META8]], !align [[META9]]
|
||||
// CHECK12-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
|
||||
// CHECK12-NEXT: store i32 [[TMP1]], ptr [[N_CASTED]], align 4
|
||||
// CHECK12-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_CASTED]], align 4
|
||||
// CHECK12-NEXT: [[TMP3:%.*]] = load ptr, ptr [[G_ADDR]], align 4
|
||||
// CHECK12-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l57.omp_outlined, i32 [[TMP2]], ptr [[TMP0]], ptr [[TMP3]])
|
||||
// CHECK12-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK12-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK12-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
|
||||
// CHECK12-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
|
||||
// CHECK12-NEXT: store i32 [[TMP2]], ptr [[N]], align 4
|
||||
// CHECK12-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
|
||||
// CHECK12-NEXT: [[A:%.*]] = load ptr, ptr [[TMP3]], align 4
|
||||
// CHECK12-NEXT: [[G:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 2
|
||||
// CHECK12-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 3
|
||||
// CHECK12-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK12-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
|
||||
// CHECK12-NEXT: [[TMP4:%.*]] = load i32, ptr [[N]], align 4
|
||||
// CHECK12-NEXT: store i32 [[TMP4]], ptr [[N_CASTED]], align 4
|
||||
// CHECK12-NEXT: [[TMP5:%.*]] = load i32, ptr [[N_CASTED]], align 4
|
||||
// CHECK12-NEXT: [[TMP6:%.*]] = load ptr, ptr [[G]], align 4
|
||||
// CHECK12-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l57.omp_outlined, i32 [[TMP5]], ptr [[A]], ptr [[TMP6]])
|
||||
// CHECK12-NEXT: ret void
|
||||
//
|
||||
//
|
||||
|
||||
@ -1504,10 +1504,15 @@ int main() {
|
||||
//
|
||||
//
|
||||
// CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124
|
||||
// CHECK13-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK13-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK13-NEXT: entry:
|
||||
// CHECK13-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK13-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK13-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK13-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
|
||||
// CHECK13-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK13-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK13-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
|
||||
// CHECK13-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK13-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
|
||||
// CHECK13-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2:[0-9]+]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124.omp_outlined)
|
||||
// CHECK13-NEXT: ret void
|
||||
//
|
||||
@ -1637,10 +1642,15 @@ int main() {
|
||||
//
|
||||
//
|
||||
// CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l80
|
||||
// CHECK13-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK13-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK13-NEXT: entry:
|
||||
// CHECK13-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK13-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK13-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK13-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
|
||||
// CHECK13-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK13-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK13-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
|
||||
// CHECK13-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK13-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
|
||||
// CHECK13-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l80.omp_outlined)
|
||||
// CHECK13-NEXT: ret void
|
||||
//
|
||||
@ -1813,10 +1823,15 @@ int main() {
|
||||
//
|
||||
//
|
||||
// CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124
|
||||
// CHECK15-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK15-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK15-NEXT: entry:
|
||||
// CHECK15-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK15-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK15-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK15-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 4
|
||||
// CHECK15-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK15-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK15-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
|
||||
// CHECK15-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK15-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
|
||||
// CHECK15-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2:[0-9]+]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124.omp_outlined)
|
||||
// CHECK15-NEXT: ret void
|
||||
//
|
||||
@ -1944,10 +1959,15 @@ int main() {
|
||||
//
|
||||
//
|
||||
// CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l80
|
||||
// CHECK15-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK15-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK15-NEXT: entry:
|
||||
// CHECK15-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK15-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK15-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK15-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 4
|
||||
// CHECK15-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK15-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK15-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
|
||||
// CHECK15-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK15-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
|
||||
// CHECK15-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l80.omp_outlined)
|
||||
// CHECK15-NEXT: ret void
|
||||
//
|
||||
@ -2118,10 +2138,15 @@ int main() {
|
||||
//
|
||||
//
|
||||
// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l104
|
||||
// CHECK17-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK17-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK17-NEXT: entry:
|
||||
// CHECK17-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK17-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK17-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK17-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
|
||||
// CHECK17-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK17-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
|
||||
// CHECK17-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK17-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
|
||||
// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2:[0-9]+]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l104.omp_outlined)
|
||||
// CHECK17-NEXT: ret void
|
||||
//
|
||||
|
||||
@ -2368,10 +2368,15 @@ void mapInt128() {
|
||||
//
|
||||
//
|
||||
// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14mapWithPrivatev_l27
|
||||
// CHECK5-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK5-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK5-NEXT: entry:
|
||||
// CHECK5-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK5-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK5-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK5-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
|
||||
// CHECK5-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK5-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
|
||||
// CHECK5-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK5-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
|
||||
// CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1:[0-9]+]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14mapWithPrivatev_l27.omp_outlined)
|
||||
// CHECK5-NEXT: ret void
|
||||
//
|
||||
@ -2389,25 +2394,28 @@ void mapInt128() {
|
||||
//
|
||||
//
|
||||
// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z19mapWithFirstprivatev_l33
|
||||
// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[X:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[Y:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK5-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK5-NEXT: entry:
|
||||
// CHECK5-NEXT: [[X_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK5-NEXT: [[Y_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK5-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK5-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK5-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
|
||||
// CHECK5-NEXT: [[X_CASTED:%.*]] = alloca i64, align 8
|
||||
// CHECK5-NEXT: [[Y_CASTED:%.*]] = alloca i64, align 8
|
||||
// CHECK5-NEXT: store ptr [[X]], ptr [[X_ADDR]], align 8
|
||||
// CHECK5-NEXT: store ptr [[Y]], ptr [[Y_ADDR]], align 8
|
||||
// CHECK5-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[X_ADDR]], align 8, !nonnull [[META25:![0-9]+]], !align [[META26:![0-9]+]]
|
||||
// CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[Y_ADDR]], align 8, !nonnull [[META25]], !align [[META26]]
|
||||
// CHECK5-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP0]], align 4
|
||||
// CHECK5-NEXT: store i32 [[TMP2]], ptr [[X_CASTED]], align 4
|
||||
// CHECK5-NEXT: [[TMP3:%.*]] = load i64, ptr [[X_CASTED]], align 8
|
||||
// CHECK5-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP1]], align 4
|
||||
// CHECK5-NEXT: store i32 [[TMP4]], ptr [[Y_CASTED]], align 4
|
||||
// CHECK5-NEXT: [[TMP5:%.*]] = load i64, ptr [[Y_CASTED]], align 8
|
||||
// CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z19mapWithFirstprivatev_l33.omp_outlined, i64 [[TMP3]], i64 [[TMP5]])
|
||||
// CHECK5-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK5-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
|
||||
// CHECK5-NEXT: [[X:%.*]] = load ptr, ptr [[TMP1]], align 8
|
||||
// CHECK5-NEXT: [[TMP2:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
|
||||
// CHECK5-NEXT: [[Y:%.*]] = load ptr, ptr [[TMP2]], align 8
|
||||
// CHECK5-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 2
|
||||
// CHECK5-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK5-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
|
||||
// CHECK5-NEXT: [[TMP3:%.*]] = load i32, ptr [[X]], align 4
|
||||
// CHECK5-NEXT: store i32 [[TMP3]], ptr [[X_CASTED]], align 4
|
||||
// CHECK5-NEXT: [[TMP4:%.*]] = load i64, ptr [[X_CASTED]], align 8
|
||||
// CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[Y]], align 4
|
||||
// CHECK5-NEXT: store i32 [[TMP5]], ptr [[Y_CASTED]], align 4
|
||||
// CHECK5-NEXT: [[TMP6:%.*]] = load i64, ptr [[Y_CASTED]], align 8
|
||||
// CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z19mapWithFirstprivatev_l33.omp_outlined, i64 [[TMP4]], i64 [[TMP6]])
|
||||
// CHECK5-NEXT: ret void
|
||||
//
|
||||
//
|
||||
@ -2426,17 +2434,20 @@ void mapInt128() {
|
||||
//
|
||||
//
|
||||
// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16mapWithReductionv_l39
|
||||
// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[X:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[Y:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK5-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK5-NEXT: entry:
|
||||
// CHECK5-NEXT: [[X_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK5-NEXT: [[Y_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK5-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK5-NEXT: store ptr [[X]], ptr [[X_ADDR]], align 8
|
||||
// CHECK5-NEXT: store ptr [[Y]], ptr [[Y_ADDR]], align 8
|
||||
// CHECK5-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[X_ADDR]], align 8, !nonnull [[META25]], !align [[META26]]
|
||||
// CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[Y_ADDR]], align 8, !nonnull [[META25]], !align [[META26]]
|
||||
// CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16mapWithReductionv_l39.omp_outlined, ptr [[TMP0]], ptr [[TMP1]])
|
||||
// CHECK5-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK5-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
|
||||
// CHECK5-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK5-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
|
||||
// CHECK5-NEXT: [[X:%.*]] = load ptr, ptr [[TMP1]], align 8
|
||||
// CHECK5-NEXT: [[TMP2:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
|
||||
// CHECK5-NEXT: [[Y:%.*]] = load ptr, ptr [[TMP2]], align 8
|
||||
// CHECK5-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 2
|
||||
// CHECK5-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK5-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
|
||||
// CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16mapWithReductionv_l39.omp_outlined, ptr [[X]], ptr [[Y]])
|
||||
// CHECK5-NEXT: ret void
|
||||
//
|
||||
//
|
||||
@ -2454,7 +2465,7 @@ void mapInt128() {
|
||||
// CHECK5-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
|
||||
// CHECK5-NEXT: store ptr [[X]], ptr [[X_ADDR]], align 8
|
||||
// CHECK5-NEXT: store ptr [[Y]], ptr [[Y_ADDR]], align 8
|
||||
// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[X_ADDR]], align 8, !nonnull [[META25]], !align [[META26]]
|
||||
// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[X_ADDR]], align 8, !nonnull [[META25:![0-9]+]], !align [[META26:![0-9]+]]
|
||||
// CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[Y_ADDR]], align 8, !nonnull [[META25]], !align [[META26]]
|
||||
// CHECK5-NEXT: store i32 0, ptr [[X1]], align 4
|
||||
// CHECK5-NEXT: store i32 0, ptr [[Y2]], align 4
|
||||
@ -2520,18 +2531,22 @@ void mapInt128() {
|
||||
//
|
||||
//
|
||||
// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z7mapFromv_l45
|
||||
// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[X:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK5-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK5-NEXT: entry:
|
||||
// CHECK5-NEXT: [[X_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK5-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK5-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK5-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
|
||||
// CHECK5-NEXT: [[X_CASTED:%.*]] = alloca i64, align 8
|
||||
// CHECK5-NEXT: store ptr [[X]], ptr [[X_ADDR]], align 8
|
||||
// CHECK5-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[X_ADDR]], align 8, !nonnull [[META25]], !align [[META26]]
|
||||
// CHECK5-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
|
||||
// CHECK5-NEXT: store i32 [[TMP1]], ptr [[X_CASTED]], align 4
|
||||
// CHECK5-NEXT: [[TMP2:%.*]] = load i64, ptr [[X_CASTED]], align 8
|
||||
// CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z7mapFromv_l45.omp_outlined, i64 [[TMP2]])
|
||||
// CHECK5-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK5-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
|
||||
// CHECK5-NEXT: [[X:%.*]] = load ptr, ptr [[TMP1]], align 8
|
||||
// CHECK5-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
|
||||
// CHECK5-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK5-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
|
||||
// CHECK5-NEXT: [[TMP2:%.*]] = load i32, ptr [[X]], align 4
|
||||
// CHECK5-NEXT: store i32 [[TMP2]], ptr [[X_CASTED]], align 4
|
||||
// CHECK5-NEXT: [[TMP3:%.*]] = load i64, ptr [[X_CASTED]], align 8
|
||||
// CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z7mapFromv_l45.omp_outlined, i64 [[TMP3]])
|
||||
// CHECK5-NEXT: ret void
|
||||
//
|
||||
//
|
||||
@ -2548,18 +2563,22 @@ void mapInt128() {
|
||||
//
|
||||
//
|
||||
// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5mapTov_l51
|
||||
// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[X:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK5-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK5-NEXT: entry:
|
||||
// CHECK5-NEXT: [[X_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK5-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK5-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK5-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
|
||||
// CHECK5-NEXT: [[X_CASTED:%.*]] = alloca i64, align 8
|
||||
// CHECK5-NEXT: store ptr [[X]], ptr [[X_ADDR]], align 8
|
||||
// CHECK5-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[X_ADDR]], align 8, !nonnull [[META25]], !align [[META26]]
|
||||
// CHECK5-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
|
||||
// CHECK5-NEXT: store i32 [[TMP1]], ptr [[X_CASTED]], align 4
|
||||
// CHECK5-NEXT: [[TMP2:%.*]] = load i64, ptr [[X_CASTED]], align 8
|
||||
// CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5mapTov_l51.omp_outlined, i64 [[TMP2]])
|
||||
// CHECK5-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK5-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
|
||||
// CHECK5-NEXT: [[X:%.*]] = load ptr, ptr [[TMP1]], align 8
|
||||
// CHECK5-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
|
||||
// CHECK5-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK5-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
|
||||
// CHECK5-NEXT: [[TMP2:%.*]] = load i32, ptr [[X]], align 4
|
||||
// CHECK5-NEXT: store i32 [[TMP2]], ptr [[X_CASTED]], align 4
|
||||
// CHECK5-NEXT: [[TMP3:%.*]] = load i64, ptr [[X_CASTED]], align 8
|
||||
// CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5mapTov_l51.omp_outlined, i64 [[TMP3]])
|
||||
// CHECK5-NEXT: ret void
|
||||
//
|
||||
//
|
||||
@ -2576,18 +2595,22 @@ void mapInt128() {
|
||||
//
|
||||
//
|
||||
// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8mapAllocv_l57
|
||||
// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[X:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK5-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK5-NEXT: entry:
|
||||
// CHECK5-NEXT: [[X_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK5-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK5-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK5-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
|
||||
// CHECK5-NEXT: [[X_CASTED:%.*]] = alloca i64, align 8
|
||||
// CHECK5-NEXT: store ptr [[X]], ptr [[X_ADDR]], align 8
|
||||
// CHECK5-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[X_ADDR]], align 8, !nonnull [[META25]], !align [[META26]]
|
||||
// CHECK5-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
|
||||
// CHECK5-NEXT: store i32 [[TMP1]], ptr [[X_CASTED]], align 4
|
||||
// CHECK5-NEXT: [[TMP2:%.*]] = load i64, ptr [[X_CASTED]], align 8
|
||||
// CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8mapAllocv_l57.omp_outlined, i64 [[TMP2]])
|
||||
// CHECK5-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK5-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
|
||||
// CHECK5-NEXT: [[X:%.*]] = load ptr, ptr [[TMP1]], align 8
|
||||
// CHECK5-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
|
||||
// CHECK5-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK5-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
|
||||
// CHECK5-NEXT: [[TMP2:%.*]] = load i32, ptr [[X]], align 4
|
||||
// CHECK5-NEXT: store i32 [[TMP2]], ptr [[X_CASTED]], align 4
|
||||
// CHECK5-NEXT: [[TMP3:%.*]] = load i64, ptr [[X_CASTED]], align 8
|
||||
// CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8mapAllocv_l57.omp_outlined, i64 [[TMP3]])
|
||||
// CHECK5-NEXT: ret void
|
||||
//
|
||||
//
|
||||
@ -2604,17 +2627,20 @@ void mapInt128() {
|
||||
//
|
||||
//
|
||||
// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8mapArrayv_l63
|
||||
// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(352) [[Y:%.*]], ptr noundef nonnull align 4 dereferenceable(396) [[Z:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK5-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK5-NEXT: entry:
|
||||
// CHECK5-NEXT: [[Y_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK5-NEXT: [[Z_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK5-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK5-NEXT: store ptr [[Y]], ptr [[Y_ADDR]], align 8
|
||||
// CHECK5-NEXT: store ptr [[Z]], ptr [[Z_ADDR]], align 8
|
||||
// CHECK5-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[Y_ADDR]], align 8, !nonnull [[META25]], !align [[META26]]
|
||||
// CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[Z_ADDR]], align 8, !nonnull [[META25]], !align [[META26]]
|
||||
// CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8mapArrayv_l63.omp_outlined, ptr [[TMP0]], ptr [[TMP1]])
|
||||
// CHECK5-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK5-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
|
||||
// CHECK5-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK5-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
|
||||
// CHECK5-NEXT: [[Y:%.*]] = load ptr, ptr [[TMP1]], align 8
|
||||
// CHECK5-NEXT: [[TMP2:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
|
||||
// CHECK5-NEXT: [[Z:%.*]] = load ptr, ptr [[TMP2]], align 8
|
||||
// CHECK5-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 2
|
||||
// CHECK5-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK5-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
|
||||
// CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8mapArrayv_l63.omp_outlined, ptr [[Y]], ptr [[Z]])
|
||||
// CHECK5-NEXT: ret void
|
||||
//
|
||||
//
|
||||
@ -2726,17 +2752,20 @@ void mapInt128() {
|
||||
//
|
||||
//
|
||||
// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8mapArrayv_l65
|
||||
// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(352) [[Y:%.*]], ptr noundef nonnull align 4 dereferenceable(396) [[Z:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK5-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK5-NEXT: entry:
|
||||
// CHECK5-NEXT: [[Y_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK5-NEXT: [[Z_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK5-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK5-NEXT: store ptr [[Y]], ptr [[Y_ADDR]], align 8
|
||||
// CHECK5-NEXT: store ptr [[Z]], ptr [[Z_ADDR]], align 8
|
||||
// CHECK5-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[Y_ADDR]], align 8, !nonnull [[META25]], !align [[META26]]
|
||||
// CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[Z_ADDR]], align 8, !nonnull [[META25]], !align [[META26]]
|
||||
// CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8mapArrayv_l65.omp_outlined, ptr [[TMP0]], ptr [[TMP1]])
|
||||
// CHECK5-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK5-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
|
||||
// CHECK5-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK5-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
|
||||
// CHECK5-NEXT: [[Y:%.*]] = load ptr, ptr [[TMP1]], align 8
|
||||
// CHECK5-NEXT: [[TMP2:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
|
||||
// CHECK5-NEXT: [[Z:%.*]] = load ptr, ptr [[TMP2]], align 8
|
||||
// CHECK5-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 2
|
||||
// CHECK5-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK5-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
|
||||
// CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8mapArrayv_l65.omp_outlined, ptr [[Y]], ptr [[Z]])
|
||||
// CHECK5-NEXT: ret void
|
||||
//
|
||||
//
|
||||
@ -2848,17 +2877,20 @@ void mapInt128() {
|
||||
//
|
||||
//
|
||||
// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9mapInt128v_l72
|
||||
// CHECK5-SAME: (ptr noundef nonnull align 16 dereferenceable(16) [[Y:%.*]], ptr noundef nonnull align 16 dereferenceable(16) [[Z:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK5-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK5-NEXT: entry:
|
||||
// CHECK5-NEXT: [[Y_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK5-NEXT: [[Z_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK5-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK5-NEXT: store ptr [[Y]], ptr [[Y_ADDR]], align 8
|
||||
// CHECK5-NEXT: store ptr [[Z]], ptr [[Z_ADDR]], align 8
|
||||
// CHECK5-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[Y_ADDR]], align 8, !nonnull [[META25]], !align [[META27:![0-9]+]]
|
||||
// CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[Z_ADDR]], align 8, !nonnull [[META25]], !align [[META27]]
|
||||
// CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9mapInt128v_l72.omp_outlined, ptr [[TMP0]], ptr [[TMP1]])
|
||||
// CHECK5-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK5-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
|
||||
// CHECK5-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK5-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
|
||||
// CHECK5-NEXT: [[Y:%.*]] = load ptr, ptr [[TMP1]], align 8
|
||||
// CHECK5-NEXT: [[TMP2:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
|
||||
// CHECK5-NEXT: [[Z:%.*]] = load ptr, ptr [[TMP2]], align 8
|
||||
// CHECK5-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 2
|
||||
// CHECK5-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK5-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
|
||||
// CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9mapInt128v_l72.omp_outlined, ptr [[Y]], ptr [[Z]])
|
||||
// CHECK5-NEXT: ret void
|
||||
//
|
||||
//
|
||||
@ -2880,7 +2912,7 @@ void mapInt128() {
|
||||
// CHECK5-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
|
||||
// CHECK5-NEXT: store ptr [[Y]], ptr [[Y_ADDR]], align 8
|
||||
// CHECK5-NEXT: store ptr [[Z]], ptr [[Z_ADDR]], align 8
|
||||
// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[Y_ADDR]], align 8, !nonnull [[META25]], !align [[META27]]
|
||||
// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[Y_ADDR]], align 8, !nonnull [[META25]], !align [[META27:![0-9]+]]
|
||||
// CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[Z_ADDR]], align 8, !nonnull [[META25]], !align [[META27]]
|
||||
// CHECK5-NEXT: [[TMP2:%.*]] = load i128, ptr [[TMP0]], align 16
|
||||
// CHECK5-NEXT: store i128 [[TMP2]], ptr [[Y1]], align 16
|
||||
@ -2942,17 +2974,20 @@ void mapInt128() {
|
||||
//
|
||||
//
|
||||
// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9mapInt128v_l74
|
||||
// CHECK5-SAME: (ptr noundef nonnull align 16 dereferenceable(16) [[Y:%.*]], ptr noundef nonnull align 16 dereferenceable(16) [[Z:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK5-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK5-NEXT: entry:
|
||||
// CHECK5-NEXT: [[Y_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK5-NEXT: [[Z_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK5-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK5-NEXT: store ptr [[Y]], ptr [[Y_ADDR]], align 8
|
||||
// CHECK5-NEXT: store ptr [[Z]], ptr [[Z_ADDR]], align 8
|
||||
// CHECK5-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[Y_ADDR]], align 8, !nonnull [[META25]], !align [[META27]]
|
||||
// CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[Z_ADDR]], align 8, !nonnull [[META25]], !align [[META27]]
|
||||
// CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9mapInt128v_l74.omp_outlined, ptr [[TMP0]], ptr [[TMP1]])
|
||||
// CHECK5-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK5-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
|
||||
// CHECK5-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK5-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
|
||||
// CHECK5-NEXT: [[Y:%.*]] = load ptr, ptr [[TMP1]], align 8
|
||||
// CHECK5-NEXT: [[TMP2:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
|
||||
// CHECK5-NEXT: [[Z:%.*]] = load ptr, ptr [[TMP2]], align 8
|
||||
// CHECK5-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 2
|
||||
// CHECK5-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK5-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
|
||||
// CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9mapInt128v_l74.omp_outlined, ptr [[Y]], ptr [[Z]])
|
||||
// CHECK5-NEXT: ret void
|
||||
//
|
||||
//
|
||||
@ -3036,10 +3071,15 @@ void mapInt128() {
|
||||
//
|
||||
//
|
||||
// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14mapWithPrivatev_l27
|
||||
// CHECK7-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK7-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK7-NEXT: entry:
|
||||
// CHECK7-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK7-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK7-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK7-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 4
|
||||
// CHECK7-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK7-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
|
||||
// CHECK7-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK7-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
|
||||
// CHECK7-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1:[0-9]+]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14mapWithPrivatev_l27.omp_outlined)
|
||||
// CHECK7-NEXT: ret void
|
||||
//
|
||||
@ -3057,25 +3097,28 @@ void mapInt128() {
|
||||
//
|
||||
//
|
||||
// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z19mapWithFirstprivatev_l33
|
||||
// CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[X:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[Y:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK7-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK7-NEXT: entry:
|
||||
// CHECK7-NEXT: [[X_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK7-NEXT: [[Y_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK7-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK7-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK7-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 4
|
||||
// CHECK7-NEXT: [[X_CASTED:%.*]] = alloca i32, align 4
|
||||
// CHECK7-NEXT: [[Y_CASTED:%.*]] = alloca i32, align 4
|
||||
// CHECK7-NEXT: store ptr [[X]], ptr [[X_ADDR]], align 4
|
||||
// CHECK7-NEXT: store ptr [[Y]], ptr [[Y_ADDR]], align 4
|
||||
// CHECK7-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[X_ADDR]], align 4, !nonnull [[META22:![0-9]+]], !align [[META23:![0-9]+]]
|
||||
// CHECK7-NEXT: [[TMP1:%.*]] = load ptr, ptr [[Y_ADDR]], align 4, !nonnull [[META22]], !align [[META23]]
|
||||
// CHECK7-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP0]], align 4
|
||||
// CHECK7-NEXT: store i32 [[TMP2]], ptr [[X_CASTED]], align 4
|
||||
// CHECK7-NEXT: [[TMP3:%.*]] = load i32, ptr [[X_CASTED]], align 4
|
||||
// CHECK7-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP1]], align 4
|
||||
// CHECK7-NEXT: store i32 [[TMP4]], ptr [[Y_CASTED]], align 4
|
||||
// CHECK7-NEXT: [[TMP5:%.*]] = load i32, ptr [[Y_CASTED]], align 4
|
||||
// CHECK7-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z19mapWithFirstprivatev_l33.omp_outlined, i32 [[TMP3]], i32 [[TMP5]])
|
||||
// CHECK7-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK7-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
|
||||
// CHECK7-NEXT: [[X:%.*]] = load ptr, ptr [[TMP1]], align 4
|
||||
// CHECK7-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
|
||||
// CHECK7-NEXT: [[Y:%.*]] = load ptr, ptr [[TMP2]], align 4
|
||||
// CHECK7-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 2
|
||||
// CHECK7-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK7-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
|
||||
// CHECK7-NEXT: [[TMP3:%.*]] = load i32, ptr [[X]], align 4
|
||||
// CHECK7-NEXT: store i32 [[TMP3]], ptr [[X_CASTED]], align 4
|
||||
// CHECK7-NEXT: [[TMP4:%.*]] = load i32, ptr [[X_CASTED]], align 4
|
||||
// CHECK7-NEXT: [[TMP5:%.*]] = load i32, ptr [[Y]], align 4
|
||||
// CHECK7-NEXT: store i32 [[TMP5]], ptr [[Y_CASTED]], align 4
|
||||
// CHECK7-NEXT: [[TMP6:%.*]] = load i32, ptr [[Y_CASTED]], align 4
|
||||
// CHECK7-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z19mapWithFirstprivatev_l33.omp_outlined, i32 [[TMP4]], i32 [[TMP6]])
|
||||
// CHECK7-NEXT: ret void
|
||||
//
|
||||
//
|
||||
@ -3094,17 +3137,20 @@ void mapInt128() {
|
||||
//
|
||||
//
|
||||
// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16mapWithReductionv_l39
|
||||
// CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[X:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[Y:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK7-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK7-NEXT: entry:
|
||||
// CHECK7-NEXT: [[X_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK7-NEXT: [[Y_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK7-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK7-NEXT: store ptr [[X]], ptr [[X_ADDR]], align 4
|
||||
// CHECK7-NEXT: store ptr [[Y]], ptr [[Y_ADDR]], align 4
|
||||
// CHECK7-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[X_ADDR]], align 4, !nonnull [[META22]], !align [[META23]]
|
||||
// CHECK7-NEXT: [[TMP1:%.*]] = load ptr, ptr [[Y_ADDR]], align 4, !nonnull [[META22]], !align [[META23]]
|
||||
// CHECK7-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16mapWithReductionv_l39.omp_outlined, ptr [[TMP0]], ptr [[TMP1]])
|
||||
// CHECK7-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK7-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 4
|
||||
// CHECK7-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK7-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
|
||||
// CHECK7-NEXT: [[X:%.*]] = load ptr, ptr [[TMP1]], align 4
|
||||
// CHECK7-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
|
||||
// CHECK7-NEXT: [[Y:%.*]] = load ptr, ptr [[TMP2]], align 4
|
||||
// CHECK7-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 2
|
||||
// CHECK7-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK7-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
|
||||
// CHECK7-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16mapWithReductionv_l39.omp_outlined, ptr [[X]], ptr [[Y]])
|
||||
// CHECK7-NEXT: ret void
|
||||
//
|
||||
//
|
||||
@ -3122,7 +3168,7 @@ void mapInt128() {
|
||||
// CHECK7-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
|
||||
// CHECK7-NEXT: store ptr [[X]], ptr [[X_ADDR]], align 4
|
||||
// CHECK7-NEXT: store ptr [[Y]], ptr [[Y_ADDR]], align 4
|
||||
// CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[X_ADDR]], align 4, !nonnull [[META22]], !align [[META23]]
|
||||
// CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[X_ADDR]], align 4, !nonnull [[META22:![0-9]+]], !align [[META23:![0-9]+]]
|
||||
// CHECK7-NEXT: [[TMP1:%.*]] = load ptr, ptr [[Y_ADDR]], align 4, !nonnull [[META22]], !align [[META23]]
|
||||
// CHECK7-NEXT: store i32 0, ptr [[X1]], align 4
|
||||
// CHECK7-NEXT: store i32 0, ptr [[Y2]], align 4
|
||||
@ -3188,18 +3234,22 @@ void mapInt128() {
|
||||
//
|
||||
//
|
||||
// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z7mapFromv_l45
|
||||
// CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[X:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK7-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK7-NEXT: entry:
|
||||
// CHECK7-NEXT: [[X_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK7-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK7-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK7-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 4
|
||||
// CHECK7-NEXT: [[X_CASTED:%.*]] = alloca i32, align 4
|
||||
// CHECK7-NEXT: store ptr [[X]], ptr [[X_ADDR]], align 4
|
||||
// CHECK7-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[X_ADDR]], align 4, !nonnull [[META22]], !align [[META23]]
|
||||
// CHECK7-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
|
||||
// CHECK7-NEXT: store i32 [[TMP1]], ptr [[X_CASTED]], align 4
|
||||
// CHECK7-NEXT: [[TMP2:%.*]] = load i32, ptr [[X_CASTED]], align 4
|
||||
// CHECK7-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z7mapFromv_l45.omp_outlined, i32 [[TMP2]])
|
||||
// CHECK7-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK7-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
|
||||
// CHECK7-NEXT: [[X:%.*]] = load ptr, ptr [[TMP1]], align 4
|
||||
// CHECK7-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
|
||||
// CHECK7-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK7-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
|
||||
// CHECK7-NEXT: [[TMP2:%.*]] = load i32, ptr [[X]], align 4
|
||||
// CHECK7-NEXT: store i32 [[TMP2]], ptr [[X_CASTED]], align 4
|
||||
// CHECK7-NEXT: [[TMP3:%.*]] = load i32, ptr [[X_CASTED]], align 4
|
||||
// CHECK7-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z7mapFromv_l45.omp_outlined, i32 [[TMP3]])
|
||||
// CHECK7-NEXT: ret void
|
||||
//
|
||||
//
|
||||
@ -3216,18 +3266,22 @@ void mapInt128() {
|
||||
//
|
||||
//
|
||||
// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5mapTov_l51
|
||||
// CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[X:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK7-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK7-NEXT: entry:
|
||||
// CHECK7-NEXT: [[X_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK7-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK7-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK7-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 4
|
||||
// CHECK7-NEXT: [[X_CASTED:%.*]] = alloca i32, align 4
|
||||
// CHECK7-NEXT: store ptr [[X]], ptr [[X_ADDR]], align 4
|
||||
// CHECK7-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[X_ADDR]], align 4, !nonnull [[META22]], !align [[META23]]
|
||||
// CHECK7-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
|
||||
// CHECK7-NEXT: store i32 [[TMP1]], ptr [[X_CASTED]], align 4
|
||||
// CHECK7-NEXT: [[TMP2:%.*]] = load i32, ptr [[X_CASTED]], align 4
|
||||
// CHECK7-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5mapTov_l51.omp_outlined, i32 [[TMP2]])
|
||||
// CHECK7-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK7-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
|
||||
// CHECK7-NEXT: [[X:%.*]] = load ptr, ptr [[TMP1]], align 4
|
||||
// CHECK7-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
|
||||
// CHECK7-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK7-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
|
||||
// CHECK7-NEXT: [[TMP2:%.*]] = load i32, ptr [[X]], align 4
|
||||
// CHECK7-NEXT: store i32 [[TMP2]], ptr [[X_CASTED]], align 4
|
||||
// CHECK7-NEXT: [[TMP3:%.*]] = load i32, ptr [[X_CASTED]], align 4
|
||||
// CHECK7-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5mapTov_l51.omp_outlined, i32 [[TMP3]])
|
||||
// CHECK7-NEXT: ret void
|
||||
//
|
||||
//
|
||||
@ -3244,18 +3298,22 @@ void mapInt128() {
|
||||
//
|
||||
//
|
||||
// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8mapAllocv_l57
|
||||
// CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[X:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK7-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK7-NEXT: entry:
|
||||
// CHECK7-NEXT: [[X_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK7-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK7-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK7-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 4
|
||||
// CHECK7-NEXT: [[X_CASTED:%.*]] = alloca i32, align 4
|
||||
// CHECK7-NEXT: store ptr [[X]], ptr [[X_ADDR]], align 4
|
||||
// CHECK7-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[X_ADDR]], align 4, !nonnull [[META22]], !align [[META23]]
|
||||
// CHECK7-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
|
||||
// CHECK7-NEXT: store i32 [[TMP1]], ptr [[X_CASTED]], align 4
|
||||
// CHECK7-NEXT: [[TMP2:%.*]] = load i32, ptr [[X_CASTED]], align 4
|
||||
// CHECK7-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8mapAllocv_l57.omp_outlined, i32 [[TMP2]])
|
||||
// CHECK7-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK7-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
|
||||
// CHECK7-NEXT: [[X:%.*]] = load ptr, ptr [[TMP1]], align 4
|
||||
// CHECK7-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
|
||||
// CHECK7-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK7-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
|
||||
// CHECK7-NEXT: [[TMP2:%.*]] = load i32, ptr [[X]], align 4
|
||||
// CHECK7-NEXT: store i32 [[TMP2]], ptr [[X_CASTED]], align 4
|
||||
// CHECK7-NEXT: [[TMP3:%.*]] = load i32, ptr [[X_CASTED]], align 4
|
||||
// CHECK7-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8mapAllocv_l57.omp_outlined, i32 [[TMP3]])
|
||||
// CHECK7-NEXT: ret void
|
||||
//
|
||||
//
|
||||
@ -3272,17 +3330,20 @@ void mapInt128() {
|
||||
//
|
||||
//
|
||||
// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8mapArrayv_l63
|
||||
// CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(352) [[Y:%.*]], ptr noundef nonnull align 4 dereferenceable(396) [[Z:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK7-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK7-NEXT: entry:
|
||||
// CHECK7-NEXT: [[Y_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK7-NEXT: [[Z_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK7-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK7-NEXT: store ptr [[Y]], ptr [[Y_ADDR]], align 4
|
||||
// CHECK7-NEXT: store ptr [[Z]], ptr [[Z_ADDR]], align 4
|
||||
// CHECK7-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[Y_ADDR]], align 4, !nonnull [[META22]], !align [[META23]]
|
||||
// CHECK7-NEXT: [[TMP1:%.*]] = load ptr, ptr [[Z_ADDR]], align 4, !nonnull [[META22]], !align [[META23]]
|
||||
// CHECK7-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8mapArrayv_l63.omp_outlined, ptr [[TMP0]], ptr [[TMP1]])
|
||||
// CHECK7-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK7-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 4
|
||||
// CHECK7-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK7-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
|
||||
// CHECK7-NEXT: [[Y:%.*]] = load ptr, ptr [[TMP1]], align 4
|
||||
// CHECK7-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
|
||||
// CHECK7-NEXT: [[Z:%.*]] = load ptr, ptr [[TMP2]], align 4
|
||||
// CHECK7-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 2
|
||||
// CHECK7-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK7-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
|
||||
// CHECK7-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8mapArrayv_l63.omp_outlined, ptr [[Y]], ptr [[Z]])
|
||||
// CHECK7-NEXT: ret void
|
||||
//
|
||||
//
|
||||
@ -3394,17 +3455,20 @@ void mapInt128() {
|
||||
//
|
||||
//
|
||||
// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8mapArrayv_l65
|
||||
// CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(352) [[Y:%.*]], ptr noundef nonnull align 4 dereferenceable(396) [[Z:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK7-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK7-NEXT: entry:
|
||||
// CHECK7-NEXT: [[Y_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK7-NEXT: [[Z_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK7-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK7-NEXT: store ptr [[Y]], ptr [[Y_ADDR]], align 4
|
||||
// CHECK7-NEXT: store ptr [[Z]], ptr [[Z_ADDR]], align 4
|
||||
// CHECK7-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[Y_ADDR]], align 4, !nonnull [[META22]], !align [[META23]]
|
||||
// CHECK7-NEXT: [[TMP1:%.*]] = load ptr, ptr [[Z_ADDR]], align 4, !nonnull [[META22]], !align [[META23]]
|
||||
// CHECK7-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8mapArrayv_l65.omp_outlined, ptr [[TMP0]], ptr [[TMP1]])
|
||||
// CHECK7-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK7-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 4
|
||||
// CHECK7-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK7-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
|
||||
// CHECK7-NEXT: [[Y:%.*]] = load ptr, ptr [[TMP1]], align 4
|
||||
// CHECK7-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
|
||||
// CHECK7-NEXT: [[Z:%.*]] = load ptr, ptr [[TMP2]], align 4
|
||||
// CHECK7-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 2
|
||||
// CHECK7-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK7-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
|
||||
// CHECK7-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8mapArrayv_l65.omp_outlined, ptr [[Y]], ptr [[Z]])
|
||||
// CHECK7-NEXT: ret void
|
||||
//
|
||||
//
|
||||
|
||||
@ -1437,15 +1437,22 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104
|
||||
// CHECK9-SAME: (i64 noundef [[DOTCAPTURE_EXPR_:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK9-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK9-NEXT: entry:
|
||||
// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
|
||||
// CHECK9-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]])
|
||||
// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8
|
||||
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
|
||||
// CHECK9-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0)
|
||||
// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 0
|
||||
// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 8
|
||||
// CHECK9-NEXT: store i32 [[TMP3]], ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 1
|
||||
// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
|
||||
// CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
// CHECK9-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP4]], i32 0)
|
||||
// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104.omp_outlined)
|
||||
// CHECK9-NEXT: ret void
|
||||
//
|
||||
@ -1461,15 +1468,22 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108
|
||||
// CHECK9-SAME: (i64 noundef [[DOTCAPTURE_EXPR_:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK9-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK9-NEXT: entry:
|
||||
// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
|
||||
// CHECK9-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
|
||||
// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8
|
||||
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
|
||||
// CHECK9-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0)
|
||||
// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 0
|
||||
// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 8
|
||||
// CHECK9-NEXT: store i32 [[TMP3]], ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 1
|
||||
// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
|
||||
// CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
// CHECK9-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP4]], i32 0)
|
||||
// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108.omp_outlined)
|
||||
// CHECK9-NEXT: ret void
|
||||
//
|
||||
@ -1485,25 +1499,33 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121
|
||||
// CHECK9-SAME: (ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK9-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK9-NEXT: entry:
|
||||
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[B:%.*]] = alloca i32, align 4
|
||||
// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
|
||||
// CHECK9-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
|
||||
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
|
||||
// CHECK9-NEXT: store i64 [[B]], ptr [[B_ADDR]], align 8
|
||||
// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8
|
||||
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
|
||||
// CHECK9-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0)
|
||||
// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[B_ADDR]], align 4
|
||||
// CHECK9-NEXT: store i32 [[TMP3]], ptr [[B_CASTED]], align 4
|
||||
// CHECK9-NEXT: [[TMP4:%.*]] = load i64, ptr [[B_CASTED]], align 8
|
||||
// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.omp_outlined, ptr [[TMP1]], i64 [[TMP4]])
|
||||
// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 0
|
||||
// CHECK9-NEXT: [[THIS:%.*]] = load ptr, ptr [[TMP2]], align 8
|
||||
// CHECK9-NEXT: [[TMP3:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 1
|
||||
// CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 8
|
||||
// CHECK9-NEXT: store i32 [[TMP4]], ptr [[B]], align 4
|
||||
// CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 2
|
||||
// CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 8
|
||||
// CHECK9-NEXT: store i32 [[TMP6]], ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 3
|
||||
// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
|
||||
// CHECK9-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
// CHECK9-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP7]], i32 0)
|
||||
// CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[B]], align 4
|
||||
// CHECK9-NEXT: store i32 [[TMP8]], ptr [[B_CASTED]], align 4
|
||||
// CHECK9-NEXT: [[TMP9:%.*]] = load i64, ptr [[B_CASTED]], align 8
|
||||
// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.omp_outlined, ptr [[THIS]], i64 [[TMP9]])
|
||||
// CHECK9-NEXT: ret void
|
||||
//
|
||||
//
|
||||
@ -1528,16 +1550,20 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126
|
||||
// CHECK9-SAME: (ptr noundef [[THIS:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK9-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK9-NEXT: entry:
|
||||
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
|
||||
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
|
||||
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
|
||||
// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 0
|
||||
// CHECK9-NEXT: [[THIS:%.*]] = load ptr, ptr [[TMP2]], align 8
|
||||
// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 1
|
||||
// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
|
||||
// CHECK9-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 1024, i32 0)
|
||||
// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126.omp_outlined, ptr [[TMP1]])
|
||||
// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126.omp_outlined, ptr [[THIS]])
|
||||
// CHECK9-NEXT: ret void
|
||||
//
|
||||
//
|
||||
@ -1557,11 +1583,16 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88
|
||||
// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK9-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK9-NEXT: entry:
|
||||
// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
|
||||
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 0
|
||||
// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
|
||||
// CHECK9-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 20, i32 0)
|
||||
// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88.omp_outlined)
|
||||
// CHECK9-NEXT: ret void
|
||||
@ -1578,29 +1609,40 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93
|
||||
// CHECK9-SAME: (i64 noundef [[A:%.*]], i64 noundef [[B:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK9-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK9-NEXT: entry:
|
||||
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[A:%.*]] = alloca i32, align 4
|
||||
// CHECK9-NEXT: [[B:%.*]] = alloca i16, align 2
|
||||
// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2
|
||||
// CHECK9-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
|
||||
// CHECK9-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8
|
||||
// CHECK9-NEXT: store i64 [[B]], ptr [[B_ADDR]], align 8
|
||||
// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8
|
||||
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP1:%.*]] = load i16, ptr [[DOTCAPTURE_EXPR__ADDR]], align 2
|
||||
// CHECK9-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32
|
||||
// CHECK9-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0)
|
||||
// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[A_ADDR]], align 4
|
||||
// CHECK9-NEXT: store i32 [[TMP3]], ptr [[A_CASTED]], align 4
|
||||
// CHECK9-NEXT: [[TMP4:%.*]] = load i64, ptr [[A_CASTED]], align 8
|
||||
// CHECK9-NEXT: [[TMP5:%.*]] = load i16, ptr [[B_ADDR]], align 2
|
||||
// CHECK9-NEXT: store i16 [[TMP5]], ptr [[B_CASTED]], align 2
|
||||
// CHECK9-NEXT: [[TMP6:%.*]] = load i64, ptr [[B_CASTED]], align 8
|
||||
// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93.omp_outlined, i64 [[TMP4]], i64 [[TMP6]])
|
||||
// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 0
|
||||
// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 8
|
||||
// CHECK9-NEXT: store i32 [[TMP3]], ptr [[A]], align 4
|
||||
// CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 1
|
||||
// CHECK9-NEXT: [[TMP5:%.*]] = load i16, ptr [[TMP4]], align 8
|
||||
// CHECK9-NEXT: store i16 [[TMP5]], ptr [[B]], align 2
|
||||
// CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 2
|
||||
// CHECK9-NEXT: [[TMP7:%.*]] = load i16, ptr [[TMP6]], align 8
|
||||
// CHECK9-NEXT: store i16 [[TMP7]], ptr [[DOTCAPTURE_EXPR_]], align 2
|
||||
// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 3
|
||||
// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
|
||||
// CHECK9-NEXT: [[TMP8:%.*]] = load i16, ptr [[DOTCAPTURE_EXPR_]], align 2
|
||||
// CHECK9-NEXT: [[TMP9:%.*]] = sext i16 [[TMP8]] to i32
|
||||
// CHECK9-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP9]], i32 0)
|
||||
// CHECK9-NEXT: [[TMP10:%.*]] = load i32, ptr [[A]], align 4
|
||||
// CHECK9-NEXT: store i32 [[TMP10]], ptr [[A_CASTED]], align 4
|
||||
// CHECK9-NEXT: [[TMP11:%.*]] = load i64, ptr [[A_CASTED]], align 8
|
||||
// CHECK9-NEXT: [[TMP12:%.*]] = load i16, ptr [[B]], align 2
|
||||
// CHECK9-NEXT: store i16 [[TMP12]], ptr [[B_CASTED]], align 2
|
||||
// CHECK9-NEXT: [[TMP13:%.*]] = load i64, ptr [[B_CASTED]], align 8
|
||||
// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93.omp_outlined, i64 [[TMP11]], i64 [[TMP13]])
|
||||
// CHECK9-NEXT: ret void
|
||||
//
|
||||
//
|
||||
@ -1624,15 +1666,22 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104
|
||||
// CHECK11-SAME: (i32 noundef [[DOTCAPTURE_EXPR_:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK11-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK11-NEXT: entry:
|
||||
// CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]])
|
||||
// CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
|
||||
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
|
||||
// CHECK11-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0)
|
||||
// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 0
|
||||
// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
|
||||
// CHECK11-NEXT: store i32 [[TMP3]], ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 1
|
||||
// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
|
||||
// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
// CHECK11-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP4]], i32 0)
|
||||
// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104.omp_outlined)
|
||||
// CHECK11-NEXT: ret void
|
||||
//
|
||||
@ -1648,15 +1697,22 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108
|
||||
// CHECK11-SAME: (i32 noundef [[DOTCAPTURE_EXPR_:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK11-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK11-NEXT: entry:
|
||||
// CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
|
||||
// CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
|
||||
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
|
||||
// CHECK11-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0)
|
||||
// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 0
|
||||
// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
|
||||
// CHECK11-NEXT: store i32 [[TMP3]], ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 1
|
||||
// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
|
||||
// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
// CHECK11-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP4]], i32 0)
|
||||
// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108.omp_outlined)
|
||||
// CHECK11-NEXT: ret void
|
||||
//
|
||||
@ -1672,25 +1728,33 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121
|
||||
// CHECK11-SAME: (ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK11-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK11-NEXT: entry:
|
||||
// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[B:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
|
||||
// CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
|
||||
// CHECK11-NEXT: store i32 [[B]], ptr [[B_ADDR]], align 4
|
||||
// CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
|
||||
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
|
||||
// CHECK11-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0)
|
||||
// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[B_ADDR]], align 4
|
||||
// CHECK11-NEXT: store i32 [[TMP3]], ptr [[B_CASTED]], align 4
|
||||
// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[B_CASTED]], align 4
|
||||
// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.omp_outlined, ptr [[TMP1]], i32 [[TMP4]])
|
||||
// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 0
|
||||
// CHECK11-NEXT: [[THIS:%.*]] = load ptr, ptr [[TMP2]], align 4
|
||||
// CHECK11-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 1
|
||||
// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4
|
||||
// CHECK11-NEXT: store i32 [[TMP4]], ptr [[B]], align 4
|
||||
// CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 2
|
||||
// CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4
|
||||
// CHECK11-NEXT: store i32 [[TMP6]], ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 3
|
||||
// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
|
||||
// CHECK11-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
// CHECK11-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP7]], i32 0)
|
||||
// CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[B]], align 4
|
||||
// CHECK11-NEXT: store i32 [[TMP8]], ptr [[B_CASTED]], align 4
|
||||
// CHECK11-NEXT: [[TMP9:%.*]] = load i32, ptr [[B_CASTED]], align 4
|
||||
// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.omp_outlined, ptr [[THIS]], i32 [[TMP9]])
|
||||
// CHECK11-NEXT: ret void
|
||||
//
|
||||
//
|
||||
@ -1715,16 +1779,20 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126
|
||||
// CHECK11-SAME: (ptr noundef [[THIS:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK11-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK11-NEXT: entry:
|
||||
// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
|
||||
// CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
|
||||
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
|
||||
// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 0
|
||||
// CHECK11-NEXT: [[THIS:%.*]] = load ptr, ptr [[TMP2]], align 4
|
||||
// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 1
|
||||
// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
|
||||
// CHECK11-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 1024, i32 0)
|
||||
// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126.omp_outlined, ptr [[TMP1]])
|
||||
// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126.omp_outlined, ptr [[THIS]])
|
||||
// CHECK11-NEXT: ret void
|
||||
//
|
||||
//
|
||||
@ -1744,11 +1812,16 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88
|
||||
// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK11-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK11-NEXT: entry:
|
||||
// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
|
||||
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 0
|
||||
// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
|
||||
// CHECK11-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 20, i32 0)
|
||||
// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88.omp_outlined)
|
||||
// CHECK11-NEXT: ret void
|
||||
@ -1765,29 +1838,40 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93
|
||||
// CHECK11-SAME: (i32 noundef [[A:%.*]], i32 noundef [[B:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK11-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK11-NEXT: entry:
|
||||
// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[A:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[B:%.*]] = alloca i16, align 2
|
||||
// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2
|
||||
// CHECK11-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
|
||||
// CHECK11-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
|
||||
// CHECK11-NEXT: store i32 [[B]], ptr [[B_ADDR]], align 4
|
||||
// CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
|
||||
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP1:%.*]] = load i16, ptr [[DOTCAPTURE_EXPR__ADDR]], align 2
|
||||
// CHECK11-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32
|
||||
// CHECK11-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0)
|
||||
// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[A_ADDR]], align 4
|
||||
// CHECK11-NEXT: store i32 [[TMP3]], ptr [[A_CASTED]], align 4
|
||||
// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[A_CASTED]], align 4
|
||||
// CHECK11-NEXT: [[TMP5:%.*]] = load i16, ptr [[B_ADDR]], align 2
|
||||
// CHECK11-NEXT: store i16 [[TMP5]], ptr [[B_CASTED]], align 2
|
||||
// CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[B_CASTED]], align 4
|
||||
// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93.omp_outlined, i32 [[TMP4]], i32 [[TMP6]])
|
||||
// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 0
|
||||
// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
|
||||
// CHECK11-NEXT: store i32 [[TMP3]], ptr [[A]], align 4
|
||||
// CHECK11-NEXT: [[TMP4:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 1
|
||||
// CHECK11-NEXT: [[TMP5:%.*]] = load i16, ptr [[TMP4]], align 4
|
||||
// CHECK11-NEXT: store i16 [[TMP5]], ptr [[B]], align 2
|
||||
// CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 2
|
||||
// CHECK11-NEXT: [[TMP7:%.*]] = load i16, ptr [[TMP6]], align 4
|
||||
// CHECK11-NEXT: store i16 [[TMP7]], ptr [[DOTCAPTURE_EXPR_]], align 2
|
||||
// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 3
|
||||
// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
|
||||
// CHECK11-NEXT: [[TMP8:%.*]] = load i16, ptr [[DOTCAPTURE_EXPR_]], align 2
|
||||
// CHECK11-NEXT: [[TMP9:%.*]] = sext i16 [[TMP8]] to i32
|
||||
// CHECK11-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP9]], i32 0)
|
||||
// CHECK11-NEXT: [[TMP10:%.*]] = load i32, ptr [[A]], align 4
|
||||
// CHECK11-NEXT: store i32 [[TMP10]], ptr [[A_CASTED]], align 4
|
||||
// CHECK11-NEXT: [[TMP11:%.*]] = load i32, ptr [[A_CASTED]], align 4
|
||||
// CHECK11-NEXT: [[TMP12:%.*]] = load i16, ptr [[B]], align 2
|
||||
// CHECK11-NEXT: store i16 [[TMP12]], ptr [[B_CASTED]], align 2
|
||||
// CHECK11-NEXT: [[TMP13:%.*]] = load i32, ptr [[B_CASTED]], align 4
|
||||
// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93.omp_outlined, i32 [[TMP11]], i32 [[TMP13]])
|
||||
// CHECK11-NEXT: ret void
|
||||
//
|
||||
//
|
||||
|
||||
@ -1475,18 +1475,27 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104
|
||||
// CHECK9-SAME: (i64 noundef [[DOTCAPTURE_EXPR_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_1:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK9-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK9-NEXT: entry:
|
||||
// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
|
||||
// CHECK9-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
|
||||
// CHECK9-NEXT: [[DYN_PTR2:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]])
|
||||
// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8
|
||||
// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], ptr [[DOTCAPTURE_EXPR__ADDR2]], align 8
|
||||
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
|
||||
// CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR2]], align 4
|
||||
// CHECK9-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
|
||||
// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 0
|
||||
// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 8
|
||||
// CHECK9-NEXT: store i32 [[TMP3]], ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
// CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 1
|
||||
// CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 8
|
||||
// CHECK9-NEXT: store i32 [[TMP5]], ptr [[DOTCAPTURE_EXPR_1]], align 4
|
||||
// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 2
|
||||
// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR2]], align 8
|
||||
// CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
// CHECK9-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
|
||||
// CHECK9-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP6]], i32 [[TMP7]])
|
||||
// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104.omp_outlined)
|
||||
// CHECK9-NEXT: ret void
|
||||
//
|
||||
@ -1502,15 +1511,22 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108
|
||||
// CHECK9-SAME: (i64 noundef [[DOTCAPTURE_EXPR_:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK9-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK9-NEXT: entry:
|
||||
// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
|
||||
// CHECK9-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
|
||||
// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8
|
||||
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
|
||||
// CHECK9-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 0, i32 [[TMP1]])
|
||||
// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 0
|
||||
// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 8
|
||||
// CHECK9-NEXT: store i32 [[TMP3]], ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 1
|
||||
// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
|
||||
// CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
// CHECK9-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 0, i32 [[TMP4]])
|
||||
// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108.omp_outlined)
|
||||
// CHECK9-NEXT: ret void
|
||||
//
|
||||
@ -1526,25 +1542,33 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121
|
||||
// CHECK9-SAME: (ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK9-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK9-NEXT: entry:
|
||||
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[B:%.*]] = alloca i32, align 4
|
||||
// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
|
||||
// CHECK9-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
|
||||
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
|
||||
// CHECK9-NEXT: store i64 [[B]], ptr [[B_ADDR]], align 8
|
||||
// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8
|
||||
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
|
||||
// CHECK9-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 0, i32 [[TMP2]])
|
||||
// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[B_ADDR]], align 4
|
||||
// CHECK9-NEXT: store i32 [[TMP3]], ptr [[B_CASTED]], align 4
|
||||
// CHECK9-NEXT: [[TMP4:%.*]] = load i64, ptr [[B_CASTED]], align 8
|
||||
// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.omp_outlined, ptr [[TMP1]], i64 [[TMP4]])
|
||||
// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 0
|
||||
// CHECK9-NEXT: [[THIS:%.*]] = load ptr, ptr [[TMP2]], align 8
|
||||
// CHECK9-NEXT: [[TMP3:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 1
|
||||
// CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 8
|
||||
// CHECK9-NEXT: store i32 [[TMP4]], ptr [[B]], align 4
|
||||
// CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 2
|
||||
// CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 8
|
||||
// CHECK9-NEXT: store i32 [[TMP6]], ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 3
|
||||
// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
|
||||
// CHECK9-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
// CHECK9-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 0, i32 [[TMP7]])
|
||||
// CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[B]], align 4
|
||||
// CHECK9-NEXT: store i32 [[TMP8]], ptr [[B_CASTED]], align 4
|
||||
// CHECK9-NEXT: [[TMP9:%.*]] = load i64, ptr [[B_CASTED]], align 8
|
||||
// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.omp_outlined, ptr [[THIS]], i64 [[TMP9]])
|
||||
// CHECK9-NEXT: ret void
|
||||
//
|
||||
//
|
||||
@ -1569,16 +1593,20 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126
|
||||
// CHECK9-SAME: (ptr noundef [[THIS:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK9-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK9-NEXT: entry:
|
||||
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
|
||||
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
|
||||
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
|
||||
// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 0
|
||||
// CHECK9-NEXT: [[THIS:%.*]] = load ptr, ptr [[TMP2]], align 8
|
||||
// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 1
|
||||
// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
|
||||
// CHECK9-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 0, i32 1024)
|
||||
// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126.omp_outlined, ptr [[TMP1]])
|
||||
// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126.omp_outlined, ptr [[THIS]])
|
||||
// CHECK9-NEXT: ret void
|
||||
//
|
||||
//
|
||||
@ -1598,11 +1626,16 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88
|
||||
// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK9-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK9-NEXT: entry:
|
||||
// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
|
||||
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 0
|
||||
// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
|
||||
// CHECK9-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 0, i32 20)
|
||||
// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88.omp_outlined)
|
||||
// CHECK9-NEXT: ret void
|
||||
@ -1619,29 +1652,40 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93
|
||||
// CHECK9-SAME: (i64 noundef [[A:%.*]], i64 noundef [[B:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK9-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK9-NEXT: entry:
|
||||
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[A:%.*]] = alloca i32, align 4
|
||||
// CHECK9-NEXT: [[B:%.*]] = alloca i16, align 2
|
||||
// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2
|
||||
// CHECK9-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
|
||||
// CHECK9-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8
|
||||
// CHECK9-NEXT: store i64 [[B]], ptr [[B_ADDR]], align 8
|
||||
// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8
|
||||
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP1:%.*]] = load i16, ptr [[DOTCAPTURE_EXPR__ADDR]], align 2
|
||||
// CHECK9-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32
|
||||
// CHECK9-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 1024)
|
||||
// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[A_ADDR]], align 4
|
||||
// CHECK9-NEXT: store i32 [[TMP3]], ptr [[A_CASTED]], align 4
|
||||
// CHECK9-NEXT: [[TMP4:%.*]] = load i64, ptr [[A_CASTED]], align 8
|
||||
// CHECK9-NEXT: [[TMP5:%.*]] = load i16, ptr [[B_ADDR]], align 2
|
||||
// CHECK9-NEXT: store i16 [[TMP5]], ptr [[B_CASTED]], align 2
|
||||
// CHECK9-NEXT: [[TMP6:%.*]] = load i64, ptr [[B_CASTED]], align 8
|
||||
// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93.omp_outlined, i64 [[TMP4]], i64 [[TMP6]])
|
||||
// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 0
|
||||
// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 8
|
||||
// CHECK9-NEXT: store i32 [[TMP3]], ptr [[A]], align 4
|
||||
// CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 1
|
||||
// CHECK9-NEXT: [[TMP5:%.*]] = load i16, ptr [[TMP4]], align 8
|
||||
// CHECK9-NEXT: store i16 [[TMP5]], ptr [[B]], align 2
|
||||
// CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 2
|
||||
// CHECK9-NEXT: [[TMP7:%.*]] = load i16, ptr [[TMP6]], align 8
|
||||
// CHECK9-NEXT: store i16 [[TMP7]], ptr [[DOTCAPTURE_EXPR_]], align 2
|
||||
// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 3
|
||||
// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
|
||||
// CHECK9-NEXT: [[TMP8:%.*]] = load i16, ptr [[DOTCAPTURE_EXPR_]], align 2
|
||||
// CHECK9-NEXT: [[TMP9:%.*]] = sext i16 [[TMP8]] to i32
|
||||
// CHECK9-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP9]], i32 1024)
|
||||
// CHECK9-NEXT: [[TMP10:%.*]] = load i32, ptr [[A]], align 4
|
||||
// CHECK9-NEXT: store i32 [[TMP10]], ptr [[A_CASTED]], align 4
|
||||
// CHECK9-NEXT: [[TMP11:%.*]] = load i64, ptr [[A_CASTED]], align 8
|
||||
// CHECK9-NEXT: [[TMP12:%.*]] = load i16, ptr [[B]], align 2
|
||||
// CHECK9-NEXT: store i16 [[TMP12]], ptr [[B_CASTED]], align 2
|
||||
// CHECK9-NEXT: [[TMP13:%.*]] = load i64, ptr [[B_CASTED]], align 8
|
||||
// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93.omp_outlined, i64 [[TMP11]], i64 [[TMP13]])
|
||||
// CHECK9-NEXT: ret void
|
||||
//
|
||||
//
|
||||
@ -1665,18 +1709,27 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104
|
||||
// CHECK11-SAME: (i32 noundef [[DOTCAPTURE_EXPR_:%.*]], i32 noundef [[DOTCAPTURE_EXPR_1:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK11-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK11-NEXT: entry:
|
||||
// CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[DYN_PTR2:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]])
|
||||
// CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
|
||||
// CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], ptr [[DOTCAPTURE_EXPR__ADDR2]], align 4
|
||||
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR2]], align 4
|
||||
// CHECK11-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
|
||||
// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 0
|
||||
// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
|
||||
// CHECK11-NEXT: store i32 [[TMP3]], ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
// CHECK11-NEXT: [[TMP4:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 1
|
||||
// CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
|
||||
// CHECK11-NEXT: store i32 [[TMP5]], ptr [[DOTCAPTURE_EXPR_1]], align 4
|
||||
// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 2
|
||||
// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR2]], align 4
|
||||
// CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
// CHECK11-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
|
||||
// CHECK11-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP6]], i32 [[TMP7]])
|
||||
// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104.omp_outlined)
|
||||
// CHECK11-NEXT: ret void
|
||||
//
|
||||
@ -1692,15 +1745,22 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108
|
||||
// CHECK11-SAME: (i32 noundef [[DOTCAPTURE_EXPR_:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK11-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK11-NEXT: entry:
|
||||
// CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
|
||||
// CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
|
||||
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
|
||||
// CHECK11-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 0, i32 [[TMP1]])
|
||||
// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 0
|
||||
// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
|
||||
// CHECK11-NEXT: store i32 [[TMP3]], ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 1
|
||||
// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
|
||||
// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
// CHECK11-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 0, i32 [[TMP4]])
|
||||
// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108.omp_outlined)
|
||||
// CHECK11-NEXT: ret void
|
||||
//
|
||||
@ -1716,25 +1776,33 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121
|
||||
// CHECK11-SAME: (ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK11-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK11-NEXT: entry:
|
||||
// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[B:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
|
||||
// CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
|
||||
// CHECK11-NEXT: store i32 [[B]], ptr [[B_ADDR]], align 4
|
||||
// CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
|
||||
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
|
||||
// CHECK11-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 0, i32 [[TMP2]])
|
||||
// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[B_ADDR]], align 4
|
||||
// CHECK11-NEXT: store i32 [[TMP3]], ptr [[B_CASTED]], align 4
|
||||
// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[B_CASTED]], align 4
|
||||
// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.omp_outlined, ptr [[TMP1]], i32 [[TMP4]])
|
||||
// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 0
|
||||
// CHECK11-NEXT: [[THIS:%.*]] = load ptr, ptr [[TMP2]], align 4
|
||||
// CHECK11-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 1
|
||||
// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4
|
||||
// CHECK11-NEXT: store i32 [[TMP4]], ptr [[B]], align 4
|
||||
// CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 2
|
||||
// CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4
|
||||
// CHECK11-NEXT: store i32 [[TMP6]], ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 3
|
||||
// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
|
||||
// CHECK11-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
// CHECK11-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 0, i32 [[TMP7]])
|
||||
// CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[B]], align 4
|
||||
// CHECK11-NEXT: store i32 [[TMP8]], ptr [[B_CASTED]], align 4
|
||||
// CHECK11-NEXT: [[TMP9:%.*]] = load i32, ptr [[B_CASTED]], align 4
|
||||
// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.omp_outlined, ptr [[THIS]], i32 [[TMP9]])
|
||||
// CHECK11-NEXT: ret void
|
||||
//
|
||||
//
|
||||
@ -1759,16 +1827,20 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126
|
||||
// CHECK11-SAME: (ptr noundef [[THIS:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK11-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK11-NEXT: entry:
|
||||
// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
|
||||
// CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
|
||||
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
|
||||
// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 0
|
||||
// CHECK11-NEXT: [[THIS:%.*]] = load ptr, ptr [[TMP2]], align 4
|
||||
// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 1
|
||||
// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
|
||||
// CHECK11-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 0, i32 1024)
|
||||
// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126.omp_outlined, ptr [[TMP1]])
|
||||
// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126.omp_outlined, ptr [[THIS]])
|
||||
// CHECK11-NEXT: ret void
|
||||
//
|
||||
//
|
||||
@ -1788,11 +1860,16 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88
|
||||
// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK11-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK11-NEXT: entry:
|
||||
// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
|
||||
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 0
|
||||
// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
|
||||
// CHECK11-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 0, i32 20)
|
||||
// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88.omp_outlined)
|
||||
// CHECK11-NEXT: ret void
|
||||
@ -1809,29 +1886,40 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93
|
||||
// CHECK11-SAME: (i32 noundef [[A:%.*]], i32 noundef [[B:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK11-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK11-NEXT: entry:
|
||||
// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[A:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[B:%.*]] = alloca i16, align 2
|
||||
// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2
|
||||
// CHECK11-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
|
||||
// CHECK11-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
|
||||
// CHECK11-NEXT: store i32 [[B]], ptr [[B_ADDR]], align 4
|
||||
// CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
|
||||
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP1:%.*]] = load i16, ptr [[DOTCAPTURE_EXPR__ADDR]], align 2
|
||||
// CHECK11-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32
|
||||
// CHECK11-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 1024)
|
||||
// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[A_ADDR]], align 4
|
||||
// CHECK11-NEXT: store i32 [[TMP3]], ptr [[A_CASTED]], align 4
|
||||
// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[A_CASTED]], align 4
|
||||
// CHECK11-NEXT: [[TMP5:%.*]] = load i16, ptr [[B_ADDR]], align 2
|
||||
// CHECK11-NEXT: store i16 [[TMP5]], ptr [[B_CASTED]], align 2
|
||||
// CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[B_CASTED]], align 4
|
||||
// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93.omp_outlined, i32 [[TMP4]], i32 [[TMP6]])
|
||||
// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 0
|
||||
// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
|
||||
// CHECK11-NEXT: store i32 [[TMP3]], ptr [[A]], align 4
|
||||
// CHECK11-NEXT: [[TMP4:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 1
|
||||
// CHECK11-NEXT: [[TMP5:%.*]] = load i16, ptr [[TMP4]], align 4
|
||||
// CHECK11-NEXT: store i16 [[TMP5]], ptr [[B]], align 2
|
||||
// CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 2
|
||||
// CHECK11-NEXT: [[TMP7:%.*]] = load i16, ptr [[TMP6]], align 4
|
||||
// CHECK11-NEXT: store i16 [[TMP7]], ptr [[DOTCAPTURE_EXPR_]], align 2
|
||||
// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 3
|
||||
// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
|
||||
// CHECK11-NEXT: [[TMP8:%.*]] = load i16, ptr [[DOTCAPTURE_EXPR_]], align 2
|
||||
// CHECK11-NEXT: [[TMP9:%.*]] = sext i16 [[TMP8]] to i32
|
||||
// CHECK11-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP9]], i32 1024)
|
||||
// CHECK11-NEXT: [[TMP10:%.*]] = load i32, ptr [[A]], align 4
|
||||
// CHECK11-NEXT: store i32 [[TMP10]], ptr [[A_CASTED]], align 4
|
||||
// CHECK11-NEXT: [[TMP11:%.*]] = load i32, ptr [[A_CASTED]], align 4
|
||||
// CHECK11-NEXT: [[TMP12:%.*]] = load i16, ptr [[B]], align 2
|
||||
// CHECK11-NEXT: store i16 [[TMP12]], ptr [[B_CASTED]], align 2
|
||||
// CHECK11-NEXT: [[TMP13:%.*]] = load i32, ptr [[B_CASTED]], align 4
|
||||
// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93.omp_outlined, i32 [[TMP11]], i32 [[TMP13]])
|
||||
// CHECK11-NEXT: ret void
|
||||
//
|
||||
//
|
||||
|
||||
@ -2531,13 +2531,20 @@ void foo() {
|
||||
//
|
||||
//
|
||||
// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l216
|
||||
// CHECK25-SAME: (i64 noundef [[ARGC:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK25-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK25-NEXT: entry:
|
||||
// CHECK25-NEXT: [[ARGC_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK25-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK25-NEXT: store i64 [[ARGC]], ptr [[ARGC_ADDR]], align 8
|
||||
// CHECK25-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK25-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1:[0-9]+]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l216.omp_outlined, ptr [[ARGC_ADDR]])
|
||||
// CHECK25-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK25-NEXT: [[ARGC:%.*]] = alloca i32, align 4
|
||||
// CHECK25-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
|
||||
// CHECK25-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK25-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK25-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
|
||||
// CHECK25-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 8
|
||||
// CHECK25-NEXT: store i32 [[TMP2]], ptr [[ARGC]], align 4
|
||||
// CHECK25-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
|
||||
// CHECK25-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK25-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
|
||||
// CHECK25-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1:[0-9]+]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l216.omp_outlined, ptr [[ARGC]])
|
||||
// CHECK25-NEXT: ret void
|
||||
//
|
||||
//
|
||||
@ -2556,13 +2563,17 @@ void foo() {
|
||||
//
|
||||
//
|
||||
// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIPPcEiT__l209
|
||||
// CHECK25-SAME: (ptr noundef [[ARGC:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK25-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK25-NEXT: entry:
|
||||
// CHECK25-NEXT: [[ARGC_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK25-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK25-NEXT: store ptr [[ARGC]], ptr [[ARGC_ADDR]], align 8
|
||||
// CHECK25-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK25-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIPPcEiT__l209.omp_outlined, ptr [[ARGC_ADDR]])
|
||||
// CHECK25-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK25-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
|
||||
// CHECK25-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK25-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK25-NEXT: [[ARGC:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
|
||||
// CHECK25-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
|
||||
// CHECK25-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK25-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
|
||||
// CHECK25-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIPPcEiT__l209.omp_outlined, ptr [[ARGC]])
|
||||
// CHECK25-NEXT: ret void
|
||||
//
|
||||
//
|
||||
@ -2581,13 +2592,20 @@ void foo() {
|
||||
//
|
||||
//
|
||||
// CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l216
|
||||
// CHECK27-SAME: (i32 noundef [[ARGC:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK27-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK27-NEXT: entry:
|
||||
// CHECK27-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK27-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK27-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4
|
||||
// CHECK27-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK27-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1:[0-9]+]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l216.omp_outlined, ptr [[ARGC_ADDR]])
|
||||
// CHECK27-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK27-NEXT: [[ARGC:%.*]] = alloca i32, align 4
|
||||
// CHECK27-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 4
|
||||
// CHECK27-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK27-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK27-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
|
||||
// CHECK27-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
|
||||
// CHECK27-NEXT: store i32 [[TMP2]], ptr [[ARGC]], align 4
|
||||
// CHECK27-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
|
||||
// CHECK27-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK27-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
|
||||
// CHECK27-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1:[0-9]+]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l216.omp_outlined, ptr [[ARGC]])
|
||||
// CHECK27-NEXT: ret void
|
||||
//
|
||||
//
|
||||
@ -2606,13 +2624,17 @@ void foo() {
|
||||
//
|
||||
//
|
||||
// CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIPPcEiT__l209
|
||||
// CHECK27-SAME: (ptr noundef [[ARGC:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK27-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK27-NEXT: entry:
|
||||
// CHECK27-NEXT: [[ARGC_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK27-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK27-NEXT: store ptr [[ARGC]], ptr [[ARGC_ADDR]], align 4
|
||||
// CHECK27-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK27-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIPPcEiT__l209.omp_outlined, ptr [[ARGC_ADDR]])
|
||||
// CHECK27-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK27-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 4
|
||||
// CHECK27-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK27-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK27-NEXT: [[ARGC:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
|
||||
// CHECK27-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
|
||||
// CHECK27-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK27-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
|
||||
// CHECK27-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIPPcEiT__l209.omp_outlined, ptr [[ARGC]])
|
||||
// CHECK27-NEXT: ret void
|
||||
//
|
||||
//
|
||||
@ -2631,21 +2653,32 @@ void foo() {
|
||||
//
|
||||
//
|
||||
// CHECK33-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l265
|
||||
// CHECK33-SAME: (i64 noundef [[A:%.*]], i64 noundef [[B:%.*]], i64 noundef [[ARGC:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK33-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK33-NEXT: entry:
|
||||
// CHECK33-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK33-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK33-NEXT: [[ARGC_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK33-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK33-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK33-NEXT: [[A:%.*]] = alloca i32, align 4
|
||||
// CHECK33-NEXT: [[B:%.*]] = alloca i32, align 4
|
||||
// CHECK33-NEXT: [[ARGC:%.*]] = alloca i32, align 4
|
||||
// CHECK33-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
|
||||
// CHECK33-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]])
|
||||
// CHECK33-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8
|
||||
// CHECK33-NEXT: store i64 [[B]], ptr [[B_ADDR]], align 8
|
||||
// CHECK33-NEXT: store i64 [[ARGC]], ptr [[ARGC_ADDR]], align 8
|
||||
// CHECK33-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK33-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
|
||||
// CHECK33-NEXT: [[TMP2:%.*]] = load i32, ptr [[B_ADDR]], align 4
|
||||
// CHECK33-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
|
||||
// CHECK33-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l265.omp_outlined, ptr [[ARGC_ADDR]])
|
||||
// CHECK33-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK33-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK33-NEXT: [[TMP2:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 0
|
||||
// CHECK33-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 8
|
||||
// CHECK33-NEXT: store i32 [[TMP3]], ptr [[A]], align 4
|
||||
// CHECK33-NEXT: [[TMP4:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 1
|
||||
// CHECK33-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 8
|
||||
// CHECK33-NEXT: store i32 [[TMP5]], ptr [[B]], align 4
|
||||
// CHECK33-NEXT: [[TMP6:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 2
|
||||
// CHECK33-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 8
|
||||
// CHECK33-NEXT: store i32 [[TMP7]], ptr [[ARGC]], align 4
|
||||
// CHECK33-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 3
|
||||
// CHECK33-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK33-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
|
||||
// CHECK33-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 4
|
||||
// CHECK33-NEXT: [[TMP9:%.*]] = load i32, ptr [[B]], align 4
|
||||
// CHECK33-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP8]], i32 [[TMP9]])
|
||||
// CHECK33-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l265.omp_outlined, ptr [[ARGC]])
|
||||
// CHECK33-NEXT: ret void
|
||||
//
|
||||
//
|
||||
@ -2664,21 +2697,29 @@ void foo() {
|
||||
//
|
||||
//
|
||||
// CHECK33-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIPPcEiT__l254
|
||||
// CHECK33-SAME: (i64 noundef [[A:%.*]], i64 noundef [[B:%.*]], ptr noundef [[ARGC:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK33-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK33-NEXT: entry:
|
||||
// CHECK33-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK33-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK33-NEXT: [[ARGC_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK33-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK33-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK33-NEXT: [[A:%.*]] = alloca i32, align 4
|
||||
// CHECK33-NEXT: [[B:%.*]] = alloca i32, align 4
|
||||
// CHECK33-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
|
||||
// CHECK33-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
|
||||
// CHECK33-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8
|
||||
// CHECK33-NEXT: store i64 [[B]], ptr [[B_ADDR]], align 8
|
||||
// CHECK33-NEXT: store ptr [[ARGC]], ptr [[ARGC_ADDR]], align 8
|
||||
// CHECK33-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK33-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
|
||||
// CHECK33-NEXT: [[TMP2:%.*]] = load i32, ptr [[B_ADDR]], align 4
|
||||
// CHECK33-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
|
||||
// CHECK33-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIPPcEiT__l254.omp_outlined, ptr [[ARGC_ADDR]])
|
||||
// CHECK33-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK33-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
|
||||
// CHECK33-NEXT: [[TMP2:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 0
|
||||
// CHECK33-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 8
|
||||
// CHECK33-NEXT: store i32 [[TMP3]], ptr [[A]], align 4
|
||||
// CHECK33-NEXT: [[TMP4:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 1
|
||||
// CHECK33-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 8
|
||||
// CHECK33-NEXT: store i32 [[TMP5]], ptr [[B]], align 4
|
||||
// CHECK33-NEXT: [[ARGC:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 2
|
||||
// CHECK33-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 3
|
||||
// CHECK33-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK33-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
|
||||
// CHECK33-NEXT: [[TMP6:%.*]] = load i32, ptr [[A]], align 4
|
||||
// CHECK33-NEXT: [[TMP7:%.*]] = load i32, ptr [[B]], align 4
|
||||
// CHECK33-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP6]], i32 [[TMP7]])
|
||||
// CHECK33-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIPPcEiT__l254.omp_outlined, ptr [[ARGC]])
|
||||
// CHECK33-NEXT: ret void
|
||||
//
|
||||
//
|
||||
@ -2697,21 +2738,32 @@ void foo() {
|
||||
//
|
||||
//
|
||||
// CHECK35-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l265
|
||||
// CHECK35-SAME: (i32 noundef [[A:%.*]], i32 noundef [[B:%.*]], i32 noundef [[ARGC:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK35-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK35-NEXT: entry:
|
||||
// CHECK35-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK35-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK35-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK35-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK35-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK35-NEXT: [[A:%.*]] = alloca i32, align 4
|
||||
// CHECK35-NEXT: [[B:%.*]] = alloca i32, align 4
|
||||
// CHECK35-NEXT: [[ARGC:%.*]] = alloca i32, align 4
|
||||
// CHECK35-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 4
|
||||
// CHECK35-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]])
|
||||
// CHECK35-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
|
||||
// CHECK35-NEXT: store i32 [[B]], ptr [[B_ADDR]], align 4
|
||||
// CHECK35-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4
|
||||
// CHECK35-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK35-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
|
||||
// CHECK35-NEXT: [[TMP2:%.*]] = load i32, ptr [[B_ADDR]], align 4
|
||||
// CHECK35-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
|
||||
// CHECK35-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l265.omp_outlined, ptr [[ARGC_ADDR]])
|
||||
// CHECK35-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK35-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK35-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 0
|
||||
// CHECK35-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
|
||||
// CHECK35-NEXT: store i32 [[TMP3]], ptr [[A]], align 4
|
||||
// CHECK35-NEXT: [[TMP4:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 1
|
||||
// CHECK35-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
|
||||
// CHECK35-NEXT: store i32 [[TMP5]], ptr [[B]], align 4
|
||||
// CHECK35-NEXT: [[TMP6:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 2
|
||||
// CHECK35-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4
|
||||
// CHECK35-NEXT: store i32 [[TMP7]], ptr [[ARGC]], align 4
|
||||
// CHECK35-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 3
|
||||
// CHECK35-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK35-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
|
||||
// CHECK35-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 4
|
||||
// CHECK35-NEXT: [[TMP9:%.*]] = load i32, ptr [[B]], align 4
|
||||
// CHECK35-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP8]], i32 [[TMP9]])
|
||||
// CHECK35-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l265.omp_outlined, ptr [[ARGC]])
|
||||
// CHECK35-NEXT: ret void
|
||||
//
|
||||
//
|
||||
@ -2730,21 +2782,29 @@ void foo() {
|
||||
//
|
||||
//
|
||||
// CHECK35-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIPPcEiT__l254
|
||||
// CHECK35-SAME: (i32 noundef [[A:%.*]], i32 noundef [[B:%.*]], ptr noundef [[ARGC:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK35-SAME: (ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK35-NEXT: entry:
|
||||
// CHECK35-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK35-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK35-NEXT: [[ARGC_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK35-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK35-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK35-NEXT: [[A:%.*]] = alloca i32, align 4
|
||||
// CHECK35-NEXT: [[B:%.*]] = alloca i32, align 4
|
||||
// CHECK35-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 4
|
||||
// CHECK35-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
|
||||
// CHECK35-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
|
||||
// CHECK35-NEXT: store i32 [[B]], ptr [[B_ADDR]], align 4
|
||||
// CHECK35-NEXT: store ptr [[ARGC]], ptr [[ARGC_ADDR]], align 4
|
||||
// CHECK35-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK35-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
|
||||
// CHECK35-NEXT: [[TMP2:%.*]] = load i32, ptr [[B_ADDR]], align 4
|
||||
// CHECK35-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
|
||||
// CHECK35-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIPPcEiT__l254.omp_outlined, ptr [[ARGC_ADDR]])
|
||||
// CHECK35-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK35-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
|
||||
// CHECK35-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 0
|
||||
// CHECK35-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
|
||||
// CHECK35-NEXT: store i32 [[TMP3]], ptr [[A]], align 4
|
||||
// CHECK35-NEXT: [[TMP4:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 1
|
||||
// CHECK35-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
|
||||
// CHECK35-NEXT: store i32 [[TMP5]], ptr [[B]], align 4
|
||||
// CHECK35-NEXT: [[ARGC:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 2
|
||||
// CHECK35-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 3
|
||||
// CHECK35-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK35-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
|
||||
// CHECK35-NEXT: [[TMP6:%.*]] = load i32, ptr [[A]], align 4
|
||||
// CHECK35-NEXT: [[TMP7:%.*]] = load i32, ptr [[B]], align 4
|
||||
// CHECK35-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP6]], i32 [[TMP7]])
|
||||
// CHECK35-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIPPcEiT__l254.omp_outlined, ptr [[ARGC]])
|
||||
// CHECK35-NEXT: ret void
|
||||
//
|
||||
//
|
||||
|
||||
@ -1,8 +1,5 @@
|
||||
# Try to detect in the system several dependencies required by the different
|
||||
# components of libomptarget. These are the dependencies we have:
|
||||
#
|
||||
# libffi : required to launch target kernels given function and argument
|
||||
# pointers.
|
||||
|
||||
include (FindPackageHandleStandardArgs)
|
||||
|
||||
@ -20,12 +17,6 @@ list(APPEND LIBOMPTARGET_LLVM_INCLUDE_DIRS
|
||||
message(STATUS
|
||||
"Using LLVM include directories: ${LIBOMPTARGET_LLVM_INCLUDE_DIRS}")
|
||||
|
||||
################################################################################
|
||||
# Looking for libffi...
|
||||
################################################################################
|
||||
find_package(FFI QUIET)
|
||||
set(LIBOMPTARGET_DEP_LIBFFI_FOUND ${FFI_FOUND})
|
||||
|
||||
################################################################################
|
||||
# Looking for offload-arch...
|
||||
################################################################################
|
||||
|
||||
@ -8,30 +8,9 @@ add_target_library(omptarget.rtl.host ${machine})
|
||||
|
||||
target_sources(omptarget.rtl.host PRIVATE src/rtl.cpp)
|
||||
|
||||
if(LIBOMPTARGET_DEP_LIBFFI_FOUND)
|
||||
message(STATUS "Building ${machine} plugin linked with libffi")
|
||||
if(FFI_STATIC_LIBRARIES)
|
||||
target_link_libraries(omptarget.rtl.host PRIVATE FFI::ffi_static)
|
||||
else()
|
||||
target_link_libraries(omptarget.rtl.host PRIVATE FFI::ffi)
|
||||
endif()
|
||||
else()
|
||||
message(STATUS "Building ${machine} plugin for dlopened libffi")
|
||||
target_sources(omptarget.rtl.host PRIVATE dynamic_ffi/ffi.cpp)
|
||||
target_include_directories(omptarget.rtl.host PRIVATE dynamic_ffi)
|
||||
endif()
|
||||
|
||||
target_include_directories(omptarget.rtl.host PRIVATE
|
||||
${LIBOMPTARGET_INCLUDE_DIR})
|
||||
|
||||
if(LIBOMPTARGET_DEP_LIBFFI_FOUND)
|
||||
list(APPEND LIBOMPTARGET_TESTED_PLUGINS omptarget.rtl.host)
|
||||
set(LIBOMPTARGET_TESTED_PLUGINS
|
||||
"${LIBOMPTARGET_TESTED_PLUGINS}" PARENT_SCOPE)
|
||||
else()
|
||||
message(STATUS "Not generating ${machine} tests. LibFFI not found.")
|
||||
endif()
|
||||
|
||||
# Define the target specific triples and ELF machine values.
|
||||
if(CMAKE_SYSTEM_PROCESSOR MATCHES "ppc64le$")
|
||||
list(APPEND LIBOMPTARGET_SYSTEM_TARGETS
|
||||
|
||||
@ -1,81 +0,0 @@
|
||||
//===--- generic-elf-64bit/dynamic_ffi/ffi.cpp -------------------- C++ -*-===//
|
||||
//
|
||||
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
|
||||
// See https://llvm.org/LICENSE.txt for license information.
|
||||
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
//
|
||||
// Implement subset of the FFI api by calling into the FFI library via dlopen
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
#include "llvm/Support/DynamicLibrary.h"
|
||||
|
||||
#include "Shared/Debug.h"
|
||||
#include <memory>
|
||||
|
||||
#include "DLWrap.h"
|
||||
#include "ffi.h"
|
||||
|
||||
using namespace llvm::offload::debug;
|
||||
|
||||
DLWRAP_INITIALIZE()
|
||||
|
||||
DLWRAP(ffi_call, 4);
|
||||
DLWRAP(ffi_prep_cif, 5);
|
||||
|
||||
DLWRAP_FINALIZE()
|
||||
|
||||
ffi_type ffi_type_void;
|
||||
ffi_type ffi_type_pointer;
|
||||
|
||||
// Name of the FFI shared library.
|
||||
constexpr const char *FFI_PATH = "libffi.so";
|
||||
|
||||
#define DYNAMIC_FFI_SUCCESS 0
|
||||
#define DYNAMIC_FFI_FAIL 1
|
||||
|
||||
// Initializes the dynamic FFI wrapper.
|
||||
uint32_t ffi_init() {
|
||||
std::string ErrMsg;
|
||||
auto DynlibHandle = std::make_unique<llvm::sys::DynamicLibrary>(
|
||||
llvm::sys::DynamicLibrary::getPermanentLibrary(FFI_PATH, &ErrMsg));
|
||||
|
||||
if (!DynlibHandle->isValid()) {
|
||||
ODBG(OLDT_Init) << "Unable to load library '" << FFI_PATH << "': " << ErrMsg
|
||||
<< "!";
|
||||
return DYNAMIC_FFI_FAIL;
|
||||
}
|
||||
|
||||
for (size_t I = 0; I < dlwrap::size(); I++) {
|
||||
const char *Sym = dlwrap::symbol(I);
|
||||
|
||||
void *P = DynlibHandle->getAddressOfSymbol(Sym);
|
||||
if (P == nullptr) {
|
||||
ODBG(OLDT_Init) << "Unable to find '" << Sym << "' in '" << FFI_PATH
|
||||
<< "'!";
|
||||
return DYNAMIC_FFI_FAIL;
|
||||
}
|
||||
ODBG(OLDT_Init) << "Implementing " << Sym << " with dlsym(" << Sym
|
||||
<< ") -> " << P;
|
||||
|
||||
*dlwrap::pointer(I) = P;
|
||||
}
|
||||
|
||||
#define DYNAMIC_INIT(SYMBOL) \
|
||||
{ \
|
||||
void *SymbolPtr = DynlibHandle->getAddressOfSymbol(#SYMBOL); \
|
||||
if (!SymbolPtr) { \
|
||||
ODBG(OLDT_Init) << "Unable to find '" << #SYMBOL << "' in '" << FFI_PATH \
|
||||
<< "'!"; \
|
||||
return DYNAMIC_FFI_FAIL; \
|
||||
} \
|
||||
SYMBOL = *reinterpret_cast<decltype(SYMBOL) *>(SymbolPtr); \
|
||||
}
|
||||
DYNAMIC_INIT(ffi_type_void);
|
||||
DYNAMIC_INIT(ffi_type_pointer);
|
||||
#undef DYNAMIC_INIT
|
||||
|
||||
return DYNAMIC_FFI_SUCCESS;
|
||||
}
|
||||
@ -1,89 +0,0 @@
|
||||
//===--- generic-elf-64bit/dynamic_ffi/ffi.cpp -------------------- C++ -*-===//
|
||||
//
|
||||
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
|
||||
// See https://llvm.org/LICENSE.txt for license information.
|
||||
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
//
|
||||
// Provides a mirror to the parts of the FFI interface that the plugins require.
|
||||
//
|
||||
// libffi
|
||||
// - Copyright (c) 2011, 2014, 2019, 2021, 2022 Anthony Green
|
||||
// - Copyright (c) 1996-2003, 2007, 2008 Red Hat, Inc.
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
#ifndef DYNAMIC_FFI_FFI_H
|
||||
#define DYNAMIC_FFI_FFI_H
|
||||
|
||||
#include <stddef.h>
|
||||
#include <stdint.h>
|
||||
|
||||
#define USES_DYNAMIC_FFI
|
||||
|
||||
uint32_t ffi_init();
|
||||
|
||||
typedef struct _ffi_type {
|
||||
size_t size;
|
||||
unsigned short alignment;
|
||||
unsigned short type;
|
||||
struct _ffi_type **elements;
|
||||
} ffi_type;
|
||||
|
||||
typedef enum {
|
||||
FFI_OK = 0,
|
||||
FFI_BAD_TYPEDEF,
|
||||
FFI_BAD_ABI,
|
||||
FFI_BAD_ARGTYPE
|
||||
} ffi_status;
|
||||
|
||||
// These are target dependent so we set them manually for each ABI by
|
||||
// referencing the FFI source.
|
||||
typedef enum ffi_abi {
|
||||
#if (defined(_M_X64) || defined(__x86_64__))
|
||||
FFI_DEFAULT_ABI = 2, // FFI_UNIX64.
|
||||
#elif defined(__aarch64__) || defined(__arm64__) || defined(_M_ARM64) || \
|
||||
defined(__riscv) || defined(__loongarch__)
|
||||
FFI_DEFAULT_ABI = 1, // FFI_SYSV.
|
||||
#elif defined(__powerpc64__)
|
||||
FFI_DEFAULT_ABI = 8, // FFI_LINUX.
|
||||
#elif defined(__s390x__)
|
||||
FFI_DEFAULT_ABI = 1, // FFI_SYSV.
|
||||
#else
|
||||
#error "Unknown ABI"
|
||||
#endif
|
||||
} ffi_abi;
|
||||
|
||||
typedef struct {
|
||||
ffi_abi abi;
|
||||
unsigned nargs;
|
||||
ffi_type **arg_types;
|
||||
ffi_type *rtype;
|
||||
unsigned bytes;
|
||||
unsigned flags;
|
||||
long long extra_fields; // Longest extra field defined in the FFI sources
|
||||
} ffi_cif;
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define FFI_EXTERN extern
|
||||
#define FFI_API
|
||||
|
||||
FFI_EXTERN ffi_type ffi_type_void;
|
||||
FFI_EXTERN ffi_type ffi_type_pointer;
|
||||
|
||||
FFI_API
|
||||
void ffi_call(ffi_cif *cif, void (*fn)(void), void *rvalue, void **avalue);
|
||||
|
||||
FFI_API
|
||||
ffi_status ffi_prep_cif(ffi_cif *cif, ffi_abi abi, unsigned int nargs,
|
||||
ffi_type *rtype, ffi_type **atypes);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // DYNAMIC_FFI_FFI_H
|
||||
@ -12,7 +12,6 @@
|
||||
|
||||
#include <cassert>
|
||||
#include <cstddef>
|
||||
#include <ffi.h>
|
||||
#include <string>
|
||||
#include <unordered_map>
|
||||
|
||||
@ -65,8 +64,7 @@ using namespace error;
|
||||
/// Class implementing kernel functionalities for GenELF64.
|
||||
struct GenELF64KernelTy : public GenericKernelTy {
|
||||
/// Construct the kernel with a name and an execution mode.
|
||||
GenELF64KernelTy(const char *Name, bool SupportsFFI)
|
||||
: GenericKernelTy(Name), Func(nullptr), SupportsFFI(SupportsFFI) {}
|
||||
GenELF64KernelTy(const char *Name) : GenericKernelTy(Name), Func(nullptr) {}
|
||||
|
||||
/// Initialize the kernel.
|
||||
Error initImpl(GenericDeviceTy &Device, DeviceImageTy &Image) override {
|
||||
@ -84,7 +82,7 @@ struct GenELF64KernelTy : public GenericKernelTy {
|
||||
"invalid function for kernel %s", getName());
|
||||
|
||||
// Save the function pointer.
|
||||
Func = (void (*)())Global.getPtr();
|
||||
Func = reinterpret_cast<KernelTy *>(Global.getPtr());
|
||||
|
||||
KernelEnvironment.Configuration.ExecMode = OMP_TGT_EXEC_MODE_GENERIC;
|
||||
KernelEnvironment.Configuration.MayUseNestedParallelism = /*Unknown=*/2;
|
||||
@ -95,29 +93,17 @@ struct GenELF64KernelTy : public GenericKernelTy {
|
||||
return Plugin::success();
|
||||
}
|
||||
|
||||
/// Launch the kernel using the libffi.
|
||||
/// Launch the kernel using the arguments.
|
||||
Error launchImpl(GenericDeviceTy &GenericDevice, uint32_t NumThreads[3],
|
||||
uint32_t NumBlocks[3], uint32_t DynBlockMemSize,
|
||||
KernelArgsTy &KernelArgs, KernelLaunchParamsTy LaunchParams,
|
||||
AsyncInfoWrapperTy &AsyncInfoWrapper) const override {
|
||||
if (!SupportsFFI)
|
||||
if (KernelArgs.Version < OMP_KERNEL_ARG_VERSION)
|
||||
return Plugin::error(ErrorCode::UNSUPPORTED,
|
||||
"libffi is not available, cannot launch kernel");
|
||||
// Create a vector of ffi_types, one per argument.
|
||||
SmallVector<ffi_type *, 16> ArgTypes(KernelArgs.NumArgs, &ffi_type_pointer);
|
||||
ffi_type **ArgTypesPtr = (ArgTypes.size()) ? &ArgTypes[0] : nullptr;
|
||||
|
||||
// Prepare the cif structure before running the kernel function.
|
||||
ffi_cif Cif;
|
||||
ffi_status Status = ffi_prep_cif(&Cif, FFI_DEFAULT_ABI, KernelArgs.NumArgs,
|
||||
&ffi_type_void, ArgTypesPtr);
|
||||
if (Status != FFI_OK)
|
||||
return Plugin::error(ErrorCode::UNKNOWN, "error in ffi_prep_cif: %d",
|
||||
Status);
|
||||
|
||||
// Call the kernel function through libffi.
|
||||
long Return;
|
||||
ffi_call(&Cif, Func, &Return, (void **)LaunchParams.Ptrs);
|
||||
"Incompatible kernel argument version for plugin");
|
||||
// TODO: The data will need to be copied locally if we ever support
|
||||
// asynchronous kernel launches in the host interface.
|
||||
Func(LaunchParams.Data);
|
||||
return Plugin::success();
|
||||
}
|
||||
|
||||
@ -130,10 +116,10 @@ struct GenELF64KernelTy : public GenericKernelTy {
|
||||
}
|
||||
|
||||
private:
|
||||
/// Host kernel arguments are defined as a single, contiguous buffer.
|
||||
using KernelTy = void(void *);
|
||||
/// The kernel function to execute.
|
||||
void (*Func)(void);
|
||||
/// Whether this kernel supports FFI-based launch.
|
||||
bool SupportsFFI;
|
||||
KernelTy *Func;
|
||||
};
|
||||
|
||||
/// Class implementing the GenELF64 device images properties.
|
||||
@ -156,9 +142,8 @@ private:
|
||||
struct GenELF64DeviceTy : public GenericDeviceTy {
|
||||
/// Create the device with a specific id.
|
||||
GenELF64DeviceTy(GenericPluginTy &Plugin, int32_t DeviceId,
|
||||
int32_t NumDevices, bool SupportsFFI)
|
||||
: GenericDeviceTy(Plugin, DeviceId, NumDevices, GenELF64GridValues),
|
||||
SupportsFFI(SupportsFFI) {}
|
||||
int32_t NumDevices)
|
||||
: GenericDeviceTy(Plugin, DeviceId, NumDevices, GenELF64GridValues) {}
|
||||
|
||||
~GenELF64DeviceTy() {}
|
||||
|
||||
@ -190,7 +175,7 @@ struct GenELF64DeviceTy : public GenericDeviceTy {
|
||||
return Plugin::error(ErrorCode::OUT_OF_RESOURCES,
|
||||
"failed to allocate memory for GenELF64 kernel");
|
||||
|
||||
new (GenELF64Kernel) GenELF64KernelTy(Name, SupportsFFI);
|
||||
new (GenELF64Kernel) GenELF64KernelTy(Name);
|
||||
|
||||
return *GenELF64Kernel;
|
||||
}
|
||||
@ -442,9 +427,6 @@ private:
|
||||
1, // GV_Max_WG_Size
|
||||
1, // GV_Default_WG_Size
|
||||
};
|
||||
|
||||
/// Whether this device supports FFI-based launch.
|
||||
bool SupportsFFI;
|
||||
};
|
||||
|
||||
class GenELF64GlobalHandlerTy final : public GenericGlobalHandlerTy {
|
||||
@ -483,13 +465,6 @@ struct GenELF64PluginTy final : public GenericPluginTy {
|
||||
GenELF64PluginTy(GenELF64PluginTy &&) = delete;
|
||||
/// Initialize the plugin and return the number of devices.
|
||||
Expected<int32_t> initImpl() override {
|
||||
#ifdef USES_DYNAMIC_FFI
|
||||
SupportsFFI = ffi_init() == FFI_OK ? true : false;
|
||||
if (!SupportsFFI)
|
||||
ODBG(OLDT_Init)
|
||||
<< "libffi is not available, kernels will not be launched "
|
||||
"through libffi, and some features may be unavailable";
|
||||
#endif
|
||||
ODBG(OLDT_Init) << "GenELF64 plugin detected " << ODBG_IF_LEVEL(2)
|
||||
<< NUM_DEVICES << " " << ODBG_RESET_LEVEL() << "devices";
|
||||
|
||||
@ -502,7 +477,7 @@ struct GenELF64PluginTy final : public GenericPluginTy {
|
||||
/// Creates a generic ELF device.
|
||||
GenericDeviceTy *createDevice(GenericPluginTy &Plugin, int32_t DeviceId,
|
||||
int32_t NumDevices) override {
|
||||
return new GenELF64DeviceTy(Plugin, DeviceId, NumDevices, SupportsFFI);
|
||||
return new GenELF64DeviceTy(Plugin, DeviceId, NumDevices);
|
||||
}
|
||||
|
||||
/// Creates a generic global handler.
|
||||
@ -557,10 +532,6 @@ struct GenELF64PluginTy final : public GenericPluginTy {
|
||||
}
|
||||
|
||||
const char *getName() const override { return GETNAME(TARGET_NAME); }
|
||||
|
||||
private:
|
||||
/// Whether this plugin supports FFI-based launch.
|
||||
bool SupportsFFI = true;
|
||||
};
|
||||
|
||||
template <typename... ArgsTy>
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user