[NFC][AMDGPU] Add tests for dependent v_bfi instructions.
This commit adds a few tests which are used to test the codegen of nested v_bfi instructions. These instruction sequences are being generated when using the canonical form for bitfieldInsert and having the sequences being transformed by SimplifyDemandedBits. This is a pre-commit for a change which enables the backend to lower these instruction sequences into v_bfi instructions.
This commit is contained in:
Thomas Symalla
parent
1b06307aa4
commit
09fbdde42c
@ -1907,70 +1907,3 @@ entry:
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store i64 %scalar.use, i64 addrspace(1)* undef
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ret void
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}
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define i32 @v_bfi_seq_i32(i32 %x, i32 %y, i32 %z) {
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; GFX7-LABEL: v_bfi_seq_i32:
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; GFX7: ; %bb.0:
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; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX7-NEXT: v_lshlrev_b32_e32 v0, 20, v0
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; GFX7-NEXT: s_mov_b32 s4, 0xffc00
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; GFX7-NEXT: v_xor_b32_e32 v0, v0, v1
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; GFX7-NEXT: v_bfi_b32 v2, s4, v1, v2
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; GFX7-NEXT: v_and_b32_e32 v0, 0x3ff00000, v0
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; GFX7-NEXT: v_xor_b32_e32 v0, v0, v2
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; GFX7-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX8-LABEL: v_bfi_seq_i32:
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; GFX8: ; %bb.0:
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; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX8-NEXT: v_lshlrev_b32_e32 v0, 20, v0
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; GFX8-NEXT: s_mov_b32 s4, 0xffc00
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; GFX8-NEXT: v_xor_b32_e32 v0, v0, v1
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; GFX8-NEXT: v_bfi_b32 v2, s4, v1, v2
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; GFX8-NEXT: v_and_b32_e32 v0, 0x3ff00000, v0
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; GFX8-NEXT: v_xor_b32_e32 v0, v0, v2
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; GFX8-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX10-LABEL: v_bfi_seq_i32:
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; GFX10: ; %bb.0:
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; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
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; GFX10-NEXT: v_lshlrev_b32_e32 v0, 20, v0
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; GFX10-NEXT: v_xor_b32_e32 v0, v0, v1
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; GFX10-NEXT: v_bfi_b32 v1, 0xffc00, v1, v2
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; GFX10-NEXT: v_and_b32_e32 v0, 0x3ff00000, v0
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; GFX10-NEXT: v_xor_b32_e32 v0, v0, v1
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; GFX10-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX8-GISEL-LABEL: v_bfi_seq_i32:
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; GFX8-GISEL: ; %bb.0:
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; GFX8-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX8-GISEL-NEXT: v_lshlrev_b32_e32 v0, 20, v0
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; GFX8-GISEL-NEXT: v_and_b32_e32 v3, 0xffc00, v1
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; GFX8-GISEL-NEXT: v_and_b32_e32 v2, 0xfff003ff, v2
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; GFX8-GISEL-NEXT: v_xor_b32_e32 v0, v0, v1
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; GFX8-GISEL-NEXT: v_or_b32_e32 v2, v3, v2
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; GFX8-GISEL-NEXT: v_and_b32_e32 v0, 0x3ff00000, v0
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; GFX8-GISEL-NEXT: v_xor_b32_e32 v0, v0, v2
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; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX10-GISEL-LABEL: v_bfi_seq_i32:
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; GFX10-GISEL: ; %bb.0:
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; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX10-GISEL-NEXT: s_waitcnt_vscnt null, 0x0
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; GFX10-GISEL-NEXT: v_lshlrev_b32_e32 v0, 20, v0
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; GFX10-GISEL-NEXT: v_and_b32_e32 v2, 0xfff003ff, v2
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; GFX10-GISEL-NEXT: v_xor_b32_e32 v0, v0, v1
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; GFX10-GISEL-NEXT: v_and_or_b32 v1, 0xffc00, v1, v2
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; GFX10-GISEL-NEXT: v_and_b32_e32 v0, 0x3ff00000, v0
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; GFX10-GISEL-NEXT: v_xor_b32_e32 v0, v0, v1
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; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
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%1 = shl i32 %x, 20
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%2 = and i32 %y, 1047552
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%3 = and i32 %z, -1047553
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%4 = or i32 %2, %3
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%5 = xor i32 %1, %y
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%6 = and i32 %5, 1072693248
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%7 = xor i32 %6, %4
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ret i32 %7
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}
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116
llvm/test/CodeGen/AMDGPU/bfi_nested.ll
Normal file
116
llvm/test/CodeGen/AMDGPU/bfi_nested.ll
Normal file
@ -0,0 +1,116 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -march=amdgcn -mcpu=gfx1030 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GFX10 %s
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; When translating sequences like
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; bitfieldInsert(bitfieldInsert(...)),
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; where one bitfieldInsert's result is the base for another one,
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; the SimplifyDemandedBits transform executed during InstCombine
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; can merge the inverted mask of the outer bitfieldInsert and the
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; inverted mask of the inner bitfieldInsert. When it is possible,
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; e. g. if the constants are disjoint and the original inverted mask of
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; the outer bitfieldInsert can be reconstructed, aim to generate multiple
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; v_bfi instructions.
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define float @v_bfi_single_nesting_level (float %x, float %y, float %z) {
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; GFX10-LABEL: v_bfi_single_nesting_level:
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; GFX10: ; %bb.0: ; %.entry
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; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
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; GFX10-NEXT: v_mul_f32_e32 v0, 0x447fc000, v0
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; GFX10-NEXT: v_cvt_u32_f32_e32 v1, v1
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; GFX10-NEXT: v_mul_f32_e32 v2, 0x447fc000, v2
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; GFX10-NEXT: v_cvt_u32_f32_e32 v0, v0
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; GFX10-NEXT: v_lshlrev_b32_e32 v1, 10, v1
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; GFX10-NEXT: v_cvt_u32_f32_e32 v2, v2
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; GFX10-NEXT: v_lshlrev_b32_e32 v0, 20, v0
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; GFX10-NEXT: v_and_b32_e32 v1, 0xffc00, v1
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; GFX10-NEXT: v_and_b32_e32 v2, 0xc00003ff, v2
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; GFX10-NEXT: v_and_b32_e32 v0, 0x3ff00000, v0
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; GFX10-NEXT: v_or3_b32 v0, v1, v2, v0
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; GFX10-NEXT: s_setpc_b64 s[30:31]
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.entry:
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%mul.base = fmul reassoc nnan nsz arcp contract afn float %z, 1.023000e+03
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%mul.base.i32 = fptoui float %mul.base to i32
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%y.i32 = fptoui float %y to i32
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%shl.inner.insert = shl i32 %y.i32, 10
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%bfi1.and = and i32 %shl.inner.insert, 1047552
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%bfi1.andnot = and i32 %mul.base.i32, -1073740801
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%bfi1.or = or i32 %bfi1.and, %bfi1.andnot
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%mul.outer.insert = fmul reassoc nnan nsz arcp contract afn float %x, 1.023000e+03
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%mul.outer.insert.i32 = fptoui float %mul.outer.insert to i32
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%shl.outer.insert = shl i32 %mul.outer.insert.i32, 20
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%and.outer = and i32 %shl.outer.insert, 1072693248
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%or.outer = or i32 %bfi1.or, %and.outer
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%result = bitcast i32 %or.outer to float
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ret float %result
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}
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define float @v_bfi_no_nesting(float %x, float %y, float %z) {
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; GFX10-LABEL: v_bfi_no_nesting:
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; GFX10: ; %bb.0: ; %.entry
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; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
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; GFX10-NEXT: v_mul_f32_e32 v0, 0x447fc000, v0
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; GFX10-NEXT: v_cvt_u32_f32_e32 v1, v1
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; GFX10-NEXT: v_mul_f32_e32 v2, 0x447fc000, v2
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; GFX10-NEXT: v_cvt_u32_f32_e32 v0, v0
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; GFX10-NEXT: v_lshlrev_b32_e32 v1, 10, v1
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; GFX10-NEXT: v_cvt_u32_f32_e32 v2, v2
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; GFX10-NEXT: v_lshlrev_b32_e32 v0, 20, v0
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; GFX10-NEXT: v_and_b32_e32 v1, 0xffc00, v1
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; GFX10-NEXT: v_and_b32_e32 v2, 0xc0000400, v2
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; GFX10-NEXT: v_and_b32_e32 v0, 0x3ff00000, v0
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; GFX10-NEXT: v_or3_b32 v0, v1, v2, v0
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; GFX10-NEXT: s_setpc_b64 s[30:31]
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.entry:
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%mul.base = fmul reassoc nnan nsz arcp contract afn float %z, 1.023000e+03
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%mul.base.i32 = fptoui float %mul.base to i32
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%y.i32 = fptoui float %y to i32
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%shl.inner.insert = shl i32 %y.i32, 10
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%inner.and = and i32 %shl.inner.insert, 1047552
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%inner.and2 = and i32 %mul.base.i32, -1073740800
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%inner.or = or i32 %inner.and, %inner.and2
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%mul.outer.insert = fmul reassoc nnan nsz arcp contract afn float %x, 1.023000e+03
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%mul.outer.insert.i32 = fptoui float %mul.outer.insert to i32
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%shl.outer.insert = shl i32 %mul.outer.insert.i32, 20
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%and.outer = and i32 %shl.outer.insert, 1072693248
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%or.outer = or i32 %inner.or, %and.outer
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%result = bitcast i32 %or.outer to float
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ret float %result
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}
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define float @v_bfi_two_levels(float %x, float %y, float %z) {
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; GFX10-LABEL: v_bfi_two_levels:
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; GFX10: ; %bb.0: ; %.entry
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; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
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; GFX10-NEXT: v_mul_f32_e32 v0, 0x447fc000, v0
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; GFX10-NEXT: v_cvt_u32_f32_e32 v1, v1
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; GFX10-NEXT: v_cvt_u32_f32_e32 v2, v2
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; GFX10-NEXT: v_cvt_u32_f32_e32 v0, v0
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; GFX10-NEXT: v_lshlrev_b32_e32 v3, 5, v1
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; GFX10-NEXT: v_and_b32_e32 v2, 0xc000001f, v2
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; GFX10-NEXT: v_lshlrev_b32_e32 v1, 10, v1
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; GFX10-NEXT: v_lshlrev_b32_e32 v0, 20, v0
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; GFX10-NEXT: v_and_or_b32 v2, 0x3e0, v3, v2
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; GFX10-NEXT: v_and_b32_e32 v1, 0xffc00, v1
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; GFX10-NEXT: v_and_b32_e32 v0, 0x3ff00000, v0
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; GFX10-NEXT: v_or3_b32 v0, v2, v1, v0
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; GFX10-NEXT: s_setpc_b64 s[30:31]
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.entry:
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%y.i32 = fptoui float %y to i32
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%shl.insert.inner = shl i32 %y.i32, 5
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%and.insert.inner = and i32 %shl.insert.inner, 992
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%z.i32 = fptoui float %z to i32
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%base.inner = and i32 %z.i32, -1073741793
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%or.inner = or i32 %and.insert.inner , %base.inner
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%shl.insert.mid = shl i32 %y.i32, 10
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%and.insert.mid = and i32 %shl.insert.mid, 1047552
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%or.mid = or i32 %or.inner, %and.insert.mid
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%fmul.insert.outer = fmul reassoc nnan nsz arcp contract afn float %x, 1.023000e+03
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%cast.insert.outer = fptoui float %fmul.insert.outer to i32
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%shl.insert.outer = shl i32 %cast.insert.outer, 20
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%and.insert.outer = and i32 %shl.insert.outer, 1072693248
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%or.outer = or i32 %or.mid, %and.insert.outer
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%result = bitcast i32 %or.outer to float
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ret float %result
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}
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