[Bitcode] Add abbreviations for additional instructions (#146825)
Add abbreviations for icmp/fcmp, store and br, which are the most common instructions that don't have abbreviations yet. This requires increasing the abbreviation size to 5 bits. This gives about 3-5% bitcode size reductions for the clang build.
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@ -141,6 +141,7 @@ enum {
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// FUNCTION_BLOCK abbrev id's.
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FUNCTION_INST_LOAD_ABBREV = bitc::FIRST_APPLICATION_ABBREV,
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FUNCTION_INST_STORE_ABBREV,
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FUNCTION_INST_UNOP_ABBREV,
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FUNCTION_INST_UNOP_FLAGS_ABBREV,
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FUNCTION_INST_BINOP_ABBREV,
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@ -149,8 +150,12 @@ enum {
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FUNCTION_INST_CAST_FLAGS_ABBREV,
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FUNCTION_INST_RET_VOID_ABBREV,
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FUNCTION_INST_RET_VAL_ABBREV,
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FUNCTION_INST_BR_UNCOND_ABBREV,
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FUNCTION_INST_BR_COND_ABBREV,
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FUNCTION_INST_UNREACHABLE_ABBREV,
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FUNCTION_INST_GEP_ABBREV,
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FUNCTION_INST_CMP_ABBREV,
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FUNCTION_INST_CMP_FLAGS_ABBREV,
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FUNCTION_DEBUG_RECORD_VALUE_ABBREV,
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};
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@ -3197,12 +3202,17 @@ void ModuleBitcodeWriter::writeInstruction(const Instruction &I,
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case Instruction::FCmp: {
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// compare returning Int1Ty or vector of Int1Ty
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Code = bitc::FUNC_CODE_INST_CMP2;
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pushValueAndType(I.getOperand(0), InstID, Vals);
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AbbrevToUse = FUNCTION_INST_CMP_ABBREV;
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if (pushValueAndType(I.getOperand(0), InstID, Vals))
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AbbrevToUse = 0;
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pushValue(I.getOperand(1), InstID, Vals);
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Vals.push_back(cast<CmpInst>(I).getPredicate());
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uint64_t Flags = getOptimizationFlags(&I);
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if (Flags != 0)
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if (Flags != 0) {
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Vals.push_back(Flags);
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if (AbbrevToUse)
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AbbrevToUse = FUNCTION_INST_CMP_FLAGS_ABBREV;
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}
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break;
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}
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@ -3224,11 +3234,13 @@ void ModuleBitcodeWriter::writeInstruction(const Instruction &I,
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case Instruction::Br:
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{
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Code = bitc::FUNC_CODE_INST_BR;
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AbbrevToUse = FUNCTION_INST_BR_UNCOND_ABBREV;
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const BranchInst &II = cast<BranchInst>(I);
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Vals.push_back(VE.getValueID(II.getSuccessor(0)));
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if (II.isConditional()) {
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Vals.push_back(VE.getValueID(II.getSuccessor(1)));
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pushValue(II.getCondition(), InstID, Vals);
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AbbrevToUse = FUNCTION_INST_BR_COND_ABBREV;
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}
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}
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break;
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@ -3449,12 +3461,16 @@ void ModuleBitcodeWriter::writeInstruction(const Instruction &I,
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}
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break;
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case Instruction::Store:
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if (cast<StoreInst>(I).isAtomic())
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if (cast<StoreInst>(I).isAtomic()) {
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Code = bitc::FUNC_CODE_INST_STOREATOMIC;
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else
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} else {
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Code = bitc::FUNC_CODE_INST_STORE;
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pushValueAndType(I.getOperand(1), InstID, Vals); // ptrty + ptr
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pushValueAndType(I.getOperand(0), InstID, Vals); // valty + val
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AbbrevToUse = FUNCTION_INST_STORE_ABBREV;
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}
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if (pushValueAndType(I.getOperand(1), InstID, Vals)) // ptrty + ptr
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AbbrevToUse = 0;
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if (pushValueAndType(I.getOperand(0), InstID, Vals)) // valty + val
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AbbrevToUse = 0;
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Vals.push_back(getEncodedAlign(cast<StoreInst>(I).getAlign()));
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Vals.push_back(cast<StoreInst>(I).isVolatile());
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if (cast<StoreInst>(I).isAtomic()) {
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@ -3677,7 +3693,7 @@ void ModuleBitcodeWriter::writeFunction(
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// in the VST.
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FunctionToBitcodeIndex[&F] = Stream.GetCurrentBitNo();
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Stream.EnterSubblock(bitc::FUNCTION_BLOCK_ID, 4);
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Stream.EnterSubblock(bitc::FUNCTION_BLOCK_ID, 5);
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VE.incorporateFunction(F);
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SmallVector<unsigned, 64> Vals;
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@ -3952,6 +3968,17 @@ void ModuleBitcodeWriter::writeBlockInfo() {
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FUNCTION_INST_LOAD_ABBREV)
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llvm_unreachable("Unexpected abbrev ordering!");
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}
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{
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auto Abbv = std::make_shared<BitCodeAbbrev>();
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Abbv->Add(BitCodeAbbrevOp(bitc::FUNC_CODE_INST_STORE));
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Abbv->Add(ValAbbrevOp); // op1
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Abbv->Add(ValAbbrevOp); // op0
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Abbv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::VBR, 4)); // align
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Abbv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Fixed, 1)); // volatile
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if (Stream.EmitBlockInfoAbbrev(bitc::FUNCTION_BLOCK_ID, Abbv) !=
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FUNCTION_INST_STORE_ABBREV)
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llvm_unreachable("Unexpected abbrev ordering!");
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}
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{ // INST_UNOP abbrev for FUNCTION_BLOCK.
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auto Abbv = std::make_shared<BitCodeAbbrev>();
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Abbv->Add(BitCodeAbbrevOp(bitc::FUNC_CODE_INST_UNOP));
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@ -4029,6 +4056,26 @@ void ModuleBitcodeWriter::writeBlockInfo() {
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FUNCTION_INST_RET_VAL_ABBREV)
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llvm_unreachable("Unexpected abbrev ordering!");
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}
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{
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auto Abbv = std::make_shared<BitCodeAbbrev>();
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Abbv->Add(BitCodeAbbrevOp(bitc::FUNC_CODE_INST_BR));
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// TODO: Use different abbrev for absolute value reference (succ0)?
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Abbv->Add(ValAbbrevOp); // succ0
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if (Stream.EmitBlockInfoAbbrev(bitc::FUNCTION_BLOCK_ID, Abbv) !=
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FUNCTION_INST_BR_UNCOND_ABBREV)
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llvm_unreachable("Unexpected abbrev ordering!");
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}
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{
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auto Abbv = std::make_shared<BitCodeAbbrev>();
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Abbv->Add(BitCodeAbbrevOp(bitc::FUNC_CODE_INST_BR));
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// TODO: Use different abbrev for absolute value references (succ0, succ1)?
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Abbv->Add(ValAbbrevOp); // succ0
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Abbv->Add(ValAbbrevOp); // succ1
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Abbv->Add(ValAbbrevOp); // cond
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if (Stream.EmitBlockInfoAbbrev(bitc::FUNCTION_BLOCK_ID, Abbv) !=
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FUNCTION_INST_BR_COND_ABBREV)
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llvm_unreachable("Unexpected abbrev ordering!");
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}
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{ // INST_UNREACHABLE abbrev for FUNCTION_BLOCK.
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auto Abbv = std::make_shared<BitCodeAbbrev>();
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Abbv->Add(BitCodeAbbrevOp(bitc::FUNC_CODE_INST_UNREACHABLE));
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@ -4047,6 +4094,27 @@ void ModuleBitcodeWriter::writeBlockInfo() {
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FUNCTION_INST_GEP_ABBREV)
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llvm_unreachable("Unexpected abbrev ordering!");
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}
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{
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auto Abbv = std::make_shared<BitCodeAbbrev>();
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Abbv->Add(BitCodeAbbrevOp(bitc::FUNC_CODE_INST_CMP2));
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Abbv->Add(ValAbbrevOp); // op0
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Abbv->Add(ValAbbrevOp); // op1
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Abbv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Fixed, 6)); // pred
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if (Stream.EmitBlockInfoAbbrev(bitc::FUNCTION_BLOCK_ID, Abbv) !=
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FUNCTION_INST_CMP_ABBREV)
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llvm_unreachable("Unexpected abbrev ordering!");
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}
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{
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auto Abbv = std::make_shared<BitCodeAbbrev>();
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Abbv->Add(BitCodeAbbrevOp(bitc::FUNC_CODE_INST_CMP2));
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Abbv->Add(ValAbbrevOp); // op0
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Abbv->Add(ValAbbrevOp); // op1
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Abbv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Fixed, 6)); // pred
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Abbv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Fixed, 8)); // flags
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if (Stream.EmitBlockInfoAbbrev(bitc::FUNCTION_BLOCK_ID, Abbv) !=
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FUNCTION_INST_CMP_FLAGS_ABBREV)
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llvm_unreachable("Unexpected abbrev ordering!");
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}
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{
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auto Abbv = std::make_shared<BitCodeAbbrev>();
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Abbv->Add(BitCodeAbbrevOp(bitc::FUNC_CODE_DEBUG_RECORD_VALUE_SIMPLE));
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@ -48,7 +48,7 @@ define double @test_float_binops(i32 %a) nounwind {
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; between literals and the formal parameters.
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; CHECK: INST_GEP {{.*}}
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; CHECK: INST_LOAD {{.*}}op0=1 {{.*}}
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; CHECK: INST_CMP2 op0=1 {{.*}}
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; CHECK: INST_CMP2 {{.*}}op0=1 {{.*}}
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; CHECK: INST_RET {{.*}}op0=1
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define i1 @test_load(i32 %a, {i32, i32}* %ptr) nounwind {
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entry:
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