Revert "[AMDGPU] Speedup GCNDownwardRPTracker::advanceBeforeNext"
This reverts commit 2d09bec169277fb5a341249afacff532c7511756. It was causing assertion failures in some out-of-tree tests.
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@ -336,38 +336,23 @@ bool GCNDownwardRPTracker::advanceBeforeNext() {
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assert(SI.isValid());
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// Remove dead registers or mask bits.
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SmallSet<Register, 8> SeenRegs;
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for (auto &MO : LastTrackedMI->operands()) {
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if (!MO.isReg() || !MO.getReg().isVirtual())
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continue;
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if (MO.isUse() && !MO.readsReg())
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continue;
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if (!SeenRegs.insert(MO.getReg()).second)
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continue;
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const LiveInterval &LI = LIS.getInterval(MO.getReg());
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for (auto &It : LiveRegs) {
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const LiveInterval &LI = LIS.getInterval(It.first);
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if (LI.hasSubRanges()) {
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auto It = LiveRegs.end();
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for (const auto &S : LI.subranges()) {
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if (!S.liveAt(SI)) {
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if (It == LiveRegs.end()) {
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It = LiveRegs.find(MO.getReg());
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if (It == LiveRegs.end())
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llvm_unreachable("register isn't live");
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}
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auto PrevMask = It->second;
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It->second &= ~S.LaneMask;
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CurPressure.inc(MO.getReg(), PrevMask, It->second, *MRI);
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auto PrevMask = It.second;
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It.second &= ~S.LaneMask;
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CurPressure.inc(It.first, PrevMask, It.second, *MRI);
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}
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}
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if (It != LiveRegs.end() && It->second.none())
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LiveRegs.erase(It);
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} else if (!LI.liveAt(SI)) {
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auto It = LiveRegs.find(MO.getReg());
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if (It == LiveRegs.end())
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llvm_unreachable("register isn't live");
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CurPressure.inc(MO.getReg(), It->second, LaneBitmask::getNone(), *MRI);
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LiveRegs.erase(It);
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auto PrevMask = It.second;
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It.second = LaneBitmask::getNone();
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CurPressure.inc(It.first, PrevMask, It.second, *MRI);
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}
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if (It.second.none())
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LiveRegs.erase(It.first);
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}
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MaxPressure = max(MaxPressure, CurPressure);
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