Revert "[AMDGPU] Speedup GCNDownwardRPTracker::advanceBeforeNext"

This reverts commit 2d09bec169277fb5a341249afacff532c7511756.

It was causing assertion failures in some out-of-tree tests.
This commit is contained in:
Jay Foad 2022-12-02 14:07:11 +00:00
parent 26424c96c0
commit 0affe0c8cf

View File

@ -336,38 +336,23 @@ bool GCNDownwardRPTracker::advanceBeforeNext() {
assert(SI.isValid());
// Remove dead registers or mask bits.
SmallSet<Register, 8> SeenRegs;
for (auto &MO : LastTrackedMI->operands()) {
if (!MO.isReg() || !MO.getReg().isVirtual())
continue;
if (MO.isUse() && !MO.readsReg())
continue;
if (!SeenRegs.insert(MO.getReg()).second)
continue;
const LiveInterval &LI = LIS.getInterval(MO.getReg());
for (auto &It : LiveRegs) {
const LiveInterval &LI = LIS.getInterval(It.first);
if (LI.hasSubRanges()) {
auto It = LiveRegs.end();
for (const auto &S : LI.subranges()) {
if (!S.liveAt(SI)) {
if (It == LiveRegs.end()) {
It = LiveRegs.find(MO.getReg());
if (It == LiveRegs.end())
llvm_unreachable("register isn't live");
}
auto PrevMask = It->second;
It->second &= ~S.LaneMask;
CurPressure.inc(MO.getReg(), PrevMask, It->second, *MRI);
auto PrevMask = It.second;
It.second &= ~S.LaneMask;
CurPressure.inc(It.first, PrevMask, It.second, *MRI);
}
}
if (It != LiveRegs.end() && It->second.none())
LiveRegs.erase(It);
} else if (!LI.liveAt(SI)) {
auto It = LiveRegs.find(MO.getReg());
if (It == LiveRegs.end())
llvm_unreachable("register isn't live");
CurPressure.inc(MO.getReg(), It->second, LaneBitmask::getNone(), *MRI);
LiveRegs.erase(It);
auto PrevMask = It.second;
It.second = LaneBitmask::getNone();
CurPressure.inc(It.first, PrevMask, It.second, *MRI);
}
if (It.second.none())
LiveRegs.erase(It.first);
}
MaxPressure = max(MaxPressure, CurPressure);