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[RISCV] Add release notes for Zvabd (#185617)

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Pengcheng Wang 2026-03-11 14:28:42 +08:00 committed by GitHub
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clang/docs/ReleaseNotes.rst
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@ -416,6 +416,7 @@ RISC-V Support
^^^^^^^^^^^^^^
- Tenstorrent Ascalon D8 was renamed to Ascalon X. Use `tt-ascalon-x` with `-mcpu` or `-mtune`.
- Intrinsics were added for the 'Zvabd` (RISC-V Integer Vector Absolute Difference) extension.
CUDA/HIP Language Changes
^^^^^^^^^^^^^^^^^^^^^^^^^

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llvm/docs/ReleaseNotes.md
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@ -153,6 +153,7 @@ Changes to the RISC-V Backend
extensions.
* Adds experimental assembler support for the 'Zvabd` (RISC-V Integer Vector
Absolute Difference) extension.
* Adds CodeGen support for the 'Zvabd` extension.
* `-mcpu=spacemit-a100` was added.
* The opt-in `-riscv-enable-p-ext-simd-codegen` flag has been removed. P extension SIMD code generation is now enabled automatically if the P extension is supported.
* `-mcpu=xt-c910v2` and `-mcpu=xt-c920v2` were added.