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[RISCV] Use SHL_ADD in remaining strength reduce cases for MUL (#89789)

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The interesting bit is the zext folding. This is the first case where we
end up with a profitable fold of shNadd (zext x), y to shNadd.uw x, y.
See zext_mul68 from rv64zba.ll.

The test differences are cases where we can legally fold (only because
there's no one use check). These are not profitable or harmful, but we
can't a oneuse check without breaking the zext_mul68 case.

Note that XTHeadBa doesn't appear to have the equivalent patterns so
this only shows up in Zba.
This commit is contained in:
Philip Reames 2024-04-23 12:40:55 -07:00 committed by GitHub
parent dc8f6a8cda
commit 0c032fd542
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4 changed files with 12 additions and 12 deletions
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10
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
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@ -13449,9 +13449,8 @@ static SDValue expandMul(SDNode *N, SelectionDAG &DAG,
SDValue X = DAG.getFreeze(N->getOperand(0));
SDValue Shift1 =
DAG.getNode(ISD::SHL, DL, VT, X, DAG.getConstant(ShiftAmt, DL, VT));
SDValue Shift2 =
DAG.getNode(ISD::SHL, DL, VT, X, DAG.getConstant(ScaleShift, DL, VT));
return DAG.getNode(ISD::ADD, DL, VT, Shift1, Shift2);
return DAG.getNode(RISCVISD::SHL_ADD, DL, VT, X,
DAG.getConstant(ScaleShift, DL, VT), Shift1);
}
}
@ -13485,10 +13484,9 @@ static SDValue expandMul(SDNode *N, SelectionDAG &DAG,
SDValue X = DAG.getFreeze(N->getOperand(0));
SDValue Shift1 =
DAG.getNode(ISD::SHL, DL, VT, X, DAG.getConstant(ShiftAmt, DL, VT));
SDValue Shift2 =
DAG.getNode(ISD::SHL, DL, VT, X, DAG.getConstant(ScaleShift, DL, VT));
return DAG.getNode(ISD::ADD, DL, VT, Shift1,
DAG.getNode(ISD::ADD, DL, VT, Shift2, X));
DAG.getNode(RISCVISD::SHL_ADD, DL, VT, X,
DAG.getConstant(ScaleShift, DL, VT), X));
}
}

2
llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
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@ -747,6 +747,8 @@ foreach i = {1,2,3} in {
defvar shxadd_uw = !cast<Instruction>("SH"#i#"ADD_UW");
def : Pat<(i64 (add_like_non_imm12 (shl (and GPR:$rs1, 0xFFFFFFFF), (i64 i)), (XLenVT GPR:$rs2))),
(shxadd_uw GPR:$rs1, GPR:$rs2)>;
def : Pat<(i64 (riscv_shl_add (and GPR:$rs1, 0xFFFFFFFF), (i64 i), GPR:$rs2)),
(shxadd_uw GPR:$rs1, GPR:$rs2)>;
}
def : Pat<(i64 (add_like_non_imm12 (and (shl GPR:$rs1, (i64 1)), 0x1FFFFFFFF), (XLenVT GPR:$rs2))),

6
llvm/test/CodeGen/RISCV/rv64-legal-i32/xaluo.ll
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@ -810,9 +810,9 @@ define zeroext i1 @umulo2.i32(i32 signext %v1, ptr %res) {
;
; RV64ZBA-LABEL: umulo2.i32:
; RV64ZBA: # %bb.0: # %entry
; RV64ZBA-NEXT: zext.w a0, a0
; RV64ZBA-NEXT: sh1add a2, a0, a0
; RV64ZBA-NEXT: sh2add a2, a2, a0
; RV64ZBA-NEXT: zext.w a2, a0
; RV64ZBA-NEXT: sh1add.uw a0, a0, a2
; RV64ZBA-NEXT: sh2add a2, a0, a2
; RV64ZBA-NEXT: srli a0, a2, 32
; RV64ZBA-NEXT: snez a0, a0
; RV64ZBA-NEXT: sw a2, 0(a1)

6
llvm/test/CodeGen/RISCV/xaluo.ll
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@ -1759,9 +1759,9 @@ define zeroext i1 @umulo2.i32(i32 signext %v1, ptr %res) {
;
; RV64ZBA-LABEL: umulo2.i32:
; RV64ZBA: # %bb.0: # %entry
; RV64ZBA-NEXT: zext.w a0, a0
; RV64ZBA-NEXT: sh1add a2, a0, a0
; RV64ZBA-NEXT: sh2add a2, a2, a0
; RV64ZBA-NEXT: zext.w a2, a0
; RV64ZBA-NEXT: sh1add.uw a0, a0, a2
; RV64ZBA-NEXT: sh2add a2, a0, a2
; RV64ZBA-NEXT: srli a0, a2, 32
; RV64ZBA-NEXT: snez a0, a0
; RV64ZBA-NEXT: sw a2, 0(a1)