[AMDGPU][GFX90A][DOC][NFC] Update assembler syntax description
Summary of changes: - Enable register tuples with 9, 10, 11 and 12 registers (https://reviews.llvm.org/D138205). - Enable VOP3 variants of dot2c/dot4c/dot8c instructions (https://reviews.llvm.org/D138494). - Enable omod modifiers for v_max3_f16, v_min3_f16, etc. (https://reviews.llvm.org/D139469). - Enable abs and neg modifiers for v_cndmask_b32 (https://reviews.llvm.org/D135900). - Correct v_mov_b32_sdwa (it does not support abs and neg input modifiers yet). - Enable abs and neg modifiers for v_dot2c_f32_f16_dpp. - Minor corrections and improvements.
This commit is contained in:
Dmitry Preobrazhensky
parent
bcb457c68e
commit
0d0018e709
File diff suppressed because it is too large
Load Diff
@ -10,7 +10,7 @@
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FX Operand
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==========
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This is an *f32* or *f16* operand depending on instruction modifiers:
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This is a *f32* or *f16* operand depending on instruction modifiers:
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* Operand size is controlled by :ref:`m_op_sel_hi<amdgpu_synid_mad_mix_op_sel_hi>`.
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* Location of 16-bit operand is controlled by :ref:`m_op_sel<amdgpu_synid_mad_mix_op_sel>`.
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* Location of the 16-bit operand is controlled by :ref:`m_op_sel<amdgpu_synid_mad_mix_op_sel>`.
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@ -24,27 +24,27 @@ The bits of this operand have the following meaning:
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This operand may be specified as one of the following:
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* An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range 0..0xFFFF.
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* An *hwreg* value described below.
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* An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range from 0 to 0xFFFF.
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* An *hwreg* value which is described below.
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==================================== ============================================================================
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==================================== ===============================================================================
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Hwreg Value Syntax Description
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==================================== ============================================================================
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hwreg({0..63}) All bits of a register indicated by its *id*.
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hwreg(<*name*>) All bits of a register indicated by its *name*.
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hwreg({0..63}, {0..31}, {1..32}) Register bits indicated by register *id*, first bit *offset* and *size*.
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hwreg(<*name*>, {0..31}, {1..32}) Register bits indicated by register *name*, first bit *offset* and *size*.
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==================================== ============================================================================
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==================================== ===============================================================================
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hwreg({0..63}) All bits of a register indicated by the register *id*.
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hwreg(<*name*>) All bits of a register indicated by the register *name*.
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hwreg({0..63}, {0..31}, {1..32}) Register bits indicated by the register *id*, first bit *offset* and *size*.
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hwreg(<*name*>, {0..31}, {1..32}) Register bits indicated by the register *name*, first bit *offset* and *size*.
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==================================== ===============================================================================
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Numeric values may be specified as positive :ref:`integer numbers<amdgpu_synid_integer_number>`
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or :ref:`absolute expressions<amdgpu_synid_absolute_expression>`.
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Defined register *names* include:
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Predefined register *names* include:
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============================== ==========================================
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Name Description
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============================== ==========================================
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HW_REG_MODE Shader writeable mode bits.
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HW_REG_MODE Shader writable mode bits.
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HW_REG_STATUS Shader read-only status.
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HW_REG_TRAPSTS Trap status.
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HW_REG_HW_ID Id of wave, simd, compute unit, etc.
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@ -12,7 +12,7 @@ imask
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This operand is a mask which controls indexing mode for operands of subsequent instructions.
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Bits 0, 1 and 2 control indexing of *src0*, *src1* and *src2*, while bit 3 controls indexing of *dst*.
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Value 1 enables indexing and value 0 disables it.
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Value 1 enables indexing, and value 0 disables it.
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===== ========================================
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Bit Meaning
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@ -25,31 +25,31 @@ Value 1 enables indexing and value 0 disables it.
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This operand may be specified as one of the following:
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* An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range 0..15.
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* A *gpr_idx* value described below.
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* An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range from 0 to 15.
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* A *gpr_idx* value which is described below.
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==================================== ===========================================
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==================================== =============================================
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Gpr_idx Value Syntax Description
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==================================== ===========================================
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gpr_idx(*<operands>*) Enable indexing for specified *operands*
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==================================== =============================================
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gpr_idx(*<operand list>*) Enable indexing for the specified *operands*
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and disable it for the rest.
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*Operands* is a comma-separated list of
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*Operand list* is a comma-separated list of
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values which may include:
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* "SRC0" - enable *src0* indexing.
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* SRC0 - enable *src0* indexing.
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* "SRC1" - enable *src1* indexing.
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* SRC1 - enable *src1* indexing.
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* "SRC2" - enable *src2* indexing.
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* SRC2 - enable *src2* indexing.
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* "DST" - enable *dst* indexing.
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* DST - enable *dst* indexing.
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Each of these values may be specified only
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once.
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*Operands* list may be empty; this syntax
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*Operand list* may be empty; this syntax
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disables indexing for all operands.
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==================================== ===========================================
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==================================== =============================================
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Examples:
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@ -5,9 +5,9 @@
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* *
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**************************************************
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.. _amdgpu_synid_gfx90a_imm16_a04fb3:
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.. _amdgpu_synid_gfx90a_imm16_0533c2:
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imm16
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=====
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An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range 0..65535.
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An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range from -32768 to 65535.
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@ -5,9 +5,9 @@
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* *
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**************************************************
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.. _amdgpu_synid_gfx90a_imm16_73139a:
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.. _amdgpu_synid_gfx90a_imm16_169952:
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imm16
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=====
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An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range -32768..65535.
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An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range from 0 to 65535.
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@ -10,11 +10,11 @@
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label
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=====
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A branch target which is a 16-bit signed integer treated as a PC-relative dword offset.
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A branch target, which is a 16-bit signed integer treated as a PC-relative dword offset.
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This operand may be specified as one of the following:
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* An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range -32768..65535.
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* An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range from -32768 to 65535.
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* A :ref:`symbol<amdgpu_synid_symbol>` (for example, a label) representing a relocatable address in the same compilation unit where it is referred from. The value is handled as a 16-bit PC-relative dword offset to be resolved by a linker.
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Examples:
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@ -5,9 +5,9 @@
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* *
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**************************************************
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.. _amdgpu_synid_gfx90a_m_254bcb:
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.. _amdgpu_synid_gfx90a_m_28b494:
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m
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=
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This operand may be used with integer operand modifier :ref:`sext<amdgpu_synid_sext>`.
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This operand may be used with an integer operand modifier :ref:`sext<amdgpu_synid_sext>`.
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@ -5,9 +5,9 @@
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* *
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**************************************************
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.. _amdgpu_synid_gfx90a_m_f5d306:
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.. _amdgpu_synid_gfx90a_m_c141fc:
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m
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=
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This operand may be used with floating point operand modifiers :ref:`abs<amdgpu_synid_abs>` and :ref:`neg<amdgpu_synid_neg>`.
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This operand may be used with floating-point operand modifiers :ref:`abs<amdgpu_synid_abs>` and :ref:`neg<amdgpu_synid_neg>`.
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@ -24,8 +24,8 @@ A 16-bit message code. The bits of this operand have the following meaning:
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This operand may be specified as one of the following:
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* An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range 0..0xFFFF.
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* A *sendmsg* value described below.
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* An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range from 0 to 0xFFFF.
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* A *sendmsg* value which is described below.
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==================================== ====================================================
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Sendmsg Value Syntax Description
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@ -40,7 +40,7 @@ This operand may be specified as one of the following:
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*Op* may be specified using operation *name* or operation *id*.
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Stream *id* is an integer in the range 0..3.
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Stream *id* is an integer in the range from 0 to 3.
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Numeric values may be specified as positive :ref:`integer numbers<amdgpu_synid_integer_number>`
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or :ref:`absolute expressions<amdgpu_synid_absolute_expression>`.
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@ -73,7 +73,7 @@ Each message type supports specific operations:
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*Sendmsg* arguments are validated depending on how *type* value is specified:
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* If message *type* is specified by name, arguments values must satisfy limitations detailed in the table above.
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* If message *type* is specified as a number, each argument must not exceed corresponding value range (see the first table).
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* If message *type* is specified as a number, each argument must not exceed the corresponding value range (see the first table).
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Examples:
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@ -5,12 +5,12 @@
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* *
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**************************************************
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.. _amdgpu_synid_gfx90a_sbase_010ce0:
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.. _amdgpu_synid_gfx90a_sbase_b0aa25:
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sbase
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=====
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A 128-bit buffer resource constant for scalar memory operations which provides a base address, a size and a stride.
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A 128-bit buffer resource constant for scalar memory operations which provides a base address, a size, and a stride.
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*Size:* 4 dwords.
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@ -5,14 +5,14 @@
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* *
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**************************************************
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.. _amdgpu_synid_gfx90a_sdata_eb6f2a:
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.. _amdgpu_synid_gfx90a_sdata_45d924:
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sdata
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=====
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Input data for an atomic instruction.
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Optionally may serve as an output data:
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Optionally, this operand may be used to store output data:
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* If :ref:`glc<amdgpu_synid_glc>` is specified, gets the memory value before the operation.
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@ -5,14 +5,14 @@
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* *
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**************************************************
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.. _amdgpu_synid_gfx90a_sdata_aefe00:
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.. _amdgpu_synid_gfx90a_sdata_ba98a3:
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sdata
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=====
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Input data for an atomic instruction.
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Optionally may serve as an output data:
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Optionally, this operand may be used to store output data:
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* If :ref:`glc<amdgpu_synid_glc>` is specified, gets the memory value before the operation.
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@ -5,14 +5,14 @@
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* *
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**************************************************
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.. _amdgpu_synid_gfx90a_sdata_c6aec1:
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.. _amdgpu_synid_gfx90a_sdata_c1aec6:
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sdata
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=====
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Input data for an atomic instruction.
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Optionally may serve as an output data:
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Optionally, this operand may be used to store output data:
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* If :ref:`glc<amdgpu_synid_glc>` is specified, gets the memory value before the operation.
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@ -5,12 +5,12 @@
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* *
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**************************************************
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.. _amdgpu_synid_gfx90a_soffset_ba92ce:
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.. _amdgpu_synid_gfx90a_soffset_02ec85:
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soffset
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=======
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An unsigned offset from the base address. My be specified as either a register or a 20-bit immediate.
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An unsigned offset from the base address. May be specified as either a register or a 20-bit immediate.
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Note that an *immediate* offset may be specified using either :ref:`uimm20<amdgpu_synid_uimm20>` operand or :ref:`offset20u<amdgpu_synid_smem_offset20u>` modifier, but not both.
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@ -5,12 +5,12 @@
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* *
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**************************************************
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.. _amdgpu_synid_gfx90a_srsrc_e73d16:
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.. _amdgpu_synid_gfx90a_srsrc_80eef6:
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srsrc
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=====
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Buffer resource constant which defines the address and characteristics of the buffer in memory.
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Buffer resource constant, which defines the address and characteristics of the buffer in memory.
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*Size:* 4 dwords.
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@ -10,4 +10,4 @@
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Type Deviation
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==============
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*Type* of this operand differs from *type* :ref:`implied by the opcode<amdgpu_syn_instruction_mnemo>`. This tag specifies actual operand *type*.
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The *type* of this operand differs from the *type* :ref:`implied by the opcode<amdgpu_syn_instruction_mnemo>`. This tag specifies the actual operand *type*.
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@ -5,17 +5,15 @@
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* *
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**************************************************
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.. _amdgpu_synid_gfx90a_vaddr_5d0b42:
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.. _amdgpu_synid_gfx90a_vaddr_cc213c:
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vaddr
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=====
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Image address which includes from one to four dimensional coordinates and other data used to locate a position in the image.
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*Size:* 1, 2, 3, 4, 8 or 16 dwords. Actual size depends on opcode, specific image being handled and :ref:`a16<amdgpu_synid_a16>`.
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*Size:* 1-12 dwords. Actual size depends on opcode, specific image being handled and :ref:`a16<amdgpu_synid_a16>`.
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Note 1. Image format and dimensions are encoded in the image resource constant but not in the instruction.
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Note 2. Actually image address size may vary from 1 to 13 dwords, but assembler currently supports a limited range of register sequences.
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Note. Image format and dimensions are encoded in the image resource constant, but not in the instruction.
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*Operands:* :ref:`v<amdgpu_synid_v>`
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@ -5,14 +5,14 @@
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* *
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**************************************************
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.. _amdgpu_synid_gfx90a_vdata_8e9b87:
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.. _amdgpu_synid_gfx90a_vdata_0c567e:
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vdata
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=====
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Input data for an atomic instruction.
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Optionally may serve as an output data:
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Optionally, this operand may be used to store output data:
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* If :ref:`glc<amdgpu_synid_glc>` is specified, gets the memory value before the operation.
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@ -5,14 +5,14 @@
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* *
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**************************************************
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.. _amdgpu_synid_gfx90a_vdata_af2725:
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.. _amdgpu_synid_gfx90a_vdata_898c08:
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vdata
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=====
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Input data for an atomic instruction.
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Optionally may serve as an output data:
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Optionally, this operand may be used to store output data:
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* If :ref:`glc<amdgpu_synid_glc>` is specified, gets the memory value before the operation.
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@ -21,6 +21,6 @@ Optionally may serve as an output data:
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* :ref:`dmask<amdgpu_synid_dmask>` may specify 1 data element for 32-bit-per-pixel surfaces or 2 data elements for 64-bit-per-pixel surfaces. Each data element occupies 1 dword.
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Note: the surface data format is indicated in the image resource constant but not in the instruction.
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Note: the surface data format is indicated in the image resource constant, but not in the instruction.
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*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
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@ -5,14 +5,14 @@
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* *
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**************************************************
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.. _amdgpu_synid_gfx90a_vdata_ca6e5f:
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.. _amdgpu_synid_gfx90a_vdata_999247:
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vdata
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=====
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Input data for an atomic instruction.
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Optionally may serve as an output data:
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Optionally, this operand may be used to store output data:
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* If :ref:`glc<amdgpu_synid_glc>` is specified, gets the memory value before the operation.
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@ -21,6 +21,6 @@ Optionally may serve as an output data:
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* :ref:`dmask<amdgpu_synid_dmask>` may specify 2 data elements for 32-bit-per-pixel surfaces or 4 data elements for 64-bit-per-pixel surfaces. Each data element occupies 1 dword.
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Note: the surface data format is indicated in the image resource constant but not in the instruction.
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Note: the surface data format is indicated in the image resource constant, but not in the instruction.
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*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
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@ -5,14 +5,14 @@
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* *
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**************************************************
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.. _amdgpu_synid_gfx90a_vdata_2d0375:
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.. _amdgpu_synid_gfx90a_vdata_ae1132:
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vdata
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=====
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Input data for an atomic instruction.
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Optionally may serve as an output data:
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Optionally, this operand may be used to store output data:
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* If :ref:`glc<amdgpu_synid_glc>` is specified, gets the memory value before the operation.
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@ -5,14 +5,14 @@
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* *
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**************************************************
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.. _amdgpu_synid_gfx90a_vdata_2a60db:
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.. _amdgpu_synid_gfx90a_vdata_bbcfbb:
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vdata
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=====
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Input data for an atomic instruction.
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Optionally may serve as an output data:
|
||||
Optionally, this operand may be used to store output data:
|
||||
|
||||
* If :ref:`glc<amdgpu_synid_glc>` is specified, gets the memory value before the operation.
|
||||
|
||||
@ -5,7 +5,7 @@
|
||||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx90a_vdata_a5f23e:
|
||||
.. _amdgpu_synid_gfx90a_vdata_cbb01e:
|
||||
|
||||
vdata
|
||||
=====
|
||||
@ -14,7 +14,7 @@ Image data to store by an *image_store* instruction.
|
||||
|
||||
*Size:* depends on :ref:`dmask<amdgpu_synid_dmask>` and :ref:`d16<amdgpu_synid_d16>`:
|
||||
|
||||
* :ref:`dmask<amdgpu_synid_dmask>` may specify from 1 to 4 data elements. Each data element occupies either 32 bits or 16 bits depending on :ref:`d16<amdgpu_synid_d16>`.
|
||||
* :ref:`dmask<amdgpu_synid_dmask>` may specify from 1 to 4 data elements. Each data element occupies either 32 bits or 16 bits, depending on :ref:`d16<amdgpu_synid_d16>`.
|
||||
* :ref:`d16<amdgpu_synid_d16>` specifies that data in registers are packed; each value occupies 16 bits.
|
||||
|
||||
*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
|
||||
@ -5,16 +5,16 @@
|
||||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx90a_vdst_7c9848:
|
||||
.. _amdgpu_synid_gfx90a_vdst_a9ee3f:
|
||||
|
||||
vdst
|
||||
====
|
||||
|
||||
Image data to load by an image instruction.
|
||||
Image data to be loaded by an image instruction.
|
||||
|
||||
*Size:* depends on :ref:`dmask<amdgpu_synid_dmask>` and :ref:`d16<amdgpu_synid_d16>`:
|
||||
|
||||
* :ref:`dmask<amdgpu_synid_dmask>` may specify from 1 to 4 data elements. Each data element occupies either 32 bits or 16 bits depending on :ref:`d16<amdgpu_synid_d16>`.
|
||||
* :ref:`dmask<amdgpu_synid_dmask>` may specify from 1 to 4 data elements. Each data element occupies either 32 bits or 16 bits, depending on :ref:`d16<amdgpu_synid_d16>`.
|
||||
* :ref:`d16<amdgpu_synid_d16>` specifies that data elements in registers are packed; each value occupies 16 bits.
|
||||
|
||||
|
||||
@ -5,12 +5,12 @@
|
||||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx90a_vdst_f47b9b:
|
||||
.. _amdgpu_synid_gfx90a_vdst_f5eb9d:
|
||||
|
||||
vdst
|
||||
====
|
||||
|
||||
Image data to load by an image instruction.
|
||||
Image data to be loaded by an image instruction.
|
||||
|
||||
*Size:* depends on :ref:`dmask<amdgpu_synid_dmask>`:
|
||||
|
||||
@ -24,7 +24,7 @@ The bits of this operand have the following meaning:
|
||||
|
||||
This operand may be specified as one of the following:
|
||||
|
||||
* An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range 0..0xFFFF.
|
||||
* An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range from 0 to 0xFFFF.
|
||||
* A combination of *vmcnt*, *expcnt*, *lgkmcnt* and other values described below.
|
||||
|
||||
====================== ======================================================================
|
||||
@ -38,7 +38,8 @@ This operand may be specified as one of the following:
|
||||
lgkmcnt_sat(<*N*>) An LGKM_CNT value computed as min(*N*, the largest LGKM_CNT value).
|
||||
====================== ======================================================================
|
||||
|
||||
These values may be specified in any order. Spaces, ampersands and commas may be used as optional separators.
|
||||
These values may be specified in any order. Spaces, ampersands, and commas may be used as optional separators.
|
||||
If some values are omitted, the corresponding fields will default to their maximum value.
|
||||
|
||||
*N* is either an
|
||||
:ref:`integer number<amdgpu_synid_integer_number>` or an
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user