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[RISCV] Pass sign-extended value to isInt check in expandMul (#150211)

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In the `isInt` check that was added in #147661 we were passing the
zero-extended `uint64_t` value instead of the sign-extended one.

(cherry picked from commit d3937e2d12648caa49fd80f9520a391fde2f7ba5)
This commit is contained in:
Sudharsan Veeravalli 2025-07-25 05:47:09 +05:30 committed by Tobias Hieta
parent be21c1395e
commit 0d8606fc85
2 changed files with 28 additions and 1 deletions
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2
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
View File

@ -16013,7 +16013,7 @@ static SDValue expandMul(SDNode *N, SelectionDAG &DAG,
uint64_t MulAmt = CNode->getZExtValue();
// Don't do this if the Xqciac extension is enabled and the MulAmt in simm12.
if (Subtarget.hasVendorXqciac() && isInt<12>(MulAmt))
if (Subtarget.hasVendorXqciac() && isInt<12>(CNode->getSExtValue()))
return SDValue();
const bool HasShlAdd = Subtarget.hasStdExtZba() ||

27
llvm/test/CodeGen/RISCV/xqciac.ll
View File

@ -463,3 +463,30 @@ entry:
%add = add nsw i32 %shlc1, %shlc2
ret i32 %add
}
define i32 @testmuliaddnegimm(i32 %a) {
; RV32IM-LABEL: testmuliaddnegimm:
; RV32IM: # %bb.0:
; RV32IM-NEXT: slli a1, a0, 1
; RV32IM-NEXT: add a0, a1, a0
; RV32IM-NEXT: li a1, 3
; RV32IM-NEXT: sub a0, a1, a0
; RV32IM-NEXT: ret
;
; RV32IMXQCIAC-LABEL: testmuliaddnegimm:
; RV32IMXQCIAC: # %bb.0:
; RV32IMXQCIAC-NEXT: li a1, 3
; RV32IMXQCIAC-NEXT: qc.muliadd a1, a0, -3
; RV32IMXQCIAC-NEXT: mv a0, a1
; RV32IMXQCIAC-NEXT: ret
;
; RV32IZBAMXQCIAC-LABEL: testmuliaddnegimm:
; RV32IZBAMXQCIAC: # %bb.0:
; RV32IZBAMXQCIAC-NEXT: li a1, 3
; RV32IZBAMXQCIAC-NEXT: qc.muliadd a1, a0, -3
; RV32IZBAMXQCIAC-NEXT: mv a0, a1
; RV32IZBAMXQCIAC-NEXT: ret
%mul = mul i32 %a, -3
%add = add i32 %mul, 3
ret i32 %add
}