[RISCV] Move the passthru operand for RISCVISD::VRGATHER*_VL nodes. NFC
Put it before the VL instead of as the first operand. I want to add passthru to more operands, but the commutable ones like VADD_VL require the commutable operands to be operand 0 and 1. So we can't have the passthru as operand 0 for those.
This commit is contained in:
Craig Topper
parent
8ae0664282
commit
0efbf5bfbb
@ -1957,8 +1957,8 @@ static SDValue matchSplatAsGather(SDValue SplatVal, MVT VT, const SDLoc &DL,
|
||||
SDValue Mask, VL;
|
||||
std::tie(Mask, VL) = getDefaultVLOps(VT, ContainerVT, DL, DAG, Subtarget);
|
||||
|
||||
SDValue Gather = DAG.getNode(RISCVISD::VRGATHER_VX_VL, DL, ContainerVT,
|
||||
DAG.getUNDEF(ContainerVT), Vec, Idx, Mask, VL);
|
||||
SDValue Gather = DAG.getNode(RISCVISD::VRGATHER_VX_VL, DL, ContainerVT, Vec,
|
||||
Idx, Mask, DAG.getUNDEF(ContainerVT), VL);
|
||||
|
||||
if (!VT.isFixedLengthVector())
|
||||
return Gather;
|
||||
@ -2581,9 +2581,9 @@ static SDValue lowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG,
|
||||
|
||||
V1 = convertToScalableVector(ContainerVT, V1, DAG, Subtarget);
|
||||
assert(Lane < (int)NumElts && "Unexpected lane!");
|
||||
SDValue Gather = DAG.getNode(
|
||||
RISCVISD::VRGATHER_VX_VL, DL, ContainerVT, DAG.getUNDEF(ContainerVT),
|
||||
V1, DAG.getConstant(Lane, DL, XLenVT), TrueMask, VL);
|
||||
SDValue Gather = DAG.getNode(RISCVISD::VRGATHER_VX_VL, DL, ContainerVT,
|
||||
V1, DAG.getConstant(Lane, DL, XLenVT),
|
||||
TrueMask, DAG.getUNDEF(ContainerVT), VL);
|
||||
return convertFromScalableVector(VT, Gather, DAG, Subtarget);
|
||||
}
|
||||
}
|
||||
@ -2793,17 +2793,16 @@ static SDValue lowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG,
|
||||
// that's beneficial.
|
||||
if (LHSIndexCounts.size() == 1) {
|
||||
int SplatIndex = LHSIndexCounts.begin()->getFirst();
|
||||
Gather = DAG.getNode(
|
||||
GatherVXOpc, DL, ContainerVT, DAG.getUNDEF(ContainerVT), V1,
|
||||
DAG.getConstant(SplatIndex, DL, XLenVT), TrueMask, VL);
|
||||
Gather = DAG.getNode(GatherVXOpc, DL, ContainerVT, V1,
|
||||
DAG.getConstant(SplatIndex, DL, XLenVT), TrueMask,
|
||||
DAG.getUNDEF(ContainerVT), VL);
|
||||
} else {
|
||||
SDValue LHSIndices = DAG.getBuildVector(IndexVT, DL, GatherIndicesLHS);
|
||||
LHSIndices =
|
||||
convertToScalableVector(IndexContainerVT, LHSIndices, DAG, Subtarget);
|
||||
|
||||
Gather =
|
||||
DAG.getNode(GatherVVOpc, DL, ContainerVT, DAG.getUNDEF(ContainerVT),
|
||||
V1, LHSIndices, TrueMask, VL);
|
||||
Gather = DAG.getNode(GatherVVOpc, DL, ContainerVT, V1, LHSIndices,
|
||||
TrueMask, DAG.getUNDEF(ContainerVT), VL);
|
||||
}
|
||||
}
|
||||
|
||||
@ -2821,15 +2820,15 @@ static SDValue lowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG,
|
||||
// that's beneficial.
|
||||
if (RHSIndexCounts.size() == 1) {
|
||||
int SplatIndex = RHSIndexCounts.begin()->getFirst();
|
||||
Gather =
|
||||
DAG.getNode(GatherVXOpc, DL, ContainerVT, Gather, V2,
|
||||
DAG.getConstant(SplatIndex, DL, XLenVT), SelectMask, VL);
|
||||
Gather = DAG.getNode(GatherVXOpc, DL, ContainerVT, V2,
|
||||
DAG.getConstant(SplatIndex, DL, XLenVT), SelectMask,
|
||||
Gather, VL);
|
||||
} else {
|
||||
SDValue RHSIndices = DAG.getBuildVector(IndexVT, DL, GatherIndicesRHS);
|
||||
RHSIndices =
|
||||
convertToScalableVector(IndexContainerVT, RHSIndices, DAG, Subtarget);
|
||||
Gather = DAG.getNode(GatherVVOpc, DL, ContainerVT, Gather, V2, RHSIndices,
|
||||
SelectMask, VL);
|
||||
Gather = DAG.getNode(GatherVVOpc, DL, ContainerVT, V2, RHSIndices,
|
||||
SelectMask, Gather, VL);
|
||||
}
|
||||
}
|
||||
|
||||
@ -5690,8 +5689,8 @@ SDValue RISCVTargetLowering::lowerVECTOR_REVERSE(SDValue Op,
|
||||
SDValue Indices =
|
||||
DAG.getNode(RISCVISD::SUB_VL, DL, IntVT, SplatVL, VID, Mask, VL);
|
||||
|
||||
return DAG.getNode(GatherOpc, DL, VecVT, DAG.getUNDEF(VecVT),
|
||||
Op.getOperand(0), Indices, Mask, VL);
|
||||
return DAG.getNode(GatherOpc, DL, VecVT, Op.getOperand(0), Indices, Mask,
|
||||
DAG.getUNDEF(VecVT), VL);
|
||||
}
|
||||
|
||||
SDValue RISCVTargetLowering::lowerVECTOR_SPLICE(SDValue Op,
|
||||
|
||||
@ -290,7 +290,7 @@ enum NodeType : unsigned {
|
||||
VMSET_VL,
|
||||
|
||||
// Matches the semantics of vrgather.vx and vrgather.vv with extra operands
|
||||
// for passthru and VL. First operand is the passthru operand.
|
||||
// for passthru and VL. Operands are (src, index, mask, passthru, vl).
|
||||
VRGATHER_VX_VL,
|
||||
VRGATHER_VV_VL,
|
||||
VRGATHEREI16_VV_VL,
|
||||
|
||||
@ -145,30 +145,30 @@ def riscv_setcc_vl : SDNode<"RISCVISD::SETCC_VL",
|
||||
def riscv_vrgather_vx_vl : SDNode<"RISCVISD::VRGATHER_VX_VL",
|
||||
SDTypeProfile<1, 5, [SDTCisVec<0>,
|
||||
SDTCisSameAs<0, 1>,
|
||||
SDTCisSameAs<0, 2>,
|
||||
SDTCisVT<3, XLenVT>,
|
||||
SDTCVecEltisVT<4, i1>,
|
||||
SDTCisSameNumEltsAs<0, 4>,
|
||||
SDTCisVT<2, XLenVT>,
|
||||
SDTCVecEltisVT<3, i1>,
|
||||
SDTCisSameNumEltsAs<0, 3>,
|
||||
SDTCisSameAs<0, 4>,
|
||||
SDTCisVT<5, XLenVT>]>>;
|
||||
def riscv_vrgather_vv_vl : SDNode<"RISCVISD::VRGATHER_VV_VL",
|
||||
SDTypeProfile<1, 5, [SDTCisVec<0>,
|
||||
SDTCisSameAs<0, 1>,
|
||||
SDTCisSameAs<0, 2>,
|
||||
SDTCisInt<3>,
|
||||
SDTCisInt<2>,
|
||||
SDTCisSameNumEltsAs<0, 2>,
|
||||
SDTCisSameSizeAs<0, 2>,
|
||||
SDTCVecEltisVT<3, i1>,
|
||||
SDTCisSameNumEltsAs<0, 3>,
|
||||
SDTCisSameSizeAs<0, 3>,
|
||||
SDTCVecEltisVT<4, i1>,
|
||||
SDTCisSameNumEltsAs<0, 4>,
|
||||
SDTCisSameAs<0, 4>,
|
||||
SDTCisVT<5, XLenVT>]>>;
|
||||
def riscv_vrgatherei16_vv_vl : SDNode<"RISCVISD::VRGATHEREI16_VV_VL",
|
||||
SDTypeProfile<1, 5, [SDTCisVec<0>,
|
||||
SDTCisSameAs<0, 1>,
|
||||
SDTCisSameAs<0, 2>,
|
||||
SDTCisInt<3>,
|
||||
SDTCVecEltisVT<3, i16>,
|
||||
SDTCisInt<2>,
|
||||
SDTCVecEltisVT<2, i16>,
|
||||
SDTCisSameNumEltsAs<0, 2>,
|
||||
SDTCVecEltisVT<3, i1>,
|
||||
SDTCisSameNumEltsAs<0, 3>,
|
||||
SDTCVecEltisVT<4, i1>,
|
||||
SDTCisSameNumEltsAs<0, 4>,
|
||||
SDTCisSameAs<0, 4>,
|
||||
SDTCisVT<5, XLenVT>]>>;
|
||||
|
||||
def SDT_RISCVSelect_VL : SDTypeProfile<1, 4, [
|
||||
@ -1839,25 +1839,25 @@ foreach vti = AllIntegerVectors in {
|
||||
vti.RegClass:$merge,
|
||||
(vti.Scalar vti.ScalarRegClass:$rs1), GPR:$vl, vti.Log2SEW)>;
|
||||
|
||||
def : Pat<(vti.Vector (riscv_vrgather_vv_vl vti.RegClass:$merge,
|
||||
vti.RegClass:$rs2,
|
||||
def : Pat<(vti.Vector (riscv_vrgather_vv_vl vti.RegClass:$rs2,
|
||||
vti.RegClass:$rs1,
|
||||
(vti.Mask V0),
|
||||
vti.RegClass:$merge,
|
||||
VLOpFrag)),
|
||||
(!cast<Instruction>("PseudoVRGATHER_VV_"# vti.LMul.MX#"_MASK")
|
||||
vti.RegClass:$merge, vti.RegClass:$rs2, vti.RegClass:$rs1,
|
||||
(vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>;
|
||||
def : Pat<(vti.Vector (riscv_vrgather_vx_vl vti.RegClass:$merge,
|
||||
vti.RegClass:$rs2, GPR:$rs1,
|
||||
def : Pat<(vti.Vector (riscv_vrgather_vx_vl vti.RegClass:$rs2, GPR:$rs1,
|
||||
(vti.Mask V0),
|
||||
vti.RegClass:$merge,
|
||||
VLOpFrag)),
|
||||
(!cast<Instruction>("PseudoVRGATHER_VX_"# vti.LMul.MX#"_MASK")
|
||||
vti.RegClass:$merge, vti.RegClass:$rs2, GPR:$rs1,
|
||||
(vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>;
|
||||
def : Pat<(vti.Vector (riscv_vrgather_vx_vl vti.RegClass:$merge,
|
||||
vti.RegClass:$rs2,
|
||||
def : Pat<(vti.Vector (riscv_vrgather_vx_vl vti.RegClass:$rs2,
|
||||
uimm5:$imm,
|
||||
(vti.Mask V0),
|
||||
vti.RegClass:$merge,
|
||||
VLOpFrag)),
|
||||
(!cast<Instruction>("PseudoVRGATHER_VI_"# vti.LMul.MX#"_MASK")
|
||||
vti.RegClass:$merge, vti.RegClass:$rs2, uimm5:$imm,
|
||||
@ -1873,10 +1873,10 @@ foreach vti = AllIntegerVectors in {
|
||||
defvar inst = "PseudoVRGATHEREI16_VV_" # vti.LMul.MX # "_" # emul_str;
|
||||
|
||||
def : Pat<(vti.Vector
|
||||
(riscv_vrgatherei16_vv_vl vti.RegClass:$merge,
|
||||
vti.RegClass:$rs2,
|
||||
(riscv_vrgatherei16_vv_vl vti.RegClass:$rs2,
|
||||
(ivti.Vector ivti.RegClass:$rs1),
|
||||
(vti.Mask V0),
|
||||
vti.RegClass:$merge,
|
||||
VLOpFrag)),
|
||||
(!cast<Instruction>(inst#"_MASK")
|
||||
vti.RegClass:$merge, vti.RegClass:$rs2, ivti.RegClass:$rs1,
|
||||
@ -1904,26 +1904,26 @@ foreach vti = AllFloatVectors in {
|
||||
defvar ivti = GetIntVTypeInfo<vti>.Vti;
|
||||
|
||||
def : Pat<(vti.Vector
|
||||
(riscv_vrgather_vv_vl vti.RegClass:$merge,
|
||||
vti.RegClass:$rs2,
|
||||
(riscv_vrgather_vv_vl vti.RegClass:$rs2,
|
||||
(ivti.Vector vti.RegClass:$rs1),
|
||||
(vti.Mask V0),
|
||||
vti.RegClass:$merge,
|
||||
VLOpFrag)),
|
||||
(!cast<Instruction>("PseudoVRGATHER_VV_"# vti.LMul.MX#"_MASK")
|
||||
vti.RegClass:$merge, vti.RegClass:$rs2, vti.RegClass:$rs1,
|
||||
(vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>;
|
||||
def : Pat<(vti.Vector (riscv_vrgather_vx_vl vti.RegClass:$merge,
|
||||
vti.RegClass:$rs2, GPR:$rs1,
|
||||
def : Pat<(vti.Vector (riscv_vrgather_vx_vl vti.RegClass:$rs2, GPR:$rs1,
|
||||
(vti.Mask V0),
|
||||
vti.RegClass:$merge,
|
||||
VLOpFrag)),
|
||||
(!cast<Instruction>("PseudoVRGATHER_VX_"# vti.LMul.MX#"_MASK")
|
||||
vti.RegClass:$merge, vti.RegClass:$rs2, GPR:$rs1,
|
||||
(vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>;
|
||||
def : Pat<(vti.Vector
|
||||
(riscv_vrgather_vx_vl vti.RegClass:$merge,
|
||||
vti.RegClass:$rs2,
|
||||
(riscv_vrgather_vx_vl vti.RegClass:$rs2,
|
||||
uimm5:$imm,
|
||||
(vti.Mask V0),
|
||||
vti.RegClass:$merge,
|
||||
VLOpFrag)),
|
||||
(!cast<Instruction>("PseudoVRGATHER_VI_"# vti.LMul.MX#"_MASK")
|
||||
vti.RegClass:$merge, vti.RegClass:$rs2, uimm5:$imm,
|
||||
@ -1938,10 +1938,10 @@ foreach vti = AllFloatVectors in {
|
||||
defvar inst = "PseudoVRGATHEREI16_VV_" # vti.LMul.MX # "_" # emul_str;
|
||||
|
||||
def : Pat<(vti.Vector
|
||||
(riscv_vrgatherei16_vv_vl vti.RegClass:$merge,
|
||||
vti.RegClass:$rs2,
|
||||
(riscv_vrgatherei16_vv_vl vti.RegClass:$rs2,
|
||||
(ivti.Vector ivti.RegClass:$rs1),
|
||||
(vti.Mask V0),
|
||||
vti.RegClass:$merge,
|
||||
VLOpFrag)),
|
||||
(!cast<Instruction>(inst#"_MASK")
|
||||
vti.RegClass:$merge, vti.RegClass:$rs2, ivti.RegClass:$rs1,
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user