diff --git a/clang/lib/CIR/CodeGen/CIRGenBuilder.h b/clang/lib/CIR/CodeGen/CIRGenBuilder.h index 6cf27126e3bc..fb047919b003 100644 --- a/clang/lib/CIR/CodeGen/CIRGenBuilder.h +++ b/clang/lib/CIR/CodeGen/CIRGenBuilder.h @@ -397,6 +397,43 @@ public: } bool isInt(mlir::Type i) { return mlir::isa(i); } + cir::IntType getExtendedIntTy(cir::IntType ty, bool isSigned) { + switch (ty.getWidth()) { + case 8: + return isSigned ? typeCache.sInt16Ty : typeCache.uInt16Ty; + case 16: + return isSigned ? typeCache.sInt32Ty : typeCache.uInt32Ty; + case 32: + return isSigned ? typeCache.sInt64Ty : typeCache.uInt64Ty; + default: + llvm_unreachable("NYI"); + } + } + + cir::IntType getTruncatedIntTy(cir::IntType ty, bool isSigned) { + switch (ty.getWidth()) { + case 16: + return isSigned ? typeCache.sInt8Ty : typeCache.uInt8Ty; + case 32: + return isSigned ? typeCache.sInt16Ty : typeCache.uInt16Ty; + case 64: + return isSigned ? typeCache.sInt32Ty : typeCache.uInt32Ty; + default: + llvm_unreachable("NYI"); + } + } + + cir::VectorType + getExtendedOrTruncatedElementVectorType(cir::VectorType vt, bool isExtended, + bool isSigned = false) { + auto elementTy = mlir::dyn_cast_or_null(vt.getElementType()); + assert(elementTy && "expected int vector"); + return cir::VectorType::get(isExtended + ? getExtendedIntTy(elementTy, isSigned) + : getTruncatedIntTy(elementTy, isSigned), + vt.getSize()); + } + // Fetch the type representing a pointer to unsigned int8 values. cir::PointerType getUInt8PtrTy() { return typeCache.uInt8PtrTy; } diff --git a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp index 2a74ab45bbdf..d9d303cd07b9 100644 --- a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp +++ b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp @@ -472,6 +472,14 @@ static mlir::Value emitCommonNeonBuiltinExpr( case NEON::BI__builtin_neon_vfmlslq_high_f16: case NEON::BI__builtin_neon_vmmlaq_s32: case NEON::BI__builtin_neon_vmmlaq_u32: + cgf.cgm.errorNYI(expr->getSourceRange(), + std::string("unimplemented AArch64 builtin call: ") + + ctx.BuiltinInfo.getName(builtinID)); + return mlir::Value{}; + case NEON::BI__builtin_neon_vmul_v: + case NEON::BI__builtin_neon_vmulq_v: + return cgf.getBuilder().emitIntrinsicCallOp(loc, "aarch64.neon.pmul", vTy, + ops); case NEON::BI__builtin_neon_vusmmlaq_s32: case NEON::BI__builtin_neon_vusdot_s32: case NEON::BI__builtin_neon_vusdotq_s32: @@ -2229,11 +2237,18 @@ CIRGenFunction::emitAArch64BuiltinExpr(unsigned builtinID, const CallExpr *expr, case NEON::BI__builtin_neon_vfmas_laneq_f32: case NEON::BI__builtin_neon_vfmad_lane_f64: case NEON::BI__builtin_neon_vfmad_laneq_f64: - case NEON::BI__builtin_neon_vmull_v: cgm.errorNYI(expr->getSourceRange(), std::string("unimplemented AArch64 builtin call: ") + getContext().BuiltinInfo.getName(builtinID)); return mlir::Value{}; + case NEON::BI__builtin_neon_vmull_v: { + intrName = usgn ? "aarch64.neon.umull" : "aarch64.neon.smull"; + if (type.isPoly()) + intrName = "aarch64.neon.pmull"; + cir::VectorType argTy = builder.getExtendedOrTruncatedElementVectorType( + ty, /*isExtended*/ false, !usgn); + return emitNeonCall(cgm, builder, {argTy, argTy}, ops, intrName, ty, loc); + } case NEON::BI__builtin_neon_vmax_v: case NEON::BI__builtin_neon_vmaxq_v: intrName = usgn ? "aarch64.neon.umax" : "aarch64.neon.smax"; diff --git a/clang/test/CodeGen/AArch64/neon-intrinsics.c b/clang/test/CodeGen/AArch64/neon-intrinsics.c index faef9ce2689b..80bb22cc43c7 100644 --- a/clang/test/CodeGen/AArch64/neon-intrinsics.c +++ b/clang/test/CodeGen/AArch64/neon-intrinsics.c @@ -539,26 +539,6 @@ float64x2_t test_vmulq_f64(float64x2_t v1, float64x2_t v2) { return vmulq_f64(v1, v2); } -// CHECK-LABEL: define dso_local <8 x i8> @test_vmul_p8( -// CHECK-SAME: <8 x i8> noundef [[V1:%.*]], <8 x i8> noundef [[V2:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[VMUL_V_I:%.*]] = call <8 x i8> @llvm.aarch64.neon.pmul.v8i8(<8 x i8> [[V1]], <8 x i8> [[V2]]) -// CHECK-NEXT: ret <8 x i8> [[VMUL_V_I]] -// -poly8x8_t test_vmul_p8(poly8x8_t v1, poly8x8_t v2) { - return vmul_p8(v1, v2); -} - -// CHECK-LABEL: define dso_local <16 x i8> @test_vmulq_p8( -// CHECK-SAME: <16 x i8> noundef [[V1:%.*]], <16 x i8> noundef [[V2:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[VMULQ_V_I:%.*]] = call <16 x i8> @llvm.aarch64.neon.pmul.v16i8(<16 x i8> [[V1]], <16 x i8> [[V2]]) -// CHECK-NEXT: ret <16 x i8> [[VMULQ_V_I]] -// -poly8x16_t test_vmulq_p8(poly8x16_t v1, poly8x16_t v2) { - return vmulq_p8(v1, v2); -} - // CHECK-LABEL: define dso_local <8 x i8> @test_vmla_s8( // CHECK-SAME: <8 x i8> noundef [[V1:%.*]], <8 x i8> noundef [[V2:%.*]], <8 x i8> noundef [[V3:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] @@ -10830,170 +10810,6 @@ uint64x2_t test_vabal_high_u32(uint64x2_t a, uint32x4_t b, uint32x4_t c) { return vabal_high_u32(a, b, c); } -// CHECK-LABEL: define dso_local <8 x i16> @test_vmull_s8( -// CHECK-SAME: <8 x i8> noundef [[A:%.*]], <8 x i8> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[VMULL_I:%.*]] = call <8 x i16> @llvm.aarch64.neon.smull.v8i16(<8 x i8> [[A]], <8 x i8> [[B]]) -// CHECK-NEXT: ret <8 x i16> [[VMULL_I]] -// -int16x8_t test_vmull_s8(int8x8_t a, int8x8_t b) { - return vmull_s8(a, b); -} - -// CHECK-LABEL: define dso_local <4 x i32> @test_vmull_s16( -// CHECK-SAME: <4 x i16> noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[B]] to <8 x i8> -// CHECK-NEXT: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> -// CHECK-NEXT: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16> -// CHECK-NEXT: [[VMULL2_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> [[VMULL_I]], <4 x i16> [[VMULL1_I]]) -// CHECK-NEXT: ret <4 x i32> [[VMULL2_I]] -// -int32x4_t test_vmull_s16(int16x4_t a, int16x4_t b) { - return vmull_s16(a, b); -} - -// CHECK-LABEL: define dso_local <2 x i64> @test_vmull_s32( -// CHECK-SAME: <2 x i32> noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[B]] to <8 x i8> -// CHECK-NEXT: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> -// CHECK-NEXT: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32> -// CHECK-NEXT: [[VMULL2_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32> [[VMULL_I]], <2 x i32> [[VMULL1_I]]) -// CHECK-NEXT: ret <2 x i64> [[VMULL2_I]] -// -int64x2_t test_vmull_s32(int32x2_t a, int32x2_t b) { - return vmull_s32(a, b); -} - -// CHECK-LABEL: define dso_local <8 x i16> @test_vmull_u8( -// CHECK-SAME: <8 x i8> noundef [[A:%.*]], <8 x i8> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[VMULL_I:%.*]] = call <8 x i16> @llvm.aarch64.neon.umull.v8i16(<8 x i8> [[A]], <8 x i8> [[B]]) -// CHECK-NEXT: ret <8 x i16> [[VMULL_I]] -// -uint16x8_t test_vmull_u8(uint8x8_t a, uint8x8_t b) { - return vmull_u8(a, b); -} - -// CHECK-LABEL: define dso_local <4 x i32> @test_vmull_u16( -// CHECK-SAME: <4 x i16> noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[B]] to <8 x i8> -// CHECK-NEXT: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> -// CHECK-NEXT: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16> -// CHECK-NEXT: [[VMULL2_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.umull.v4i32(<4 x i16> [[VMULL_I]], <4 x i16> [[VMULL1_I]]) -// CHECK-NEXT: ret <4 x i32> [[VMULL2_I]] -// -uint32x4_t test_vmull_u16(uint16x4_t a, uint16x4_t b) { - return vmull_u16(a, b); -} - -// CHECK-LABEL: define dso_local <2 x i64> @test_vmull_u32( -// CHECK-SAME: <2 x i32> noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[B]] to <8 x i8> -// CHECK-NEXT: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> -// CHECK-NEXT: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32> -// CHECK-NEXT: [[VMULL2_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.umull.v2i64(<2 x i32> [[VMULL_I]], <2 x i32> [[VMULL1_I]]) -// CHECK-NEXT: ret <2 x i64> [[VMULL2_I]] -// -uint64x2_t test_vmull_u32(uint32x2_t a, uint32x2_t b) { - return vmull_u32(a, b); -} - -// CHECK-LABEL: define dso_local <8 x i16> @test_vmull_high_s8( -// CHECK-SAME: <16 x i8> noundef [[A:%.*]], <16 x i8> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[SHUFFLE_I5_I:%.*]] = shufflevector <16 x i8> [[A]], <16 x i8> [[A]], <8 x i32> -// CHECK-NEXT: [[SHUFFLE_I_I:%.*]] = shufflevector <16 x i8> [[B]], <16 x i8> [[B]], <8 x i32> -// CHECK-NEXT: [[VMULL_I_I:%.*]] = call <8 x i16> @llvm.aarch64.neon.smull.v8i16(<8 x i8> [[SHUFFLE_I5_I]], <8 x i8> [[SHUFFLE_I_I]]) -// CHECK-NEXT: ret <8 x i16> [[VMULL_I_I]] -// -int16x8_t test_vmull_high_s8(int8x16_t a, int8x16_t b) { - return vmull_high_s8(a, b); -} - -// CHECK-LABEL: define dso_local <4 x i32> @test_vmull_high_s16( -// CHECK-SAME: <8 x i16> noundef [[A:%.*]], <8 x i16> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[SHUFFLE_I5_I:%.*]] = shufflevector <8 x i16> [[A]], <8 x i16> [[A]], <4 x i32> -// CHECK-NEXT: [[SHUFFLE_I_I:%.*]] = shufflevector <8 x i16> [[B]], <8 x i16> [[B]], <4 x i32> -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[SHUFFLE_I5_I]] to <8 x i8> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[SHUFFLE_I_I]] to <8 x i8> -// CHECK-NEXT: [[VMULL_I_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> -// CHECK-NEXT: [[VMULL1_I_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16> -// CHECK-NEXT: [[VMULL2_I_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> [[VMULL_I_I]], <4 x i16> [[VMULL1_I_I]]) -// CHECK-NEXT: ret <4 x i32> [[VMULL2_I_I]] -// -int32x4_t test_vmull_high_s16(int16x8_t a, int16x8_t b) { - return vmull_high_s16(a, b); -} - -// CHECK-LABEL: define dso_local <2 x i64> @test_vmull_high_s32( -// CHECK-SAME: <4 x i32> noundef [[A:%.*]], <4 x i32> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[SHUFFLE_I5_I:%.*]] = shufflevector <4 x i32> [[A]], <4 x i32> [[A]], <2 x i32> -// CHECK-NEXT: [[SHUFFLE_I_I:%.*]] = shufflevector <4 x i32> [[B]], <4 x i32> [[B]], <2 x i32> -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[SHUFFLE_I5_I]] to <8 x i8> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[SHUFFLE_I_I]] to <8 x i8> -// CHECK-NEXT: [[VMULL_I_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> -// CHECK-NEXT: [[VMULL1_I_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32> -// CHECK-NEXT: [[VMULL2_I_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32> [[VMULL_I_I]], <2 x i32> [[VMULL1_I_I]]) -// CHECK-NEXT: ret <2 x i64> [[VMULL2_I_I]] -// -int64x2_t test_vmull_high_s32(int32x4_t a, int32x4_t b) { - return vmull_high_s32(a, b); -} - -// CHECK-LABEL: define dso_local <8 x i16> @test_vmull_high_u8( -// CHECK-SAME: <16 x i8> noundef [[A:%.*]], <16 x i8> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[SHUFFLE_I5_I:%.*]] = shufflevector <16 x i8> [[A]], <16 x i8> [[A]], <8 x i32> -// CHECK-NEXT: [[SHUFFLE_I_I:%.*]] = shufflevector <16 x i8> [[B]], <16 x i8> [[B]], <8 x i32> -// CHECK-NEXT: [[VMULL_I_I:%.*]] = call <8 x i16> @llvm.aarch64.neon.umull.v8i16(<8 x i8> [[SHUFFLE_I5_I]], <8 x i8> [[SHUFFLE_I_I]]) -// CHECK-NEXT: ret <8 x i16> [[VMULL_I_I]] -// -uint16x8_t test_vmull_high_u8(uint8x16_t a, uint8x16_t b) { - return vmull_high_u8(a, b); -} - -// CHECK-LABEL: define dso_local <4 x i32> @test_vmull_high_u16( -// CHECK-SAME: <8 x i16> noundef [[A:%.*]], <8 x i16> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[SHUFFLE_I5_I:%.*]] = shufflevector <8 x i16> [[A]], <8 x i16> [[A]], <4 x i32> -// CHECK-NEXT: [[SHUFFLE_I_I:%.*]] = shufflevector <8 x i16> [[B]], <8 x i16> [[B]], <4 x i32> -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[SHUFFLE_I5_I]] to <8 x i8> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[SHUFFLE_I_I]] to <8 x i8> -// CHECK-NEXT: [[VMULL_I_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> -// CHECK-NEXT: [[VMULL1_I_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16> -// CHECK-NEXT: [[VMULL2_I_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.umull.v4i32(<4 x i16> [[VMULL_I_I]], <4 x i16> [[VMULL1_I_I]]) -// CHECK-NEXT: ret <4 x i32> [[VMULL2_I_I]] -// -uint32x4_t test_vmull_high_u16(uint16x8_t a, uint16x8_t b) { - return vmull_high_u16(a, b); -} - -// CHECK-LABEL: define dso_local <2 x i64> @test_vmull_high_u32( -// CHECK-SAME: <4 x i32> noundef [[A:%.*]], <4 x i32> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[SHUFFLE_I5_I:%.*]] = shufflevector <4 x i32> [[A]], <4 x i32> [[A]], <2 x i32> -// CHECK-NEXT: [[SHUFFLE_I_I:%.*]] = shufflevector <4 x i32> [[B]], <4 x i32> [[B]], <2 x i32> -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[SHUFFLE_I5_I]] to <8 x i8> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[SHUFFLE_I_I]] to <8 x i8> -// CHECK-NEXT: [[VMULL_I_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> -// CHECK-NEXT: [[VMULL1_I_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32> -// CHECK-NEXT: [[VMULL2_I_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.umull.v2i64(<2 x i32> [[VMULL_I_I]], <2 x i32> [[VMULL1_I_I]]) -// CHECK-NEXT: ret <2 x i64> [[VMULL2_I_I]] -// -uint64x2_t test_vmull_high_u32(uint32x4_t a, uint32x4_t b) { - return vmull_high_u32(a, b); -} - // CHECK-LABEL: define dso_local <8 x i16> @test_vmlal_s8( // CHECK-SAME: <8 x i16> noundef [[A:%.*]], <8 x i8> noundef [[B:%.*]], <8 x i8> noundef [[C:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] @@ -11558,28 +11374,6 @@ int64x2_t test_vqdmlsl_high_s32(int64x2_t a, int32x4_t b, int32x4_t c) { return vqdmlsl_high_s32(a, b, c); } -// CHECK-LABEL: define dso_local <8 x i16> @test_vmull_p8( -// CHECK-SAME: <8 x i8> noundef [[A:%.*]], <8 x i8> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[VMULL_I:%.*]] = call <8 x i16> @llvm.aarch64.neon.pmull.v8i16(<8 x i8> [[A]], <8 x i8> [[B]]) -// CHECK-NEXT: ret <8 x i16> [[VMULL_I]] -// -poly16x8_t test_vmull_p8(poly8x8_t a, poly8x8_t b) { - return vmull_p8(a, b); -} - -// CHECK-LABEL: define dso_local <8 x i16> @test_vmull_high_p8( -// CHECK-SAME: <16 x i8> noundef [[A:%.*]], <16 x i8> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[SHUFFLE_I5:%.*]] = shufflevector <16 x i8> [[A]], <16 x i8> [[A]], <8 x i32> -// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <16 x i8> [[B]], <16 x i8> [[B]], <8 x i32> -// CHECK-NEXT: [[VMULL_I_I:%.*]] = call <8 x i16> @llvm.aarch64.neon.pmull.v8i16(<8 x i8> [[SHUFFLE_I5]], <8 x i8> [[SHUFFLE_I]]) -// CHECK-NEXT: ret <8 x i16> [[VMULL_I_I]] -// -poly16x8_t test_vmull_high_p8(poly8x16_t a, poly8x16_t b) { - return vmull_high_p8(a, b); -} - // CHECK-LABEL: define dso_local i64 @test_vaddd_s64( // CHECK-SAME: i64 noundef [[A:%.*]], i64 noundef [[B:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] diff --git a/clang/test/CodeGen/AArch64/neon/intrinsics.c b/clang/test/CodeGen/AArch64/neon/intrinsics.c index 1c4639fbe572..6fd5bfdc9817 100644 --- a/clang/test/CodeGen/AArch64/neon/intrinsics.c +++ b/clang/test/CodeGen/AArch64/neon/intrinsics.c @@ -1275,3 +1275,246 @@ float64x2_t test_vmaxnmq_f64(float64x2_t v1, float64x2_t v2) { return vmaxnmq_f64(v1, v2); } +//===------------------------------------------------------===// +// 2.1.1.2.8. Widening Multiplication +//===------------------------------------------------------===// + +// LLVM-LABEL: @test_vmull_s8( +// CIR-LABEL: @vmull_s8( +int16x8_t test_vmull_s8(int8x8_t a, int8x8_t b) { + // CIR: cir.call_llvm_intrinsic "aarch64.neon.smull" %{{.*}}, %{{.*}} : (!cir.vector<8 x !s8i>, !cir.vector<8 x !s8i>) -> !cir.vector<8 x !s16i> + +// LLVM-SAME: <8 x i8> {{.*}} [[A:%.*]], <8 x i8> {{.*}} [[B:%.*]]) +// LLVM: [[VMULL_I:%.*]] = call <8 x i16> @llvm.aarch64.neon.smull.v8i16(<8 x i8> [[A]], <8 x i8> [[B]]) +// LLVM-NEXT: ret <8 x i16> [[VMULL_I]] + return vmull_s8(a, b); +} + +// LLVM-LABEL: @test_vmull_s16( +// CIR-LABEL: @vmull_s16( +int32x4_t test_vmull_s16(int16x4_t a, int16x4_t b) { +// CIR: cir.call_llvm_intrinsic "aarch64.neon.smull" %{{.*}}, %{{.*}} : (!cir.vector<4 x !s16i>, !cir.vector<4 x !s16i>) -> !cir.vector<4 x !s32i> + +// LLVM-SAME: <4 x i16> {{.*}} [[A:%.*]], <4 x i16> {{.*}} [[B:%.*]]) +// LLVM: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8> +// LLVM-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[B]] to <8 x i8> +// LLVM-NEXT: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> +// LLVM-NEXT: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16> +// LLVM-NEXT: [[VMULL2_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> [[VMULL_I]], <4 x i16> [[VMULL1_I]]) +// LLVM-NEXT: ret <4 x i32> [[VMULL2_I]] + return vmull_s16(a, b); +} + +// LLVM-LABEL: @test_vmull_s32( +// CIR-LABEL: @vmull_s32( +int64x2_t test_vmull_s32(int32x2_t a, int32x2_t b) { +// CIR: cir.call_llvm_intrinsic "aarch64.neon.smull" %{{.*}}, %{{.*}} : (!cir.vector<2 x !s32i>, !cir.vector<2 x !s32i>) -> !cir.vector<2 x !s64i> + +// LLVM-SAME: <2 x i32> {{.*}} [[A:%.*]], <2 x i32> {{.*}} [[B:%.*]]) +// LLVM: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8> +// LLVM-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[B]] to <8 x i8> +// LLVM-NEXT: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> +// LLVM-NEXT: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32> +// LLVM-NEXT: [[VMULL2_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32> [[VMULL_I]], <2 x i32> [[VMULL1_I]]) +// LLVM-NEXT: ret <2 x i64> [[VMULL2_I]] + return vmull_s32(a, b); +} + +// LLVM-LABEL: @test_vmull_u8( +// CIR-LABEL: @vmull_u8( +uint16x8_t test_vmull_u8(uint8x8_t a, uint8x8_t b) { +// CIR: cir.call_llvm_intrinsic "aarch64.neon.umull" %{{.*}}, %{{.*}} : (!cir.vector<8 x !u8i>, !cir.vector<8 x !u8i>) -> !cir.vector<8 x !u16i> + +// LLVM-SAME: <8 x i8> {{.*}} [[A:%.*]], <8 x i8> {{.*}} [[B:%.*]]) +// LLVM: [[VMULL_I:%.*]] = call <8 x i16> @llvm.aarch64.neon.umull.v8i16(<8 x i8> [[A]], <8 x i8> [[B]]) +// LLVM-NEXT: ret <8 x i16> [[VMULL_I]] + return vmull_u8(a, b); +} + +// LLVM-LABEL: @test_vmull_u16( +// CIR-LABEL: @vmull_u16( +uint32x4_t test_vmull_u16(uint16x4_t a, uint16x4_t b) { +// CIR: cir.call_llvm_intrinsic "aarch64.neon.umull" %{{.*}}, %{{.*}} : (!cir.vector<4 x !u16i>, !cir.vector<4 x !u16i>) -> !cir.vector<4 x !u32i> + +// LLVM-SAME: <4 x i16> {{.*}} [[A:%.*]], <4 x i16> {{.*}} [[B:%.*]]) +// LLVM: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8> +// LLVM-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[B]] to <8 x i8> +// LLVM-NEXT: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> +// LLVM-NEXT: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16> +// LLVM-NEXT: [[VMULL2_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.umull.v4i32(<4 x i16> [[VMULL_I]], <4 x i16> [[VMULL1_I]]) +// LLVM-NEXT: ret <4 x i32> [[VMULL2_I]] + return vmull_u16(a, b); +} + +// LLVM-LABEL: @test_vmull_u32( +// CIR-LABEL: @vmull_u32( +uint64x2_t test_vmull_u32(uint32x2_t a, uint32x2_t b) { +// CIR: cir.call_llvm_intrinsic "aarch64.neon.umull" %{{.*}}, %{{.*}} : (!cir.vector<2 x !u32i>, !cir.vector<2 x !u32i>) -> !cir.vector<2 x !u64i> + +// LLVM-SAME: <2 x i32> {{.*}} [[A:%.*]], <2 x i32> {{.*}} [[B:%.*]]) +// LLVM: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8> +// LLVM-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[B]] to <8 x i8> +// LLVM-NEXT: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> +// LLVM-NEXT: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32> +// LLVM-NEXT: [[VMULL2_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.umull.v2i64(<2 x i32> [[VMULL_I]], <2 x i32> [[VMULL1_I]]) +// LLVM-NEXT: ret <2 x i64> [[VMULL2_I]] + return vmull_u32(a, b); +} + +// LLVM-LABEL: @test_vmull_high_s8( +// CIR-LABEL: @vmull_high_s8( +int16x8_t test_vmull_high_s8(int8x16_t a, int8x16_t b) { +// CIR: [[HIGH_A:%.*]] = cir.call @vget_high_s8 +// CIR: [[HIGH_B:%.*]] = cir.call @vget_high_s8 +// CIR: cir.call @vmull_s8([[HIGH_A]], [[HIGH_B]]) + +// LLVM-SAME: <16 x i8> {{.*}} [[A:%.*]], <16 x i8> {{.*}} [[B:%.*]]) +// LLVM: [[SHUFFLE_I5_I:%.*]] = shufflevector <16 x i8> [[A]], <16 x i8> [[A]], <8 x i32> +// LLVM-NEXT: [[SHUFFLE_I_I:%.*]] = shufflevector <16 x i8> [[B]], <16 x i8> [[B]], <8 x i32> +// LLVM-NEXT: [[VMULL_I_I:%.*]] = call <8 x i16> @llvm.aarch64.neon.smull.v8i16(<8 x i8> [[SHUFFLE_I5_I]], <8 x i8> [[SHUFFLE_I_I]]) +// LLVM-NEXT: ret <8 x i16> [[VMULL_I_I]] + return vmull_high_s8(a, b); +} + +// LLVM-LABEL: @test_vmull_high_s16( +// CIR-LABEL: @vmull_high_s16( +int32x4_t test_vmull_high_s16(int16x8_t a, int16x8_t b) { +// CIR: [[HIGH_A:%.*]] = cir.call @vget_high_s16 +// CIR: [[HIGH_B:%.*]] = cir.call @vget_high_s16 +// CIR: {{%.*}} = cir.call @vmull_s16([[HIGH_A]], [[HIGH_B]]) + +// LLVM-SAME: <8 x i16> {{.*}} [[A:%.*]], <8 x i16> {{.*}} [[B:%.*]]) +// LLVM: [[SHUFFLE_I5_I:%.*]] = shufflevector <8 x i16> [[A]], <8 x i16> [[A]], <4 x i32> +// LLVM-NEXT: [[SHUFFLE_I_I:%.*]] = shufflevector <8 x i16> [[B]], <8 x i16> [[B]], <4 x i32> +// LLVM-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[SHUFFLE_I5_I]] to <8 x i8> +// LLVM-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[SHUFFLE_I_I]] to <8 x i8> +// LLVM-NEXT: [[VMULL_I_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> +// LLVM-NEXT: [[VMULL1_I_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16> +// LLVM-NEXT: [[VMULL2_I_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> [[VMULL_I_I]], <4 x i16> [[VMULL1_I_I]]) +// LLVM-NEXT: ret <4 x i32> [[VMULL2_I_I]] + return vmull_high_s16(a, b); +} + +// LLVM-LABEL: @test_vmull_high_s32( +// CIR-LABEL: @vmull_high_s32( +int64x2_t test_vmull_high_s32(int32x4_t a, int32x4_t b) { +// CIR: [[HIGH_A:%.*]] = cir.call @vget_high_s32 +// CIR: [[HIGH_B:%.*]] = cir.call @vget_high_s32 +// CIR: {{%.*}} = cir.call @vmull_s32([[HIGH_A]], [[HIGH_B]]) + +// LLVM-SAME: <4 x i32> {{.*}} [[A:%.*]], <4 x i32> {{.*}} [[B:%.*]]) +// LLVM: [[SHUFFLE_I5_I:%.*]] = shufflevector <4 x i32> [[A]], <4 x i32> [[A]], <2 x i32> +// LLVM-NEXT: [[SHUFFLE_I_I:%.*]] = shufflevector <4 x i32> [[B]], <4 x i32> [[B]], <2 x i32> +// LLVM-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[SHUFFLE_I5_I]] to <8 x i8> +// LLVM-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[SHUFFLE_I_I]] to <8 x i8> +// LLVM-NEXT: [[VMULL_I_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> +// LLVM-NEXT: [[VMULL1_I_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32> +// LLVM-NEXT: [[VMULL2_I_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32> [[VMULL_I_I]], <2 x i32> [[VMULL1_I_I]]) +// LLVM-NEXT: ret <2 x i64> [[VMULL2_I_I]] + return vmull_high_s32(a, b); +} + +// LLVM-LABEL: @test_vmull_high_u8( +// CIR-LABEL: @vmull_high_u8( +uint16x8_t test_vmull_high_u8(uint8x16_t a, uint8x16_t b) { +// CIR: [[HIGH_A:%.*]] = cir.call @vget_high_u8 +// CIR: [[HIGH_B:%.*]] = cir.call @vget_high_u8 +// CIR: {{%.*}} = cir.call @vmull_u8([[HIGH_A]], [[HIGH_B]]) + +// LLVM-SAME: <16 x i8> {{.*}} [[A:%.*]], <16 x i8> {{.*}} [[B:%.*]]) +// LLVM: [[SHUFFLE_I5_I:%.*]] = shufflevector <16 x i8> [[A]], <16 x i8> [[A]], <8 x i32> +// LLVM-NEXT: [[SHUFFLE_I_I:%.*]] = shufflevector <16 x i8> [[B]], <16 x i8> [[B]], <8 x i32> +// LLVM-NEXT: [[VMULL_I_I:%.*]] = call <8 x i16> @llvm.aarch64.neon.umull.v8i16(<8 x i8> [[SHUFFLE_I5_I]], <8 x i8> [[SHUFFLE_I_I]]) +// LLVM-NEXT: ret <8 x i16> [[VMULL_I_I]] + return vmull_high_u8(a, b); +} + +// LLVM-LABEL: @test_vmull_high_u16( +// CIR-LABEL: @vmull_high_u16( +uint32x4_t test_vmull_high_u16(uint16x8_t a, uint16x8_t b) { +// CIR: [[HIGH_A:%.*]] = cir.call @vget_high_u16 +// CIR: [[HIGH_B:%.*]] = cir.call @vget_high_u16 +// CIR: {{%.*}} = cir.call @vmull_u16([[HIGH_A]], [[HIGH_B]]) + +// LLVM-SAME: <8 x i16> {{.*}} [[A:%.*]], <8 x i16> {{.*}} [[B:%.*]]) +// LLVM: [[SHUFFLE_I5_I:%.*]] = shufflevector <8 x i16> [[A]], <8 x i16> [[A]], <4 x i32> +// LLVM-NEXT: [[SHUFFLE_I_I:%.*]] = shufflevector <8 x i16> [[B]], <8 x i16> [[B]], <4 x i32> +// LLVM-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[SHUFFLE_I5_I]] to <8 x i8> +// LLVM-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[SHUFFLE_I_I]] to <8 x i8> +// LLVM-NEXT: [[VMULL_I_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> +// LLVM-NEXT: [[VMULL1_I_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16> +// LLVM-NEXT: [[VMULL2_I_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.umull.v4i32(<4 x i16> [[VMULL_I_I]], <4 x i16> [[VMULL1_I_I]]) +// LLVM-NEXT: ret <4 x i32> [[VMULL2_I_I]] + return vmull_high_u16(a, b); +} + +// LLVM-LABEL: @test_vmull_high_u32( +// CIR-LABEL: @vmull_high_u32( +uint64x2_t test_vmull_high_u32(uint32x4_t a, uint32x4_t b) { +// CIR: [[HIGH_A:%.*]] = cir.call @vget_high_u32 +// CIR: [[HIGH_B:%.*]] = cir.call @vget_high_u32 +// CIR: {{%.*}} = cir.call @vmull_u32([[HIGH_A]], [[HIGH_B]]) + +// LLVM-SAME: <4 x i32> {{.*}} [[A:%.*]], <4 x i32> {{.*}} [[B:%.*]]) +// LLVM: [[SHUFFLE_I5_I:%.*]] = shufflevector <4 x i32> [[A]], <4 x i32> [[A]], <2 x i32> +// LLVM-NEXT: [[SHUFFLE_I_I:%.*]] = shufflevector <4 x i32> [[B]], <4 x i32> [[B]], <2 x i32> +// LLVM-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[SHUFFLE_I5_I]] to <8 x i8> +// LLVM-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[SHUFFLE_I_I]] to <8 x i8> +// LLVM-NEXT: [[VMULL_I_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> +// LLVM-NEXT: [[VMULL1_I_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32> +// LLVM-NEXT: [[VMULL2_I_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.umull.v2i64(<2 x i32> [[VMULL_I_I]], <2 x i32> [[VMULL1_I_I]]) +// LLVM-NEXT: ret <2 x i64> [[VMULL2_I_I]] + return vmull_high_u32(a, b); +} + +//===------------------------------------------------------===// +// 2.1.1.3.1. Polynomial Multiply +//===------------------------------------------------------===// + +// LLVM-LABEL: @test_vmul_p8( +// CIR-LABEL: @vmul_p8( +poly8x8_t test_vmul_p8(poly8x8_t v1, poly8x8_t v2) { +// CIR: cir.call_llvm_intrinsic "aarch64.neon.pmul" %{{.*}}, %{{.*}} : (!cir.vector<8 x !s8i>, !cir.vector<8 x !s8i>) -> !cir.vector<8 x !s8i> + +// LLVM-SAME: <8 x i8> {{.*}} [[V1:%.*]], <8 x i8> {{.*}} [[V2:%.*]]) +// LLVM: [[VMUL_V_I:%.*]] = call <8 x i8> @llvm.aarch64.neon.pmul.v8i8(<8 x i8> [[V1]], <8 x i8> [[V2]]) +// LLVM-NEXT: ret <8 x i8> [[VMUL_V_I]] + return vmul_p8(v1, v2); +} + +// LLVM-LABEL: @test_vmulq_p8( +// CIR-LABEL: @vmulq_p8( +poly8x16_t test_vmulq_p8(poly8x16_t v1, poly8x16_t v2) { +// CIR: cir.call_llvm_intrinsic "aarch64.neon.pmul" %{{.*}}, %{{.*}} : (!cir.vector<16 x !s8i>, !cir.vector<16 x !s8i>) -> !cir.vector<16 x !s8i> + +// LLVM-SAME: <16 x i8> {{.*}} [[V1:%.*]], <16 x i8> {{.*}} [[V2:%.*]]) +// LLVM: [[VMULQ_V_I:%.*]] = call <16 x i8> @llvm.aarch64.neon.pmul.v16i8(<16 x i8> [[V1]], <16 x i8> [[V2]]) +// LLVM-NEXT: ret <16 x i8> [[VMULQ_V_I]] + return vmulq_p8(v1, v2); +} + +// LLVM-LABEL: @test_vmull_p8( +// CIR-LABEL: @vmull_p8( +poly16x8_t test_vmull_p8(poly8x8_t a, poly8x8_t b) { +// CIR: cir.call_llvm_intrinsic "aarch64.neon.pmull" %{{.*}}, %{{.*}} : (!cir.vector<8 x !s8i>, !cir.vector<8 x !s8i>) -> !cir.vector<8 x !s16i> + +// LLVM-SAME: <8 x i8> {{.*}} [[A:%.*]], <8 x i8> {{.*}} [[B:%.*]]) +// LLVM: [[VMULL_I:%.*]] = call <8 x i16> @llvm.aarch64.neon.pmull.v8i16(<8 x i8> [[A]], <8 x i8> [[B]]) +// LLVM-NEXT: ret <8 x i16> [[VMULL_I]] + return vmull_p8(a, b); +} + +// LLVM-LABEL: @test_vmull_high_p8( +// CIR-LABEL: @vmull_high_p8( +poly16x8_t test_vmull_high_p8(poly8x16_t a, poly8x16_t b) { +// CIR: [[HIGH_A:%.*]] = cir.call @vget_high_p8 +// CIR: [[HIGH_B:%.*]] = cir.call @vget_high_p8 +// CIR: {{%.*}} = cir.call @vmull_p8([[HIGH_A]], [[HIGH_B]]) + +// LLVM-SAME: <16 x i8> {{.*}} [[A:%.*]], <16 x i8> {{.*}} [[B:%.*]]) +// LLVM: [[SHUFFLE_I5:%.*]] = shufflevector <16 x i8> [[A]], <16 x i8> [[A]], <8 x i32> +// LLVM-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <16 x i8> [[B]], <16 x i8> [[B]], <8 x i32> +// LLVM-NEXT: [[VMULL_I_I:%.*]] = call <8 x i16> @llvm.aarch64.neon.pmull.v8i16(<8 x i8> [[SHUFFLE_I5]], <8 x i8> [[SHUFFLE_I]]) +// LLVM-NEXT: ret <8 x i16> [[VMULL_I_I]] + return vmull_high_p8(a, b); +}