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[Tablegen] Patch RegUnitIntervals Initialization (#181173)

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There were a few places it was missing some code-generation to properly
initialize it if enabled, and also it was missing the sentinel value.
This commit is contained in:
Ryan Mitchell 2026-02-18 03:09:48 -08:00 committed by GitHub
parent a13e04a694
commit 10ccf11ebb
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GPG Key ID: B5690EEEBB952194
2 changed files with 16 additions and 2 deletions
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3
llvm/test/TableGen/regunit-intervals.td
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@ -32,6 +32,9 @@ let Namespace = "Test" in {
}
// CHECK: extern const unsigned TestTargetRegUnitIntervals[][2] = {
// Sentinel
// CHECK-NEXT: { 0, 0 },
// Real values
// CHECK-NEXT: { 0, 1 },
// CHECK-NEXT: { 1, 2 },
// CHECK-NEXT: { 2, 3 },

15
llvm/utils/TableGen/RegisterInfoEmitter.cpp
View File

@ -1036,6 +1036,8 @@ void RegisterInfoEmitter::runMCDesc(raw_ostream &OS, raw_ostream &MainOS,
if (Target.getRegistersAreIntervals()) {
OS << "extern const unsigned " << TargetName
<< "RegUnitIntervals[][2] = {\n";
// Add entry for NoRegister
OS << " { 0, 0 },\n";
for (const CodeGenRegister &Reg : Regs) {
const auto &Units = Reg.getNativeRegUnits();
if (Units.empty()) {
@ -1138,7 +1140,10 @@ void RegisterInfoEmitter::runMCDesc(raw_ostream &OS, raw_ostream &MainOS,
<< TargetName << "LaneMaskLists, " << TargetName << "RegStrings, "
<< TargetName << "RegClassStrings, " << TargetName << "SubRegIdxLists, "
<< (llvm::size(SubRegIndices) + 1) << ",\n"
<< TargetName << "RegEncodingTable);\n\n";
<< TargetName << "RegEncodingTable, "
<< (Target.getRegistersAreIntervals() ? TargetName + "RegUnitIntervals"
: "nullptr")
<< ");\n\n";
EmitRegMapping(OS, Regs, false);
@ -1664,6 +1669,8 @@ void RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, raw_ostream &MainOS,
OS << "extern const MCPhysReg " << TargetName << "RegUnitRoots[][2];\n";
OS << "extern const uint16_t " << TargetName << "SubRegIdxLists[];\n";
OS << "extern const uint16_t " << TargetName << "RegEncodingTable[];\n";
if (Target.getRegistersAreIntervals())
OS << "extern const unsigned " << TargetName << "RegUnitIntervals[][2];\n";
EmitRegMappingTables(OS, Regs, true);
@ -1689,7 +1696,11 @@ void RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, raw_ostream &MainOS,
<< " " << TargetName << "RegClassStrings,\n"
<< " " << TargetName << "SubRegIdxLists,\n"
<< " " << SubRegIndicesSize + 1 << ",\n"
<< " " << TargetName << "RegEncodingTable);\n\n";
<< " " << TargetName << "RegEncodingTable,\n"
<< " "
<< (Target.getRegistersAreIntervals() ? TargetName + "RegUnitIntervals"
: "nullptr")
<< ");\n\n";
EmitRegMapping(OS, Regs, true);