[SLP] Fix PR35628: Count external uses on extra reduction arguments.
Summary: If the vectorized value is marked as extra reduction argument, its users are not considered as external users. Patch fixes this. Reviewers: mkuper, hfinkel, RKSimon, spatel Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D41786 llvm-svn: 321993
This commit is contained in:
Alexey Bataev
parent
5110d4f5c0
commit
118a0a2c38
@ -1347,7 +1347,6 @@ void BoUpSLP::buildTree(ArrayRef<Value *> Roots,
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DEBUG(dbgs() << "SLP: Need to extract: Extra arg from lane " <<
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Lane << " from " << *Scalar << ".\n");
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ExternalUses.emplace_back(Scalar, nullptr, Lane);
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continue;
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}
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for (User *U : Scalar->users()) {
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DEBUG(dbgs() << "SLP: Checking user:" << *U << ".\n");
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74
llvm/test/Transforms/SLPVectorizer/X86/PR35628_1.ll
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74
llvm/test/Transforms/SLPVectorizer/X86/PR35628_1.ll
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@ -0,0 +1,74 @@
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt -slp-vectorizer -slp-vectorize-hor -slp-vectorize-hor-store -S < %s -mtriple=x86_64-unknown-linux-gnu | FileCheck %s
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target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128-ni:1"
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define void @mainTest(i32* %ptr) #0 {
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; CHECK-LABEL: @mainTest(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32* [[PTR:%.*]], null
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; CHECK-NEXT: br i1 [[CMP]], label [[LOOP:%.*]], label [[BAIL_OUT:%.*]]
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; CHECK: loop:
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; CHECK-NEXT: [[DUMMY_PHI:%.*]] = phi i32 [ 1, [[ENTRY:%.*]] ], [ [[OP_EXTRA5:%.*]], [[LOOP]] ]
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; CHECK-NEXT: [[TMP0:%.*]] = getelementptr inbounds i32, i32* [[PTR]], i64 1
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; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, i32* [[PTR]], i64 2
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; CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, i32* [[PTR]], i64 3
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; CHECK-NEXT: [[TMP3:%.*]] = bitcast i32* [[PTR]] to <4 x i32>*
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; CHECK-NEXT: [[TMP4:%.*]] = load <4 x i32>, <4 x i32>* [[TMP3]], align 4
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; CHECK-NEXT: [[TMP5:%.*]] = extractelement <4 x i32> [[TMP4]], i32 3
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; CHECK-NEXT: [[TMP6:%.*]] = extractelement <4 x i32> [[TMP4]], i32 2
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; CHECK-NEXT: [[TMP7:%.*]] = extractelement <4 x i32> [[TMP4]], i32 1
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; CHECK-NEXT: [[TMP8:%.*]] = mul <4 x i32> [[TMP4]], [[TMP4]]
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; CHECK-NEXT: [[TMP9:%.*]] = add i32 1, undef
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; CHECK-NEXT: [[TMP10:%.*]] = add i32 [[TMP9]], undef
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; CHECK-NEXT: [[TMP11:%.*]] = add i32 [[TMP10]], undef
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; CHECK-NEXT: [[TMP12:%.*]] = add i32 [[TMP11]], undef
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; CHECK-NEXT: [[TMP13:%.*]] = add i32 [[TMP12]], undef
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; CHECK-NEXT: [[TMP14:%.*]] = sext i32 [[TMP6]] to i64
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; CHECK-NEXT: [[TMP15:%.*]] = add i32 [[TMP13]], undef
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; CHECK-NEXT: [[RDX_SHUF:%.*]] = shufflevector <4 x i32> [[TMP8]], <4 x i32> undef, <4 x i32> <i32 2, i32 3, i32 undef, i32 undef>
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; CHECK-NEXT: [[BIN_RDX:%.*]] = add <4 x i32> [[TMP8]], [[RDX_SHUF]]
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; CHECK-NEXT: [[RDX_SHUF1:%.*]] = shufflevector <4 x i32> [[BIN_RDX]], <4 x i32> undef, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
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; CHECK-NEXT: [[BIN_RDX2:%.*]] = add <4 x i32> [[BIN_RDX]], [[RDX_SHUF1]]
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; CHECK-NEXT: [[TMP16:%.*]] = extractelement <4 x i32> [[BIN_RDX2]], i32 0
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; CHECK-NEXT: [[OP_EXTRA:%.*]] = add i32 [[TMP16]], 1
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; CHECK-NEXT: [[OP_EXTRA3:%.*]] = add i32 [[OP_EXTRA]], [[TMP7]]
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; CHECK-NEXT: [[OP_EXTRA4:%.*]] = add i32 [[OP_EXTRA3]], [[TMP6]]
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; CHECK-NEXT: [[OP_EXTRA5]] = add i32 [[OP_EXTRA4]], [[TMP5]]
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; CHECK-NEXT: [[TMP17:%.*]] = add i32 [[TMP15]], undef
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; CHECK-NEXT: br label [[LOOP]]
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; CHECK: bail_out:
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; CHECK-NEXT: ret void
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;
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entry:
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%cmp = icmp eq i32* %ptr, null
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br i1 %cmp, label %loop, label %bail_out
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loop:
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%dummy_phi = phi i32 [ 1, %entry ], [ %18, %loop ]
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%0 = load i32, i32 * %ptr , align 4
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%1 = mul i32 %0, %0
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%2 = add i32 1, %1
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%3 = getelementptr inbounds i32, i32 * %ptr, i64 1
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%4 = load i32, i32 * %3 , align 4
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%5 = mul i32 %4, %4
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%6 = add i32 %2, %4
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%7 = add i32 %6, %5
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%8 = getelementptr inbounds i32, i32 *%ptr, i64 2
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%9 = load i32, i32 * %8 , align 4
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%10 = mul i32 %9, %9
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%11 = add i32 %7, %9
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%12 = add i32 %11, %10
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%13 = sext i32 %9 to i64
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%14 = getelementptr inbounds i32, i32 *%ptr, i64 3
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%15 = load i32, i32 * %14 , align 4
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%16 = mul i32 %15, %15
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%17 = add i32 %12, %15
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%18 = add i32 %17, %16
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br label %loop
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bail_out:
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ret void
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}
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attributes #0 = { "target-cpu"="westmere" }
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64
llvm/test/Transforms/SLPVectorizer/X86/PR35628_2.ll
Normal file
64
llvm/test/Transforms/SLPVectorizer/X86/PR35628_2.ll
Normal file
@ -0,0 +1,64 @@
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt -slp-vectorizer -slp-vectorize-hor -slp-vectorize-hor-store -S < %s -mtriple=x86_64-unknown-linux-gnu -mcpu=haswell | FileCheck %s
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target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128-ni:1"
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define void @test() #0 {
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; CHECK-LABEL: @test(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br label [[LOOP:%.*]]
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; CHECK: loop:
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; CHECK-NEXT: [[DUMMY_PHI:%.*]] = phi i64 [ 1, [[ENTRY:%.*]] ], [ [[OP_EXTRA3:%.*]], [[LOOP]] ]
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; CHECK-NEXT: [[TMP0:%.*]] = phi i64 [ 2, [[ENTRY]] ], [ [[TMP6:%.*]], [[LOOP]] ]
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; CHECK-NEXT: [[DUMMY_ADD:%.*]] = add i16 0, 0
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; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i64> undef, i64 [[TMP0]], i32 0
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; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i64> [[TMP1]], i64 [[TMP0]], i32 1
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; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i64> [[TMP2]], i64 [[TMP0]], i32 2
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; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x i64> [[TMP3]], i64 [[TMP0]], i32 3
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; CHECK-NEXT: [[TMP5:%.*]] = add <4 x i64> <i64 3, i64 2, i64 1, i64 0>, [[TMP4]]
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; CHECK-NEXT: [[TMP6]] = extractelement <4 x i64> [[TMP5]], i32 3
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; CHECK-NEXT: [[TMP7:%.*]] = extractelement <4 x i64> [[TMP5]], i32 0
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; CHECK-NEXT: [[DUMMY_SHL:%.*]] = shl i64 [[TMP7]], 32
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; CHECK-NEXT: [[TMP8:%.*]] = add <4 x i64> <i64 1, i64 1, i64 1, i64 1>, [[TMP5]]
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; CHECK-NEXT: [[TMP9:%.*]] = ashr exact <4 x i64> [[TMP8]], <i64 32, i64 32, i64 32, i64 32>
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; CHECK-NEXT: [[SUM1:%.*]] = add i64 undef, undef
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; CHECK-NEXT: [[SUM2:%.*]] = add i64 [[SUM1]], undef
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; CHECK-NEXT: [[ZSUM:%.*]] = add i64 [[SUM2]], 0
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; CHECK-NEXT: [[JOIN:%.*]] = add i64 undef, [[ZSUM]]
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; CHECK-NEXT: [[RDX_SHUF:%.*]] = shufflevector <4 x i64> [[TMP9]], <4 x i64> undef, <4 x i32> <i32 2, i32 3, i32 undef, i32 undef>
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; CHECK-NEXT: [[BIN_RDX:%.*]] = add <4 x i64> [[TMP9]], [[RDX_SHUF]]
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; CHECK-NEXT: [[RDX_SHUF1:%.*]] = shufflevector <4 x i64> [[BIN_RDX]], <4 x i64> undef, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
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; CHECK-NEXT: [[BIN_RDX2:%.*]] = add <4 x i64> [[BIN_RDX]], [[RDX_SHUF1]]
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; CHECK-NEXT: [[TMP10:%.*]] = extractelement <4 x i64> [[BIN_RDX2]], i32 0
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; CHECK-NEXT: [[OP_EXTRA:%.*]] = add i64 [[TMP10]], 0
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; CHECK-NEXT: [[OP_EXTRA3]] = add i64 [[OP_EXTRA]], [[TMP6]]
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; CHECK-NEXT: [[LAST:%.*]] = add i64 [[JOIN]], undef
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; CHECK-NEXT: br label [[LOOP]]
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;
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entry:
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br label %loop
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loop:
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%dummy_phi = phi i64 [ 1, %entry ], [ %last, %loop ]
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%0 = phi i64 [ 2, %entry ], [ %fork, %loop ]
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%inc1 = add i64 %0, 1
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%inc2 = add i64 %0, 2
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%inc11 = add i64 1, %inc1
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%exact1 = ashr exact i64 %inc11, 32
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%inc3 = add i64 %0, 3
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%dummy_add = add i16 0, 0
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%inc12 = add i64 1, %inc2
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%exact2 = ashr exact i64 %inc12, 32
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%dummy_shl = shl i64 %inc3, 32
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%inc13 = add i64 1, %inc3
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%exact3 = ashr exact i64 %inc13, 32
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%fork = add i64 %0, 0
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%sum1 = add i64 %exact3, %exact2
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%sum2 = add i64 %sum1, %exact1
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%zsum = add i64 %sum2, 0
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%sext22 = add i64 1, %fork
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%exact4 = ashr exact i64 %sext22, 32
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%join = add i64 %fork, %zsum
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%last = add i64 %join, %exact4
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br label %loop
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}
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