[RISCV] Merge RISCVMCInstLower.cpp into RISCVAsmPrinter.cpp.
The separation here doesn't make much sense. I think it's a leftover from the creation of the MC layer that has been replicated to new targets. By merging them we can avoid passing the AsmPrinter to the MCInstLowering functions. We can make them member functions instead. I think we can still do more integration of lowerSymbolOperand and lowerRISCVVMachineInstrToMCInst, but I wanted to get feedback on the direction first. Reviewed By: asb, barannikov88 Differential Revision: https://reviews.llvm.org/D152311
This commit is contained in:
Craig Topper
parent
80fe3168b5
commit
11e5a0d290
@ -32,7 +32,6 @@ add_llvm_target(RISCVCodeGen
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RISCVISelLowering.cpp
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RISCVMachineFunctionInfo.cpp
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RISCVMacroFusion.cpp
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RISCVMCInstLower.cpp
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RISCVMergeBaseOffset.cpp
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RISCVOptWInstrs.cpp
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RISCVRedundantCopyElimination.cpp
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@ -33,11 +33,6 @@ class RISCVTargetMachine;
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FunctionPass *createRISCVCodeGenPreparePass();
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void initializeRISCVCodeGenPreparePass(PassRegistry &);
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bool lowerRISCVMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI,
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AsmPrinter &AP);
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bool lowerRISCVMachineOperandToMCOperand(const MachineOperand &MO,
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MCOperand &MCOp, const AsmPrinter &AP);
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FunctionPass *createRISCVISelDag(RISCVTargetMachine &TM,
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CodeGenOpt::Level OptLevel);
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@ -74,9 +74,7 @@ public:
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void EmitHwasanMemaccessSymbols(Module &M);
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// Wrapper needed for tblgenned pseudo lowering.
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bool lowerOperand(const MachineOperand &MO, MCOperand &MCOp) const {
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return lowerRISCVMachineOperandToMCOperand(MO, MCOp, *this);
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}
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bool lowerOperand(const MachineOperand &MO, MCOperand &MCOp) const;
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void emitStartOfAsmFile(Module &M) override;
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void emitEndOfAsmFile(Module &M) override;
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@ -87,6 +85,8 @@ private:
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void emitAttributes();
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void emitNTLHint(const MachineInstr *MI);
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bool lowerToMCInst(const MachineInstr *MI, MCInst &OutMI);
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};
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}
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@ -156,9 +156,9 @@ void RISCVAsmPrinter::emitInstruction(const MachineInstr *MI) {
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return;
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}
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MCInst TmpInst;
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if (!lowerRISCVMachineInstrToMCInst(MI, TmpInst, *this))
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EmitToStreamer(*OutStreamer, TmpInst);
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MCInst OutInst;
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if (!lowerToMCInst(MI, OutInst))
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EmitToStreamer(*OutStreamer, OutInst);
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}
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bool RISCVAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
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@ -510,3 +510,233 @@ void RISCVAsmPrinter::EmitHwasanMemaccessSymbols(Module &M) {
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MCSTI);
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}
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}
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static MCOperand lowerSymbolOperand(const MachineOperand &MO, MCSymbol *Sym,
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const AsmPrinter &AP) {
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MCContext &Ctx = AP.OutContext;
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RISCVMCExpr::VariantKind Kind;
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switch (MO.getTargetFlags()) {
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default:
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llvm_unreachable("Unknown target flag on GV operand");
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case RISCVII::MO_None:
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Kind = RISCVMCExpr::VK_RISCV_None;
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break;
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case RISCVII::MO_CALL:
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Kind = RISCVMCExpr::VK_RISCV_CALL;
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break;
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case RISCVII::MO_PLT:
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Kind = RISCVMCExpr::VK_RISCV_CALL_PLT;
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break;
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case RISCVII::MO_LO:
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Kind = RISCVMCExpr::VK_RISCV_LO;
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break;
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case RISCVII::MO_HI:
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Kind = RISCVMCExpr::VK_RISCV_HI;
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break;
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case RISCVII::MO_PCREL_LO:
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Kind = RISCVMCExpr::VK_RISCV_PCREL_LO;
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break;
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case RISCVII::MO_PCREL_HI:
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Kind = RISCVMCExpr::VK_RISCV_PCREL_HI;
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break;
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case RISCVII::MO_GOT_HI:
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Kind = RISCVMCExpr::VK_RISCV_GOT_HI;
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break;
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case RISCVII::MO_TPREL_LO:
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Kind = RISCVMCExpr::VK_RISCV_TPREL_LO;
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break;
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case RISCVII::MO_TPREL_HI:
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Kind = RISCVMCExpr::VK_RISCV_TPREL_HI;
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break;
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case RISCVII::MO_TPREL_ADD:
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Kind = RISCVMCExpr::VK_RISCV_TPREL_ADD;
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break;
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case RISCVII::MO_TLS_GOT_HI:
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Kind = RISCVMCExpr::VK_RISCV_TLS_GOT_HI;
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break;
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case RISCVII::MO_TLS_GD_HI:
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Kind = RISCVMCExpr::VK_RISCV_TLS_GD_HI;
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break;
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}
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const MCExpr *ME =
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MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_None, Ctx);
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if (!MO.isJTI() && !MO.isMBB() && MO.getOffset())
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ME = MCBinaryExpr::createAdd(
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ME, MCConstantExpr::create(MO.getOffset(), Ctx), Ctx);
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if (Kind != RISCVMCExpr::VK_RISCV_None)
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ME = RISCVMCExpr::create(ME, Kind, Ctx);
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return MCOperand::createExpr(ME);
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}
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bool RISCVAsmPrinter::lowerOperand(const MachineOperand &MO,
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MCOperand &MCOp) const {
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switch (MO.getType()) {
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default:
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report_fatal_error("lowerOperand: unknown operand type");
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case MachineOperand::MO_Register:
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// Ignore all implicit register operands.
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if (MO.isImplicit())
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return false;
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MCOp = MCOperand::createReg(MO.getReg());
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break;
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case MachineOperand::MO_RegisterMask:
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// Regmasks are like implicit defs.
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return false;
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case MachineOperand::MO_Immediate:
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MCOp = MCOperand::createImm(MO.getImm());
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break;
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case MachineOperand::MO_MachineBasicBlock:
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MCOp = lowerSymbolOperand(MO, MO.getMBB()->getSymbol(), *this);
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break;
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case MachineOperand::MO_GlobalAddress:
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MCOp = lowerSymbolOperand(MO, getSymbolPreferLocal(*MO.getGlobal()), *this);
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break;
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case MachineOperand::MO_BlockAddress:
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MCOp = lowerSymbolOperand(MO, GetBlockAddressSymbol(MO.getBlockAddress()),
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*this);
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break;
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case MachineOperand::MO_ExternalSymbol:
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MCOp = lowerSymbolOperand(MO, GetExternalSymbolSymbol(MO.getSymbolName()),
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*this);
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break;
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case MachineOperand::MO_ConstantPoolIndex:
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MCOp = lowerSymbolOperand(MO, GetCPISymbol(MO.getIndex()), *this);
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break;
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case MachineOperand::MO_JumpTableIndex:
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MCOp = lowerSymbolOperand(MO, GetJTISymbol(MO.getIndex()), *this);
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break;
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case MachineOperand::MO_MCSymbol:
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MCOp = lowerSymbolOperand(MO, MO.getMCSymbol(), *this);
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break;
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}
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return true;
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}
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static bool lowerRISCVVMachineInstrToMCInst(const MachineInstr *MI,
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MCInst &OutMI) {
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const RISCVVPseudosTable::PseudoInfo *RVV =
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RISCVVPseudosTable::getPseudoInfo(MI->getOpcode());
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if (!RVV)
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return false;
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OutMI.setOpcode(RVV->BaseInstr);
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const MachineBasicBlock *MBB = MI->getParent();
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assert(MBB && "MI expected to be in a basic block");
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const MachineFunction *MF = MBB->getParent();
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assert(MF && "MBB expected to be in a machine function");
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const TargetRegisterInfo *TRI =
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MF->getSubtarget<RISCVSubtarget>().getRegisterInfo();
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assert(TRI && "TargetRegisterInfo expected");
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uint64_t TSFlags = MI->getDesc().TSFlags;
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unsigned NumOps = MI->getNumExplicitOperands();
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// Skip policy, VL and SEW operands which are the last operands if present.
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if (RISCVII::hasVecPolicyOp(TSFlags))
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--NumOps;
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if (RISCVII::hasVLOp(TSFlags))
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--NumOps;
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if (RISCVII::hasSEWOp(TSFlags))
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--NumOps;
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bool hasVLOutput = RISCV::isFaultFirstLoad(*MI);
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for (unsigned OpNo = 0; OpNo != NumOps; ++OpNo) {
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const MachineOperand &MO = MI->getOperand(OpNo);
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// Skip vl ouput. It should be the second output.
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if (hasVLOutput && OpNo == 1)
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continue;
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// Skip merge op. It should be the first operand after the result.
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if (RISCVII::hasMergeOp(TSFlags) && OpNo == 1U + hasVLOutput) {
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assert(MI->getNumExplicitDefs() == 1U + hasVLOutput);
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continue;
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}
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MCOperand MCOp;
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switch (MO.getType()) {
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default:
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llvm_unreachable("Unknown operand type");
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case MachineOperand::MO_Register: {
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Register Reg = MO.getReg();
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if (RISCV::VRM2RegClass.contains(Reg) ||
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RISCV::VRM4RegClass.contains(Reg) ||
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RISCV::VRM8RegClass.contains(Reg)) {
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Reg = TRI->getSubReg(Reg, RISCV::sub_vrm1_0);
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assert(Reg && "Subregister does not exist");
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} else if (RISCV::FPR16RegClass.contains(Reg)) {
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Reg =
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TRI->getMatchingSuperReg(Reg, RISCV::sub_16, &RISCV::FPR32RegClass);
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assert(Reg && "Subregister does not exist");
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} else if (RISCV::FPR64RegClass.contains(Reg)) {
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Reg = TRI->getSubReg(Reg, RISCV::sub_32);
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assert(Reg && "Superregister does not exist");
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} else if (RISCV::VRN2M1RegClass.contains(Reg) ||
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RISCV::VRN2M2RegClass.contains(Reg) ||
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RISCV::VRN2M4RegClass.contains(Reg) ||
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RISCV::VRN3M1RegClass.contains(Reg) ||
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RISCV::VRN3M2RegClass.contains(Reg) ||
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RISCV::VRN4M1RegClass.contains(Reg) ||
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RISCV::VRN4M2RegClass.contains(Reg) ||
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RISCV::VRN5M1RegClass.contains(Reg) ||
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RISCV::VRN6M1RegClass.contains(Reg) ||
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RISCV::VRN7M1RegClass.contains(Reg) ||
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RISCV::VRN8M1RegClass.contains(Reg)) {
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Reg = TRI->getSubReg(Reg, RISCV::sub_vrm1_0);
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assert(Reg && "Subregister does not exist");
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}
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MCOp = MCOperand::createReg(Reg);
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break;
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}
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case MachineOperand::MO_Immediate:
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MCOp = MCOperand::createImm(MO.getImm());
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break;
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}
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OutMI.addOperand(MCOp);
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}
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// Unmasked pseudo instructions need to append dummy mask operand to
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// V instructions. All V instructions are modeled as the masked version.
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if (RISCVII::hasDummyMaskOp(TSFlags))
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OutMI.addOperand(MCOperand::createReg(RISCV::NoRegister));
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return true;
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}
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bool RISCVAsmPrinter::lowerToMCInst(const MachineInstr *MI, MCInst &OutMI) {
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if (lowerRISCVVMachineInstrToMCInst(MI, OutMI))
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return false;
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OutMI.setOpcode(MI->getOpcode());
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for (const MachineOperand &MO : MI->operands()) {
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MCOperand MCOp;
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if (lowerOperand(MO, MCOp))
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OutMI.addOperand(MCOp);
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}
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switch (OutMI.getOpcode()) {
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case TargetOpcode::PATCHABLE_FUNCTION_ENTER: {
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const Function &F = MI->getParent()->getParent()->getFunction();
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if (F.hasFnAttribute("patchable-function-entry")) {
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unsigned Num;
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if (F.getFnAttribute("patchable-function-entry")
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.getValueAsString()
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.getAsInteger(10, Num))
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return false;
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emitNops(Num);
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return true;
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}
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break;
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}
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}
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return false;
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}
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@ -1,258 +0,0 @@
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//===-- RISCVMCInstLower.cpp - Convert RISC-V MachineInstr to an MCInst -----=//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains code to lower RISC-V MachineInstrs to their corresponding
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// MCInst records.
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//
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//===----------------------------------------------------------------------===//
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#include "RISCV.h"
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#include "RISCVSubtarget.h"
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#include "MCTargetDesc/RISCVMCExpr.h"
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#include "llvm/CodeGen/AsmPrinter.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/MC/MCAsmInfo.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/MC/MCExpr.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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static MCOperand lowerSymbolOperand(const MachineOperand &MO, MCSymbol *Sym,
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const AsmPrinter &AP) {
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MCContext &Ctx = AP.OutContext;
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RISCVMCExpr::VariantKind Kind;
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switch (MO.getTargetFlags()) {
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default:
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llvm_unreachable("Unknown target flag on GV operand");
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case RISCVII::MO_None:
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Kind = RISCVMCExpr::VK_RISCV_None;
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break;
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case RISCVII::MO_CALL:
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Kind = RISCVMCExpr::VK_RISCV_CALL;
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break;
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case RISCVII::MO_PLT:
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Kind = RISCVMCExpr::VK_RISCV_CALL_PLT;
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break;
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case RISCVII::MO_LO:
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Kind = RISCVMCExpr::VK_RISCV_LO;
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break;
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case RISCVII::MO_HI:
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Kind = RISCVMCExpr::VK_RISCV_HI;
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break;
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case RISCVII::MO_PCREL_LO:
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Kind = RISCVMCExpr::VK_RISCV_PCREL_LO;
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break;
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case RISCVII::MO_PCREL_HI:
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Kind = RISCVMCExpr::VK_RISCV_PCREL_HI;
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break;
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case RISCVII::MO_GOT_HI:
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Kind = RISCVMCExpr::VK_RISCV_GOT_HI;
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break;
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case RISCVII::MO_TPREL_LO:
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Kind = RISCVMCExpr::VK_RISCV_TPREL_LO;
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break;
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case RISCVII::MO_TPREL_HI:
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Kind = RISCVMCExpr::VK_RISCV_TPREL_HI;
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break;
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case RISCVII::MO_TPREL_ADD:
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Kind = RISCVMCExpr::VK_RISCV_TPREL_ADD;
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break;
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case RISCVII::MO_TLS_GOT_HI:
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Kind = RISCVMCExpr::VK_RISCV_TLS_GOT_HI;
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break;
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case RISCVII::MO_TLS_GD_HI:
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Kind = RISCVMCExpr::VK_RISCV_TLS_GD_HI;
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break;
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}
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const MCExpr *ME =
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MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_None, Ctx);
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if (!MO.isJTI() && !MO.isMBB() && MO.getOffset())
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ME = MCBinaryExpr::createAdd(
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ME, MCConstantExpr::create(MO.getOffset(), Ctx), Ctx);
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if (Kind != RISCVMCExpr::VK_RISCV_None)
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ME = RISCVMCExpr::create(ME, Kind, Ctx);
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return MCOperand::createExpr(ME);
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}
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bool llvm::lowerRISCVMachineOperandToMCOperand(const MachineOperand &MO,
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MCOperand &MCOp,
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const AsmPrinter &AP) {
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switch (MO.getType()) {
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default:
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report_fatal_error("LowerRISCVMachineInstrToMCInst: unknown operand type");
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case MachineOperand::MO_Register:
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// Ignore all implicit register operands.
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if (MO.isImplicit())
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return false;
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MCOp = MCOperand::createReg(MO.getReg());
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break;
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case MachineOperand::MO_RegisterMask:
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// Regmasks are like implicit defs.
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return false;
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case MachineOperand::MO_Immediate:
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MCOp = MCOperand::createImm(MO.getImm());
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break;
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case MachineOperand::MO_MachineBasicBlock:
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MCOp = lowerSymbolOperand(MO, MO.getMBB()->getSymbol(), AP);
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break;
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case MachineOperand::MO_GlobalAddress:
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MCOp = lowerSymbolOperand(MO, AP.getSymbolPreferLocal(*MO.getGlobal()), AP);
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break;
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case MachineOperand::MO_BlockAddress:
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MCOp = lowerSymbolOperand(
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MO, AP.GetBlockAddressSymbol(MO.getBlockAddress()), AP);
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break;
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case MachineOperand::MO_ExternalSymbol:
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MCOp = lowerSymbolOperand(
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MO, AP.GetExternalSymbolSymbol(MO.getSymbolName()), AP);
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break;
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case MachineOperand::MO_ConstantPoolIndex:
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MCOp = lowerSymbolOperand(MO, AP.GetCPISymbol(MO.getIndex()), AP);
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break;
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case MachineOperand::MO_JumpTableIndex:
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MCOp = lowerSymbolOperand(MO, AP.GetJTISymbol(MO.getIndex()), AP);
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break;
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case MachineOperand::MO_MCSymbol:
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MCOp = lowerSymbolOperand(MO, MO.getMCSymbol(), AP);
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break;
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}
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return true;
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}
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static bool lowerRISCVVMachineInstrToMCInst(const MachineInstr *MI,
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MCInst &OutMI) {
|
||||
const RISCVVPseudosTable::PseudoInfo *RVV =
|
||||
RISCVVPseudosTable::getPseudoInfo(MI->getOpcode());
|
||||
if (!RVV)
|
||||
return false;
|
||||
|
||||
OutMI.setOpcode(RVV->BaseInstr);
|
||||
|
||||
const MachineBasicBlock *MBB = MI->getParent();
|
||||
assert(MBB && "MI expected to be in a basic block");
|
||||
const MachineFunction *MF = MBB->getParent();
|
||||
assert(MF && "MBB expected to be in a machine function");
|
||||
|
||||
const TargetRegisterInfo *TRI =
|
||||
MF->getSubtarget<RISCVSubtarget>().getRegisterInfo();
|
||||
|
||||
assert(TRI && "TargetRegisterInfo expected");
|
||||
|
||||
uint64_t TSFlags = MI->getDesc().TSFlags;
|
||||
unsigned NumOps = MI->getNumExplicitOperands();
|
||||
|
||||
// Skip policy, VL and SEW operands which are the last operands if present.
|
||||
if (RISCVII::hasVecPolicyOp(TSFlags))
|
||||
--NumOps;
|
||||
if (RISCVII::hasVLOp(TSFlags))
|
||||
--NumOps;
|
||||
if (RISCVII::hasSEWOp(TSFlags))
|
||||
--NumOps;
|
||||
|
||||
bool hasVLOutput = RISCV::isFaultFirstLoad(*MI);
|
||||
for (unsigned OpNo = 0; OpNo != NumOps; ++OpNo) {
|
||||
const MachineOperand &MO = MI->getOperand(OpNo);
|
||||
// Skip vl ouput. It should be the second output.
|
||||
if (hasVLOutput && OpNo == 1)
|
||||
continue;
|
||||
|
||||
// Skip merge op. It should be the first operand after the result.
|
||||
if (RISCVII::hasMergeOp(TSFlags) && OpNo == 1U + hasVLOutput) {
|
||||
assert(MI->getNumExplicitDefs() == 1U + hasVLOutput);
|
||||
continue;
|
||||
}
|
||||
|
||||
MCOperand MCOp;
|
||||
switch (MO.getType()) {
|
||||
default:
|
||||
llvm_unreachable("Unknown operand type");
|
||||
case MachineOperand::MO_Register: {
|
||||
Register Reg = MO.getReg();
|
||||
|
||||
if (RISCV::VRM2RegClass.contains(Reg) ||
|
||||
RISCV::VRM4RegClass.contains(Reg) ||
|
||||
RISCV::VRM8RegClass.contains(Reg)) {
|
||||
Reg = TRI->getSubReg(Reg, RISCV::sub_vrm1_0);
|
||||
assert(Reg && "Subregister does not exist");
|
||||
} else if (RISCV::FPR16RegClass.contains(Reg)) {
|
||||
Reg = TRI->getMatchingSuperReg(Reg, RISCV::sub_16, &RISCV::FPR32RegClass);
|
||||
assert(Reg && "Subregister does not exist");
|
||||
} else if (RISCV::FPR64RegClass.contains(Reg)) {
|
||||
Reg = TRI->getSubReg(Reg, RISCV::sub_32);
|
||||
assert(Reg && "Superregister does not exist");
|
||||
} else if (RISCV::VRN2M1RegClass.contains(Reg) ||
|
||||
RISCV::VRN2M2RegClass.contains(Reg) ||
|
||||
RISCV::VRN2M4RegClass.contains(Reg) ||
|
||||
RISCV::VRN3M1RegClass.contains(Reg) ||
|
||||
RISCV::VRN3M2RegClass.contains(Reg) ||
|
||||
RISCV::VRN4M1RegClass.contains(Reg) ||
|
||||
RISCV::VRN4M2RegClass.contains(Reg) ||
|
||||
RISCV::VRN5M1RegClass.contains(Reg) ||
|
||||
RISCV::VRN6M1RegClass.contains(Reg) ||
|
||||
RISCV::VRN7M1RegClass.contains(Reg) ||
|
||||
RISCV::VRN8M1RegClass.contains(Reg)) {
|
||||
Reg = TRI->getSubReg(Reg, RISCV::sub_vrm1_0);
|
||||
assert(Reg && "Subregister does not exist");
|
||||
}
|
||||
|
||||
MCOp = MCOperand::createReg(Reg);
|
||||
break;
|
||||
}
|
||||
case MachineOperand::MO_Immediate:
|
||||
MCOp = MCOperand::createImm(MO.getImm());
|
||||
break;
|
||||
}
|
||||
OutMI.addOperand(MCOp);
|
||||
}
|
||||
|
||||
// Unmasked pseudo instructions need to append dummy mask operand to
|
||||
// V instructions. All V instructions are modeled as the masked version.
|
||||
if (RISCVII::hasDummyMaskOp(TSFlags))
|
||||
OutMI.addOperand(MCOperand::createReg(RISCV::NoRegister));
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
bool llvm::lowerRISCVMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI,
|
||||
AsmPrinter &AP) {
|
||||
if (lowerRISCVVMachineInstrToMCInst(MI, OutMI))
|
||||
return false;
|
||||
|
||||
OutMI.setOpcode(MI->getOpcode());
|
||||
|
||||
for (const MachineOperand &MO : MI->operands()) {
|
||||
MCOperand MCOp;
|
||||
if (lowerRISCVMachineOperandToMCOperand(MO, MCOp, AP))
|
||||
OutMI.addOperand(MCOp);
|
||||
}
|
||||
|
||||
switch (OutMI.getOpcode()) {
|
||||
case TargetOpcode::PATCHABLE_FUNCTION_ENTER: {
|
||||
const Function &F = MI->getParent()->getParent()->getFunction();
|
||||
if (F.hasFnAttribute("patchable-function-entry")) {
|
||||
unsigned Num;
|
||||
if (F.getFnAttribute("patchable-function-entry")
|
||||
.getValueAsString()
|
||||
.getAsInteger(10, Num))
|
||||
return false;
|
||||
AP.emitNops(Num);
|
||||
return true;
|
||||
}
|
||||
break;
|
||||
}
|
||||
}
|
||||
return false;
|
||||
}
|
||||
Loading…
x
Reference in New Issue
Block a user