[ELF][LoongArch] -r: Synthesize R_LARCH_ALIGN at input section start (#153935)
Similay to
94655dc8ae
The difference is that in LoongArch, the ALIGN is synthesized when the
alignment is >4, (instead of >=4), and the number of bytes inserted is
`sec->addralign - 4`.
This commit is contained in:
Zhaoxin Yang
GitHub
parent
6560adb584
commit
149d9a38e1
@ -39,6 +39,7 @@ public:
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void relocate(uint8_t *loc, const Relocation &rel,
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uint64_t val) const override;
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bool relaxOnce(int pass) const override;
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bool synthesizeAlign(uint64_t &dot, InputSection *sec) override;
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RelExpr adjustTlsExpr(RelType type, RelExpr expr) const override;
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void relocateAlloc(InputSectionBase &sec, uint8_t *buf) const override;
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void finalizeRelax(int passes) const override;
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@ -48,6 +49,19 @@ private:
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void tlsdescToLe(uint8_t *loc, const Relocation &rel, uint64_t val) const;
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bool tryGotToPCRel(uint8_t *loc, const Relocation &rHi20,
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const Relocation &rLo12, uint64_t secAddr) const;
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template <class ELFT, class RelTy>
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bool synthesizeAlignForInput(uint64_t &dot, InputSection *sec,
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Relocs<RelTy> rels);
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template <class ELFT, class RelTy>
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void finalizeSynthesizeAligns(uint64_t &dot, InputSection *sec,
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Relocs<RelTy> rels);
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template <class ELFT>
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bool synthesizeAlignAux(uint64_t &dot, InputSection *sec);
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// The following two variables are used by synthesized ALIGN relocations.
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InputSection *baseSec = nullptr;
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// r_offset and r_addend pairs.
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SmallVector<std::pair<uint64_t, uint64_t>, 0> synthesizedAligns;
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};
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} // end anonymous namespace
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@ -766,6 +780,117 @@ void LoongArch::relocate(uint8_t *loc, const Relocation &rel,
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}
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}
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// If the section alignment is > 4, advance `dot` to insert NOPs and synthesize
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// an ALIGN relocation. Otherwise, return false to use default handling.
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template <class ELFT, class RelTy>
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bool LoongArch::synthesizeAlignForInput(uint64_t &dot, InputSection *sec,
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Relocs<RelTy> rels) {
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if (!baseSec) {
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// Record the first input section with RELAX relocations. We will synthesize
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// ALIGN relocations here.
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for (auto rel : rels) {
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if (rel.getType(false) == R_LARCH_RELAX) {
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baseSec = sec;
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break;
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}
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}
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} else if (sec->addralign > 4) {
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// If the alignment is > 4 and the section does not start with an ALIGN
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// relocation, synthesize one.
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bool hasAlignRel = llvm::any_of(rels, [](const RelTy &rel) {
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return rel.r_offset == 0 && rel.getType(false) == R_LARCH_ALIGN;
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});
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if (!hasAlignRel) {
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synthesizedAligns.emplace_back(dot - baseSec->getVA(),
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sec->addralign - 4);
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dot += sec->addralign - 4;
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return true;
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}
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}
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return false;
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}
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// Finalize the relocation section by appending synthesized ALIGN relocations
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// after processing all input sections.
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template <class ELFT, class RelTy>
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void LoongArch::finalizeSynthesizeAligns(uint64_t &dot, InputSection *sec,
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Relocs<RelTy> rels) {
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auto *f = cast<ObjFile<ELFT>>(baseSec->file);
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auto shdr = f->template getELFShdrs<ELFT>()[baseSec->relSecIdx];
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// Create a copy of InputSection.
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sec = make<InputSection>(*f, shdr, baseSec->name);
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auto *baseRelSec = cast<InputSection>(f->getSections()[baseSec->relSecIdx]);
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*sec = *baseRelSec;
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baseSec = nullptr;
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// Allocate buffer for original and synthesized relocations in RELA format.
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// If CREL is used, OutputSection::finalizeNonAllocCrel will convert RELA to
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// CREL.
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auto newSize = rels.size() + synthesizedAligns.size();
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auto *relas = makeThreadLocalN<typename ELFT::Rela>(newSize);
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sec->size = newSize * sizeof(typename ELFT::Rela);
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sec->content_ = reinterpret_cast<uint8_t *>(relas);
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sec->type = SHT_RELA;
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// Copy original relocations to the new buffer, potentially converting CREL to
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// RELA.
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for (auto [i, r] : llvm::enumerate(rels)) {
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relas[i].r_offset = r.r_offset;
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relas[i].setSymbolAndType(r.getSymbol(0), r.getType(0), false);
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if constexpr (RelTy::HasAddend)
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relas[i].r_addend = r.r_addend;
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}
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// Append synthesized ALIGN relocations to the buffer.
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for (auto [i, r] : llvm::enumerate(synthesizedAligns)) {
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auto &rela = relas[rels.size() + i];
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rela.r_offset = r.first;
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rela.setSymbolAndType(0, R_LARCH_ALIGN, false);
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rela.r_addend = r.second;
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}
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synthesizedAligns.clear();
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// Replace the old relocation section with the new one in the output section.
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// addOrphanSections ensures that the output relocation section is processed
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// after osec.
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for (SectionCommand *cmd : sec->getParent()->commands) {
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auto *isd = dyn_cast<InputSectionDescription>(cmd);
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if (!isd)
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continue;
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for (auto *&isec : isd->sections)
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if (isec == baseRelSec)
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isec = sec;
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}
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}
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template <class ELFT>
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bool LoongArch::synthesizeAlignAux(uint64_t &dot, InputSection *sec) {
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bool ret = false;
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if (sec) {
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invokeOnRelocs(*sec, ret = synthesizeAlignForInput<ELFT>, dot, sec);
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} else if (baseSec) {
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invokeOnRelocs(*baseSec, finalizeSynthesizeAligns<ELFT>, dot, sec);
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}
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return ret;
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}
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// Without linker relaxation enabled for a particular relocatable file or
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// section, the assembler will not generate R_LARCH_ALIGN relocations for
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// alignment directives. This becomes problematic in a two-stage linking
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// process: ld -r a.o b.o -o ab.o; ld ab.o -o ab. This function synthesizes an
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// R_LARCH_ALIGN relocation at section start when needed.
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//
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// When called with an input section (`sec` is not null): If the section
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// alignment is > 4, advance `dot` to insert NOPs and synthesize an ALIGN
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// relocation.
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//
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// When called after all input sections are processed (`sec` is null): The
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// output relocation section is updated with all the newly synthesized ALIGN
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// relocations.
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bool LoongArch::synthesizeAlign(uint64_t &dot, InputSection *sec) {
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assert(ctx.arg.relocatable);
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if (ctx.arg.is64)
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return synthesizeAlignAux<ELF64LE>(dot, sec);
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return synthesizeAlignAux<ELF32LE>(dot, sec);
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}
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static bool relaxable(ArrayRef<Relocation> relocs, size_t i) {
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return i + 1 < relocs.size() && relocs[i + 1].type == R_LARCH_RELAX;
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}
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@ -1230,9 +1230,9 @@ bool LinkerScript::assignOffsets(OutputSection *sec) {
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if (sec->firstInOverlay)
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state->overlaySize = 0;
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bool synthesizeAlign = ctx.arg.relocatable && ctx.arg.relax &&
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(sec->flags & SHF_EXECINSTR) &&
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ctx.arg.emachine == EM_RISCV;
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bool synthesizeAlign =
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ctx.arg.relocatable && ctx.arg.relax && (sec->flags & SHF_EXECINSTR) &&
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(ctx.arg.emachine == EM_LOONGARCH || ctx.arg.emachine == EM_RISCV);
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// We visited SectionsCommands from processSectionCommands to
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// layout sections. Now, we visit SectionsCommands again to fix
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// section offsets.
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@ -899,6 +899,8 @@ std::array<uint8_t, 4> OutputSection::getFiller(Ctx &ctx) {
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return {1, 0, 1, 0};
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return {0x13, 0, 0, 0};
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}
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if (ctx.arg.relocatable && ctx.arg.emachine == EM_LOONGARCH)
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return {0, 0, 0x40, 0x03};
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return ctx.target->trapInstr;
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}
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147
lld/test/ELF/loongarch-relocatable-align.s
Normal file
147
lld/test/ELF/loongarch-relocatable-align.s
Normal file
@ -0,0 +1,147 @@
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# REQUIRES: loongarch
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## Test LA64.
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# RUN: rm -rf %t && split-file %s %t && cd %t
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# RUN: llvm-mc -filetype=obj -triple=loongarch64 -mattr=+relax a.s -o a.o
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# RUN: llvm-mc -filetype=obj -triple=loongarch64 -mattr=+relax --defsym ELF64=1 b.s -o b.o
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# RUN: llvm-mc -filetype=obj -triple=loongarch64 -mattr=+relax b1.s -o b1.o
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# RUN: llvm-mc -filetype=obj -triple=loongarch64 -mattr=+relax c.s -o c.o
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# RUN: llvm-mc -filetype=obj -triple=loongarch64 d.s -o d.o
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## No RELAX. Don't synthesize ALIGN.
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# RUN: ld.lld -r b.o d.o -o bd.ro
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# RUN: llvm-readelf -r bd.ro | FileCheck %s --check-prefix=NOREL
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# NOREL: no relocations
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# RUN: ld.lld -r b.o b.o a.o b.o b1.o c.o d.o -o out.ro
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# RUN: llvm-objdump -dr --no-show-raw-insn out.ro | FileCheck %s
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# RUN: llvm-readelf -r out.ro | FileCheck %s --check-prefix=CHECK-REL
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# CHECK: <b0>:
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# CHECK-NEXT: 0: addi.d $a0, $a1, 1
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# CHECK-NEXT: 4: nop
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# CHECK-EMPTY:
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# CHECK-NEXT: <b0>:
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# CHECK-NEXT: 8: addi.d $a0, $a1, 1
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# CHECK-EMPTY:
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# CHECK-NEXT: <_start>:
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# CHECK-NEXT: c: pcalau12i $a0, 0
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# CHECK-NEXT: 000000000000000c: R_LARCH_PCALA_HI20 .Ltext1_start
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# CHECK-NEXT: 000000000000000c: R_LARCH_RELAX *ABS*
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# CHECK-NEXT: 10: addi.d $a0, $a0, 0
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# CHECK-NEXT: 0000000000000010: R_LARCH_PCALA_LO12 .Ltext1_start
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# CHECK-NEXT: 0000000000000010: R_LARCH_RELAX *ABS*
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# CHECK-NEXT: 14: nop
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# CHECK-NEXT: 0000000000000014: R_LARCH_ALIGN *ABS*+0x4
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# CHECK-EMPTY:
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# CHECK-NEXT: <b0>:
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# CHECK-NEXT: 18: addi.d $a0, $a1, 1
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# CHECK-NEXT: 1c: nop
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# CHECK-NEXT: 20: nop
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# CHECK-NEXT: 0000000000000020: R_LARCH_ALIGN *ABS*+0x4
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# CHECK-NEXT: 24: nop
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# CHECK-EMPTY:
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# CHECK-NEXT: <b1>:
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# CHECK-NEXT: 28: addi.d $a0, $a1, 3
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# CHECK-EMPTY:
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# CHECK-NEXT: <c0>:
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# CHECK-NEXT: 2c: addi.d $a0, $a1, 4
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# CHECK-NEXT: 30: nop
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# CHECK-NEXT: 0000000000000030: R_LARCH_ALIGN *ABS*+0x4
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# CHECK-EMPTY:
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# CHECK-NEXT: <d0>:
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# CHECK-NEXT: 34: addi.d $a0, $a1, 5
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# CHECK-REL: Relocation section '.rela.text' at offset {{.*}} contains 7 entries:
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# CHECK-REL: Relocation section '.rela.text1' at offset {{.*}} contains 5 entries:
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## Test LA32.
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# RUN: llvm-mc -filetype=obj -triple=loongarch32 -mattr=+relax a.s -o a.32.o
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# RUN: llvm-mc -filetype=obj -triple=loongarch32 -mattr=+relax b.s -o b.32.o
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# RUN: ld.lld -r a.32.o b.32.o -o out.32.ro
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# RUN: ld.lld -Ttext=0x10000 out.32.ro -o out32
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# RUN: llvm-objdump -dr --no-show-raw-insn out32 | FileCheck %s --check-prefix=CHECK32
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# CHECK32: <_start>:
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# CHECK32-NEXT: 10000: pcaddi $a0, 4
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# CHECK32-NEXT: 10004: nop
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# CHECK32-EMPTY:
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# CHECK32-NEXT: <b0>:
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# CHECK32-NEXT: 10008: addi.w $a0, $a1, 1
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# CHECK32: <.Ltext1_start>:
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# CHECK32-NEXT: 10010: pcaddi $a1, 0
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# CHECK32-NEXT: 10014: nop
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# CHECK32-NEXT: 10018: addi.w $a0, $a1, 2
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## Test CREL.
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# RUN: llvm-mc -filetype=obj -triple=loongarch64 -mattr=+relax --crel a.s -o acrel.o
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# RUN: ld.lld -r acrel.o b.o -o out.crel.ro
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# RUN: llvm-objdump -dr --no-show-raw-insn out.crel.ro | FileCheck %s --check-prefix=CHECKC
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# CHECKC: <_start>:
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# CHECKC-NEXT: 0: pcalau12i $a0, 0
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# CHECKC-NEXT: 0000000000000000: R_LARCH_PCALA_HI20 .Ltext1_start
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# CHECKC-NEXT: 0000000000000000: R_LARCH_RELAX *ABS*
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# CHECKC-NEXT: 4: addi.d $a0, $a0, 0
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# CHECKC-NEXT: 0000000000000004: R_LARCH_PCALA_LO12 .Ltext1_start
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# CHECKC-NEXT: 0000000000000004: R_LARCH_RELAX *ABS*
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# CHECKC-NEXT: 8: nop
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# CHECKC-NEXT: 0000000000000008: R_LARCH_ALIGN *ABS*+0x4
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# CHECKC-EMPTY:
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# CHECKC-NEXT: <b0>:
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# CHECKC-NEXT: c: addi.d $a0, $a1, 1
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#--- a.s
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.globl _start
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_start:
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la.pcrel $a0, .Ltext1_start
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.section .text1,"ax"
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.Ltext1_start:
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la.pcrel $a1, .Ltext1_start
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#--- b.s
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.macro addi dst, src1, src2
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.ifdef ELF64
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addi.d \dst, \src1, \src2
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.else
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addi.w \dst, \src1, \src2
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.endif
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.endm
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## Needs synthesized ALIGN.
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.option push
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.option norelax
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.balign 8
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b0:
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addi $a0, $a1, 1
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.section .text1,"ax"
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.balign 8
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addi $a0, $a1, 2
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.option pop
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#--- b1.s
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# Starts with an ALIGN relocation, don't need synthesized ALIGN.
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.option push
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.option norelax
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.reloc ., R_LARCH_ALIGN, 4
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nop
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.balign 8
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b1:
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addi.d $a0, $a1, 3
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.option pop
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#--- c.s
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## Alignment == 4, don't need synthesized ALIGN.
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.balign 4
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c0:
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addi.d $a0, $a1, 4
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#--- d.s
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## Needs synthesized ALIGN.
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.balign 8
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d0:
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addi.d $a0, $a1, 5
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