[SPARC] Set how many bytes load from or store to stack slot (#182674)
Refer from: https://reviews.llvm.org/D44782 The testcase is copied from llvm/test/CodeGen/RISCV/stack-slot-coloring.mir.
This commit is contained in:
dianqk
GitHub
parent
8542514e5c
commit
15487238c4
@ -47,15 +47,31 @@ SparcInstrInfo::SparcInstrInfo(const SparcSubtarget &ST)
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/// not, return 0. This predicate must return 0 if the instruction has
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/// any side effects other than loading from the stack slot.
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Register SparcInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
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int &FrameIndex) const {
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if (MI.getOpcode() == SP::LDri || MI.getOpcode() == SP::LDXri ||
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MI.getOpcode() == SP::LDFri || MI.getOpcode() == SP::LDDFri ||
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MI.getOpcode() == SP::LDQFri) {
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if (MI.getOperand(1).isFI() && MI.getOperand(2).isImm() &&
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MI.getOperand(2).getImm() == 0) {
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FrameIndex = MI.getOperand(1).getIndex();
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return MI.getOperand(0).getReg();
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}
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int &FrameIndex,
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TypeSize &MemBytes) const {
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switch (MI.getOpcode()) {
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default:
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return 0;
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case SP::LDri:
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MemBytes = TypeSize::getFixed(4);
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break;
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case SP::LDXri:
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MemBytes = TypeSize::getFixed(8);
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break;
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case SP::LDFri:
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MemBytes = TypeSize::getFixed(4);
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break;
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case SP::LDDFri:
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MemBytes = TypeSize::getFixed(8);
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break;
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case SP::LDQFri:
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MemBytes = TypeSize::getFixed(16);
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break;
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}
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if (MI.getOperand(1).isFI() && MI.getOperand(2).isImm() &&
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MI.getOperand(2).getImm() == 0) {
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FrameIndex = MI.getOperand(1).getIndex();
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return MI.getOperand(0).getReg();
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}
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return 0;
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}
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@ -66,15 +82,31 @@ Register SparcInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
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/// not, return 0. This predicate must return 0 if the instruction has
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/// any side effects other than storing to the stack slot.
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Register SparcInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
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int &FrameIndex) const {
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if (MI.getOpcode() == SP::STri || MI.getOpcode() == SP::STXri ||
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MI.getOpcode() == SP::STFri || MI.getOpcode() == SP::STDFri ||
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MI.getOpcode() == SP::STQFri) {
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if (MI.getOperand(0).isFI() && MI.getOperand(1).isImm() &&
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MI.getOperand(1).getImm() == 0) {
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FrameIndex = MI.getOperand(0).getIndex();
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return MI.getOperand(2).getReg();
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}
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int &FrameIndex,
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TypeSize &MemBytes) const {
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switch (MI.getOpcode()) {
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default:
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return 0;
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case SP::STri:
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MemBytes = TypeSize::getFixed(4);
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break;
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case SP::STXri:
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MemBytes = TypeSize::getFixed(8);
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break;
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case SP::STFri:
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MemBytes = TypeSize::getFixed(4);
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break;
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case SP::STDFri:
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MemBytes = TypeSize::getFixed(8);
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break;
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case SP::STQFri:
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MemBytes = TypeSize::getFixed(16);
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break;
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}
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if (MI.getOperand(0).isFI() && MI.getOperand(1).isImm() &&
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MI.getOperand(1).getImm() == 0) {
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FrameIndex = MI.getOperand(0).getIndex();
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return MI.getOperand(2).getReg();
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}
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return 0;
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}
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@ -53,16 +53,16 @@ public:
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/// the destination along with the FrameIndex of the loaded stack slot. If
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/// not, return 0. This predicate must return 0 if the instruction has
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/// any side effects other than loading from the stack slot.
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Register isLoadFromStackSlot(const MachineInstr &MI,
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int &FrameIndex) const override;
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Register isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex,
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TypeSize &MemBytes) const override;
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/// isStoreToStackSlot - If the specified machine instruction is a direct
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/// store to a stack slot, return the virtual or physical register number of
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/// the source reg along with the FrameIndex of the loaded stack slot. If
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/// not, return 0. This predicate must return 0 if the instruction has
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/// any side effects other than storing to the stack slot.
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Register isStoreToStackSlot(const MachineInstr &MI,
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int &FrameIndex) const override;
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Register isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex,
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TypeSize &MemBytes) const override;
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MachineBasicBlock *getBranchDestBlock(const MachineInstr &MI) const override;
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179
llvm/test/CodeGen/SPARC/stack-slot-coloring.mir
Normal file
179
llvm/test/CodeGen/SPARC/stack-slot-coloring.mir
Normal file
@ -0,0 +1,179 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
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# RUN: llc -mtriple=sparcv9 -run-pass=greedy,virtregrewriter,stack-slot-coloring %s -o - | FileCheck %s
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# RUN: llc -mtriple=sparc -run-pass=greedy,virtregrewriter,stack-slot-coloring %s -o - | FileCheck %s
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--- |
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define dso_local i32 @main() local_unnamed_addr {
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entry:
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%a = alloca i64, align 4
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ret i32 0
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}
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...
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---
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name: main
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stack:
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- { id: 0, name: a, type: spill-slot, offset: 0, size: 8, alignment: 4,
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stack-id: default, callee-saved-register: '', callee-saved-restored: true,
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debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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body: |
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bb.0.entry:
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; CHECK-LABEL: name: main
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; CHECK: $i0 = LDri %stack.0.a, 0 :: (load (s32) from %ir.a)
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; CHECK-NEXT: $i1 = LDri %stack.0.a, 0 :: (load (s32) from %ir.a)
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; CHECK-NEXT: $i3 = LDri %stack.0.a, 0 :: (load (s32) from %ir.a)
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; CHECK-NEXT: $i4 = LDri %stack.0.a, 0 :: (load (s32) from %ir.a)
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; CHECK-NEXT: $i5 = LDri %stack.0.a, 0 :: (load (s32) from %ir.a)
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; CHECK-NEXT: $i6 = LDri %stack.0.a, 0 :: (load (s32) from %ir.a)
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; CHECK-NEXT: $i7 = LDri %stack.0.a, 0 :: (load (s32) from %ir.a)
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; CHECK-NEXT: $g0 = LDri %stack.0.a, 0 :: (load (s32) from %ir.a)
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; CHECK-NEXT: $g1 = LDri %stack.0.a, 0 :: (load (s32) from %ir.a)
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; CHECK-NEXT: $g2 = LDri %stack.0.a, 0 :: (load (s32) from %ir.a)
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; CHECK-NEXT: $g3 = LDri %stack.0.a, 0 :: (load (s32) from %ir.a)
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; CHECK-NEXT: $g4 = LDri %stack.0.a, 0 :: (load (s32) from %ir.a)
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; CHECK-NEXT: $g5 = LDri %stack.0.a, 0 :: (load (s32) from %ir.a)
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; CHECK-NEXT: $g6 = LDri %stack.0.a, 0 :: (load (s32) from %ir.a)
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; CHECK-NEXT: $g7 = LDri %stack.0.a, 0 :: (load (s32) from %ir.a)
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; CHECK-NEXT: $l0 = LDri %stack.0.a, 0 :: (load (s32) from %ir.a)
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; CHECK-NEXT: $l1 = LDri %stack.0.a, 0 :: (load (s32) from %ir.a)
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; CHECK-NEXT: $l2 = LDri %stack.0.a, 0 :: (load (s32) from %ir.a)
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; CHECK-NEXT: $l3 = LDri %stack.0.a, 0 :: (load (s32) from %ir.a)
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; CHECK-NEXT: $l4 = LDri %stack.0.a, 0 :: (load (s32) from %ir.a)
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; CHECK-NEXT: $l5 = LDri %stack.0.a, 0 :: (load (s32) from %ir.a)
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; CHECK-NEXT: $l6 = LDri %stack.0.a, 0 :: (load (s32) from %ir.a)
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; CHECK-NEXT: $l7 = LDri %stack.0.a, 0 :: (load (s32) from %ir.a)
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; CHECK-NEXT: $o0 = LDri %stack.0.a, 0 :: (load (s32) from %ir.a)
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; CHECK-NEXT: $o1 = LDri %stack.0.a, 0 :: (load (s32) from %ir.a)
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; CHECK-NEXT: $o2 = LDri %stack.0.a, 0 :: (load (s32) from %ir.a)
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; CHECK-NEXT: $o3 = LDri %stack.0.a, 0 :: (load (s32) from %ir.a)
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; CHECK-NEXT: $o4 = LDri %stack.0.a, 0 :: (load (s32) from %ir.a)
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; CHECK-NEXT: $o5 = LDri %stack.0.a, 0 :: (load (s32) from %ir.a)
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; CHECK-NEXT: $o6 = LDri %stack.0.a, 0 :: (load (s32) from %ir.a)
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; CHECK-NEXT: $o7 = LDri %stack.0.a, 0 :: (load (s32) from %ir.a)
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; CHECK-NEXT: renamable $i2 = LDri %stack.0.a, 0 :: (load (s32) from %ir.a)
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; CHECK-NEXT: STXri %stack.1, 0, killed renamable $i2 :: (store (s64) into %stack.1)
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; CHECK-NEXT: renamable $i2 = LDri %stack.0.a, 0 :: (load (s32) from %ir.a)
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; CHECK-NEXT: STXri %stack.0.a, 0, killed renamable $i2 :: (store (s64) into %ir.a)
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; CHECK-NEXT: renamable $i2 = LDXri %stack.1, 0 :: (load (s64) from %stack.1)
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; CHECK-NEXT: STri %stack.0.a, 0, killed renamable $i2 :: (store (s32) into %ir.a)
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; CHECK-NEXT: renamable $i2 = LDri %stack.0.a, 0 :: (load (s32) from %ir.a)
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; CHECK-NEXT: STXri %stack.1, 0, killed renamable $i2 :: (store (s64) into %stack.1)
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; CHECK-NEXT: renamable $i2 = LDri %stack.0.a, 0 :: (load (s32) from %ir.a)
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; CHECK-NEXT: STXri %stack.0.a, 0, killed renamable $i2 :: (store (s64) into %ir.a)
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; CHECK-NEXT: renamable $i2 = LDXri %stack.1, 0 :: (load (s64) from %stack.1)
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; CHECK-NEXT: STri %stack.0.a, 0, killed renamable $i2 :: (store (s32) into %ir.a)
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; CHECK-NEXT: STri %stack.0.a, 0, $i0 :: (store (s32) into %ir.a)
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; CHECK-NEXT: STri %stack.0.a, 0, $i1 :: (store (s32) into %ir.a)
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; CHECK-NEXT: STri %stack.0.a, 0, $i3 :: (store (s32) into %ir.a)
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; CHECK-NEXT: STri %stack.0.a, 0, $i4 :: (store (s32) into %ir.a)
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; CHECK-NEXT: STri %stack.0.a, 0, $i5 :: (store (s32) into %ir.a)
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; CHECK-NEXT: STri %stack.0.a, 0, $i6 :: (store (s32) into %ir.a)
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; CHECK-NEXT: STri %stack.0.a, 0, $i7 :: (store (s32) into %ir.a)
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; CHECK-NEXT: STri %stack.0.a, 0, $g0 :: (store (s32) into %ir.a)
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; CHECK-NEXT: STri %stack.0.a, 0, $g1 :: (store (s32) into %ir.a)
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; CHECK-NEXT: STri %stack.0.a, 0, $g2 :: (store (s32) into %ir.a)
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; CHECK-NEXT: STri %stack.0.a, 0, $g3 :: (store (s32) into %ir.a)
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; CHECK-NEXT: STri %stack.0.a, 0, $g4 :: (store (s32) into %ir.a)
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; CHECK-NEXT: STri %stack.0.a, 0, $g5 :: (store (s32) into %ir.a)
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; CHECK-NEXT: STri %stack.0.a, 0, $g6 :: (store (s32) into %ir.a)
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; CHECK-NEXT: STri %stack.0.a, 0, $g7 :: (store (s32) into %ir.a)
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; CHECK-NEXT: STri %stack.0.a, 0, $l0 :: (store (s32) into %ir.a)
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; CHECK-NEXT: STri %stack.0.a, 0, $l1 :: (store (s32) into %ir.a)
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; CHECK-NEXT: STri %stack.0.a, 0, $l2 :: (store (s32) into %ir.a)
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; CHECK-NEXT: STri %stack.0.a, 0, $l3 :: (store (s32) into %ir.a)
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; CHECK-NEXT: STri %stack.0.a, 0, $l4 :: (store (s32) into %ir.a)
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; CHECK-NEXT: STri %stack.0.a, 0, $l5 :: (store (s32) into %ir.a)
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; CHECK-NEXT: STri %stack.0.a, 0, $l6 :: (store (s32) into %ir.a)
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; CHECK-NEXT: STri %stack.0.a, 0, $l7 :: (store (s32) into %ir.a)
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; CHECK-NEXT: STri %stack.0.a, 0, $o0 :: (store (s32) into %ir.a)
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; CHECK-NEXT: STri %stack.0.a, 0, $o1 :: (store (s32) into %ir.a)
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; CHECK-NEXT: STri %stack.0.a, 0, $o2 :: (store (s32) into %ir.a)
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; CHECK-NEXT: STri %stack.0.a, 0, $o3 :: (store (s32) into %ir.a)
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; CHECK-NEXT: STri %stack.0.a, 0, $o4 :: (store (s32) into %ir.a)
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; CHECK-NEXT: STri %stack.0.a, 0, $o5 :: (store (s32) into %ir.a)
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; CHECK-NEXT: STri %stack.0.a, 0, $o6 :: (store (s32) into %ir.a)
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; CHECK-NEXT: STri %stack.0.a, 0, $o7 :: (store (s32) into %ir.a)
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; CHECK-NEXT: RETL 8, implicit $i0
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$i0 = LDri %stack.0.a, 0 :: (load (s32) from %ir.a)
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$i1 = LDri %stack.0.a, 0 :: (load (s32) from %ir.a)
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$i3 = LDri %stack.0.a, 0 :: (load (s32) from %ir.a)
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$i4 = LDri %stack.0.a, 0 :: (load (s32) from %ir.a)
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$i5 = LDri %stack.0.a, 0 :: (load (s32) from %ir.a)
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$i6 = LDri %stack.0.a, 0 :: (load (s32) from %ir.a)
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$i7 = LDri %stack.0.a, 0 :: (load (s32) from %ir.a)
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$g0 = LDri %stack.0.a, 0 :: (load (s32) from %ir.a)
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$g1 = LDri %stack.0.a, 0 :: (load (s32) from %ir.a)
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$g2 = LDri %stack.0.a, 0 :: (load (s32) from %ir.a)
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$g3 = LDri %stack.0.a, 0 :: (load (s32) from %ir.a)
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$g4 = LDri %stack.0.a, 0 :: (load (s32) from %ir.a)
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$g5 = LDri %stack.0.a, 0 :: (load (s32) from %ir.a)
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$g6 = LDri %stack.0.a, 0 :: (load (s32) from %ir.a)
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$g7 = LDri %stack.0.a, 0 :: (load (s32) from %ir.a)
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$l0 = LDri %stack.0.a, 0 :: (load (s32) from %ir.a)
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$l1 = LDri %stack.0.a, 0 :: (load (s32) from %ir.a)
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$l2 = LDri %stack.0.a, 0 :: (load (s32) from %ir.a)
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$l3 = LDri %stack.0.a, 0 :: (load (s32) from %ir.a)
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$l4 = LDri %stack.0.a, 0 :: (load (s32) from %ir.a)
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$l5 = LDri %stack.0.a, 0 :: (load (s32) from %ir.a)
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$l6 = LDri %stack.0.a, 0 :: (load (s32) from %ir.a)
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$l7 = LDri %stack.0.a, 0 :: (load (s32) from %ir.a)
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$o0 = LDri %stack.0.a, 0 :: (load (s32) from %ir.a)
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$o1 = LDri %stack.0.a, 0 :: (load (s32) from %ir.a)
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$o2 = LDri %stack.0.a, 0 :: (load (s32) from %ir.a)
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$o3 = LDri %stack.0.a, 0 :: (load (s32) from %ir.a)
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$o4 = LDri %stack.0.a, 0 :: (load (s32) from %ir.a)
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$o5 = LDri %stack.0.a, 0 :: (load (s32) from %ir.a)
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$o6 = LDri %stack.0.a, 0 :: (load (s32) from %ir.a)
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$o7 = LDri %stack.0.a, 0 :: (load (s32) from %ir.a)
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; First vreg load
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%1:i64regs = LDri %stack.0.a, 0 :: (load (s32) from %ir.a)
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; First faulty sequence; %1 spilt
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%12:i64regs = LDri %stack.0.a, 0 :: (load (s32) from %ir.a)
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STXri %stack.0.a, 0, %12 :: (store (s64) into %ir.a)
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; Store %1 to avoid it being optimised out, will result in a load-from-spill
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STri %stack.0.a, 0, %1 :: (store (s32) into %ir.a)
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; That code sequence a second time, to generate a second spill slot that
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; will get coloured and merged.
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%2:i64regs = LDri %stack.0.a, 0 :: (load (s32) from %ir.a)
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%22:i64regs = LDri %stack.0.a, 0 :: (load (s32) from %ir.a)
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STXri %stack.0.a, 0, %22 :: (store (s64) into %ir.a)
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STri %stack.0.a, 0, %2 :: (store (s32) into %ir.a)
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STri %stack.0.a, 0, $i0 :: (store (s32) into %ir.a)
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STri %stack.0.a, 0, $i1 :: (store (s32) into %ir.a)
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STri %stack.0.a, 0, $i3 :: (store (s32) into %ir.a)
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STri %stack.0.a, 0, $i4 :: (store (s32) into %ir.a)
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STri %stack.0.a, 0, $i5 :: (store (s32) into %ir.a)
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STri %stack.0.a, 0, $i6 :: (store (s32) into %ir.a)
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STri %stack.0.a, 0, $i7 :: (store (s32) into %ir.a)
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STri %stack.0.a, 0, $g0 :: (store (s32) into %ir.a)
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STri %stack.0.a, 0, $g1 :: (store (s32) into %ir.a)
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STri %stack.0.a, 0, $g2 :: (store (s32) into %ir.a)
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STri %stack.0.a, 0, $g3 :: (store (s32) into %ir.a)
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STri %stack.0.a, 0, $g4 :: (store (s32) into %ir.a)
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STri %stack.0.a, 0, $g5 :: (store (s32) into %ir.a)
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STri %stack.0.a, 0, $g6 :: (store (s32) into %ir.a)
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STri %stack.0.a, 0, $g7 :: (store (s32) into %ir.a)
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STri %stack.0.a, 0, $l0 :: (store (s32) into %ir.a)
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STri %stack.0.a, 0, $l1 :: (store (s32) into %ir.a)
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STri %stack.0.a, 0, $l2 :: (store (s32) into %ir.a)
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STri %stack.0.a, 0, $l3 :: (store (s32) into %ir.a)
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STri %stack.0.a, 0, $l4 :: (store (s32) into %ir.a)
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STri %stack.0.a, 0, $l5 :: (store (s32) into %ir.a)
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STri %stack.0.a, 0, $l6 :: (store (s32) into %ir.a)
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STri %stack.0.a, 0, $l7 :: (store (s32) into %ir.a)
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STri %stack.0.a, 0, $o0 :: (store (s32) into %ir.a)
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STri %stack.0.a, 0, $o1 :: (store (s32) into %ir.a)
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STri %stack.0.a, 0, $o2 :: (store (s32) into %ir.a)
|
||||
STri %stack.0.a, 0, $o3 :: (store (s32) into %ir.a)
|
||||
STri %stack.0.a, 0, $o4 :: (store (s32) into %ir.a)
|
||||
STri %stack.0.a, 0, $o5 :: (store (s32) into %ir.a)
|
||||
STri %stack.0.a, 0, $o6 :: (store (s32) into %ir.a)
|
||||
STri %stack.0.a, 0, $o7 :: (store (s32) into %ir.a)
|
||||
RETL 8, implicit $i0
|
||||
...
|
||||
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Reference in New Issue
Block a user