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[InstCombine] Use KnownBits::ashr()

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This fixes a consistency violation under -instcombine-verify-known-bits.
This commit is contained in:
Nikita Popov 2024-07-01 14:48:21 +02:00
parent 035e76ff37
commit 154c8a02ed
2 changed files with 6 additions and 11 deletions
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15
llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
View File

@ -812,15 +812,15 @@ Value *InstCombinerImpl::SimplifyDemandedUseBits(Value *V, APInt DemandedMask,
return I;
}
// Compute the new bits that are at the top now plus sign bits.
APInt HighBits(APInt::getHighBitsSet(
BitWidth, std::min(SignBits + ShiftAmt - 1, BitWidth)));
Known.Zero.lshrInPlace(ShiftAmt);
Known.One.lshrInPlace(ShiftAmt);
Known = KnownBits::ashr(
Known, KnownBits::makeConstant(APInt(BitWidth, ShiftAmt)),
ShiftAmt != 0, I->isExact());
// If the input sign bit is known to be zero, or if none of the top bits
// are demanded, turn this into an unsigned shift right.
assert(BitWidth > ShiftAmt && "Shift amount not saturated?");
APInt HighBits(APInt::getHighBitsSet(
BitWidth, std::min(SignBits + ShiftAmt - 1, BitWidth)));
if (Known.Zero[BitWidth-ShiftAmt-1] ||
!DemandedMask.intersects(HighBits)) {
BinaryOperator *LShr = BinaryOperator::CreateLShr(I->getOperand(0),
@ -828,11 +828,6 @@ Value *InstCombinerImpl::SimplifyDemandedUseBits(Value *V, APInt DemandedMask,
LShr->setIsExact(cast<BinaryOperator>(I)->isExact());
LShr->takeName(I);
return InsertNewInstWith(LShr, I->getIterator());
} else if (Known.One[BitWidth-ShiftAmt-1]) { // New bits are known one.
Known.One |= HighBits;
// SignBits may be out-of-sync with Known.countMinSignBits(). Mask out
// high bits of Known.Zero to avoid conflicts.
Known.Zero &= ~HighBits;
}
} else {
llvm::computeKnownBits(I, Known, Depth, Q);

2
llvm/test/Transforms/InstCombine/pr80597.ll
View File

@ -11,7 +11,7 @@ define i64 @pr80597(i1 %cond) {
; CHECK-NEXT: br i1 [[CMP]], label [[IF_THEN:%.*]], label [[IF_ELSE:%.*]]
; CHECK: if.else:
; CHECK-NEXT: [[SEXT2:%.*]] = ashr exact i64 [[ADD]], 1
; CHECK-NEXT: [[ASHR:%.*]] = or i64 [[SEXT2]], 4418419761487020032
; CHECK-NEXT: [[ASHR:%.*]] = or disjoint i64 [[SEXT2]], 4418419761487020032
; CHECK-NEXT: ret i64 [[ASHR]]
; CHECK: if.then:
; CHECK-NEXT: ret i64 0