[LLVM][CodeGen][SVE] Add ISel for bfloat scalable vector compares. (#138707)
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@ -1758,10 +1758,10 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
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for (auto Opcode :
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{ISD::FCEIL, ISD::FDIV, ISD::FFLOOR, ISD::FNEARBYINT, ISD::FRINT,
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ISD::FROUND, ISD::FROUNDEVEN, ISD::FSQRT, ISD::FTRUNC}) {
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ISD::FROUND, ISD::FROUNDEVEN, ISD::FSQRT, ISD::FTRUNC, ISD::SETCC}) {
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setOperationPromotedToType(Opcode, MVT::nxv2bf16, MVT::nxv2f32);
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setOperationPromotedToType(Opcode, MVT::nxv4bf16, MVT::nxv4f32);
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setOperationAction(Opcode, MVT::nxv8bf16, Expand);
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setOperationPromotedToType(Opcode, MVT::nxv8bf16, MVT::nxv8f32);
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}
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if (!Subtarget->hasSVEB16B16()) {
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@ -1769,7 +1769,7 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
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ISD::FMINIMUM, ISD::FMINNUM, ISD::FMUL, ISD::FSUB}) {
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setOperationPromotedToType(Opcode, MVT::nxv2bf16, MVT::nxv2f32);
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setOperationPromotedToType(Opcode, MVT::nxv4bf16, MVT::nxv4f32);
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setOperationAction(Opcode, MVT::nxv8bf16, Expand);
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setOperationPromotedToType(Opcode, MVT::nxv8bf16, MVT::nxv8f32);
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}
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}
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1001
llvm/test/CodeGen/AArch64/sve-bf16-compares.ll
Normal file
1001
llvm/test/CodeGen/AArch64/sve-bf16-compares.ll
Normal file
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