[mlir][arith][spirv] Hard fail in -convert-arith-to-spirv
Turn legalization failures into hard failures to make sure that we do not miss conversion pattern application failures. Add a message on type conversion failure. Move unsupported cases into a separate test file. Reviewed By: antiagainst Differential Revision: https://reviews.llvm.org/D137102
This commit is contained in:
Jakub Kuderski
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d4c8a0edca
commit
179978d7b8
@ -1046,6 +1046,9 @@ struct ConvertArithToSPIRVPass
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typeConverter.addTargetMaterialization(addUnrealizedCast);
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target->addLegalOp<UnrealizedConversionCastOp>();
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// Fail hard when there are any remaining 'arith' ops.
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target->addIllegalDialect<arith::ArithDialect>();
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RewritePatternSet patterns(&getContext());
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arith::populateArithToSPIRVPatterns(typeConverter, patterns);
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@ -11,6 +11,7 @@
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#include "mlir/Dialect/SPIRV/IR/SPIRVOpTraits.h"
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#include "mlir/Transforms/DialectConversion.h"
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#include "llvm/Support/FormatVariadic.h"
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namespace mlir {
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namespace spirv {
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@ -26,9 +27,13 @@ public:
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matchAndRewrite(Op op, typename Op::Adaptor adaptor,
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ConversionPatternRewriter &rewriter) const override {
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assert(adaptor.getOperands().size() <= 3);
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auto dstType = this->getTypeConverter()->convertType(op.getType());
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if (!dstType)
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return failure();
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Type dstType = this->getTypeConverter()->convertType(op.getType());
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if (!dstType) {
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return rewriter.notifyMatchFailure(
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op->getLoc(),
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llvm::formatv("failed to convert type {0} for SPIR-V", op.getType()));
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}
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if (SPIRVOp::template hasTrait<OpTrait::spirv::UnsignedOp>() &&
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!op.getType().isIndex() && dstType != op.getType()) {
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return op.emitError(
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@ -0,0 +1,72 @@
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// RUN: mlir-opt -split-input-file -convert-arith-to-spirv -verify-diagnostics %s
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///===----------------------------------------------------------------------===//
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// Binary ops
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//===----------------------------------------------------------------------===//
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// -----
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module attributes {
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spirv.target_env = #spirv.target_env<
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#spirv.vce<v1.0, [Int8, Int16, Int64, Float16, Float64, Shader], []>, #spirv.resource_limits<>>
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} {
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func.func @unsupported_5elem_vector(%arg0: vector<5xi32>) {
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// expected-error@+1 {{failed to legalize operation 'arith.subi'}}
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%1 = arith.subi %arg0, %arg0: vector<5xi32>
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return
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}
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} // end module
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// -----
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module attributes {
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spirv.target_env = #spirv.target_env<
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#spirv.vce<v1.0, [Int8, Int16, Int64, Float16, Float64, Shader], []>, #spirv.resource_limits<>>
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} {
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func.func @unsupported_2x2elem_vector(%arg0: vector<2x2xi32>) {
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// expected-error@+1 {{failed to legalize operation 'arith.muli'}}
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%2 = arith.muli %arg0, %arg0: vector<2x2xi32>
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return
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}
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} // end module
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// -----
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func.func @int_vector4_invalid(%arg0: vector<2xi16>) {
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// expected-error @+2 {{failed to legalize operation 'arith.divui'}}
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// expected-error @+1 {{bitwidth emulation is not implemented yet on unsigned op}}
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%0 = arith.divui %arg0, %arg0: vector<2xi16>
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return
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}
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///===----------------------------------------------------------------------===//
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// Constant ops
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//===----------------------------------------------------------------------===//
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// -----
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func.func @unsupported_constant_0() {
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// expected-error @+1 {{failed to legalize operation 'arith.constant'}}
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%0 = arith.constant 4294967296 : i64 // 2^32
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return
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}
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// -----
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func.func @unsupported_constant_1() {
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// expected-error @+1 {{failed to legalize operation 'arith.constant'}}
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%1 = arith.constant -2147483649 : i64 // -2^31 - 1
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return
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}
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// -----
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func.func @unsupported_constant_2() {
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// expected-error @+1 {{failed to legalize operation 'arith.constant'}}
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%2 = arith.constant -2147483649 : i64 // -2^31 - 1
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return
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}
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@ -163,63 +163,6 @@ func.func @one_elem_vector(%arg0: vector<1xi32>) {
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return
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}
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// CHECK-LABEL: @unsupported_5elem_vector
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func.func @unsupported_5elem_vector(%arg0: vector<5xi32>) {
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// CHECK: arith.subi
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%1 = arith.subi %arg0, %arg0: vector<5xi32>
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return
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}
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// CHECK-LABEL: @unsupported_2x2elem_vector
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func.func @unsupported_2x2elem_vector(%arg0: vector<2x2xi32>) {
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// CHECK: arith.muli
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%2 = arith.muli %arg0, %arg0: vector<2x2xi32>
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return
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}
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} // end module
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// -----
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// Check that types are converted to 32-bit when no special capabilities.
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module attributes {
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spirv.target_env = #spirv.target_env<#spirv.vce<v1.0, [], []>, #spirv.resource_limits<>>
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} {
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// CHECK-LABEL: @int_vector23
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func.func @int_vector23(%arg0: vector<2xi8>, %arg1: vector<3xi16>) {
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// CHECK: spirv.SDiv %{{.*}}, %{{.*}}: vector<2xi32>
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%0 = arith.divsi %arg0, %arg0: vector<2xi8>
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// CHECK: spirv.SDiv %{{.*}}, %{{.*}}: vector<3xi32>
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%1 = arith.divsi %arg1, %arg1: vector<3xi16>
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return
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}
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// CHECK-LABEL: @float_scalar
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func.func @float_scalar(%arg0: f16, %arg1: f64) {
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// CHECK: spirv.FAdd %{{.*}}, %{{.*}}: f32
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%0 = arith.addf %arg0, %arg0: f16
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// CHECK: spirv.FMul %{{.*}}, %{{.*}}: f32
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%1 = arith.mulf %arg1, %arg1: f64
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return
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}
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} // end module
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// -----
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// Check that types are converted to 32-bit when no special capabilities that
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// are not supported.
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module attributes {
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spirv.target_env = #spirv.target_env<#spirv.vce<v1.0, [], []>, #spirv.resource_limits<>>
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} {
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func.func @int_vector4_invalid(%arg0: vector<4xi64>) {
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// expected-error @+1 {{bitwidth emulation is not implemented yet on unsigned op}}
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%0 = arith.divui %arg0, %arg0: vector<4xi64>
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return
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}
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} // end module
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// -----
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@ -643,17 +586,6 @@ func.func @corner_cases() {
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return
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}
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// CHECK-LABEL: @unsupported_cases
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func.func @unsupported_cases() {
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// CHECK: %{{.*}} = arith.constant 4294967296 : i64
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%0 = arith.constant 4294967296 : i64 // 2^32
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// CHECK: %{{.*}} = arith.constant -2147483649 : i64
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%1 = arith.constant -2147483649 : i64 // -2^31 - 1
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// CHECK: %{{.*}} = arith.constant 1.0000000000000002 : f64
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%2 = arith.constant 0x3FF0000000000001 : f64 // smallest number > 1
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return
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}
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} // end module
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// -----
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@ -1258,20 +1190,6 @@ func.func @one_elem_vector(%arg0: vector<1xi32>) {
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return
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}
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// CHECK-LABEL: @unsupported_5elem_vector
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func.func @unsupported_5elem_vector(%arg0: vector<5xi32>) {
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// CHECK: subi
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%1 = arith.subi %arg0, %arg0: vector<5xi32>
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return
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}
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// CHECK-LABEL: @unsupported_2x2elem_vector
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func.func @unsupported_2x2elem_vector(%arg0: vector<2x2xi32>) {
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// CHECK: muli
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%2 = arith.muli %arg0, %arg0: vector<2x2xi32>
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return
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}
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} // end module
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// -----
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@ -1303,22 +1221,6 @@ func.func @float_scalar(%arg0: f16, %arg1: f64) {
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// -----
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// Check that types are converted to 32-bit when no special capabilities that
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// are not supported.
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module attributes {
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spirv.target_env = #spirv.target_env<#spirv.vce<v1.0, [], []>, #spirv.resource_limits<>>
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} {
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func.func @int_vector4_invalid(%arg0: vector<4xi64>) {
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// expected-error@+1 {{bitwidth emulation is not implemented yet on unsigned op}}
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%0 = arith.divui %arg0, %arg0: vector<4xi64>
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return
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}
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} // end module
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// -----
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//===----------------------------------------------------------------------===//
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// std bit ops
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//===----------------------------------------------------------------------===//
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@ -1675,17 +1577,6 @@ func.func @corner_cases() {
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return
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}
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// CHECK-LABEL: @unsupported_cases
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func.func @unsupported_cases() {
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// CHECK: %{{.*}} = arith.constant 4294967296 : i64
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%0 = arith.constant 4294967296 : i64 // 2^32
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// CHECK: %{{.*}} = arith.constant -2147483649 : i64
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%1 = arith.constant -2147483649 : i64 // -2^31 - 1
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// CHECK: %{{.*}} = arith.constant 1.0000000000000002 : f64
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%2 = arith.constant 0x3FF0000000000001 : f64 // smallest number > 1
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return
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}
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} // end module
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// -----
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