[RISCV] Optimize the spill/reload of segment registers (#153184)
The simplest way is: 1. Save `vtype` to a scalar register. 2. Insert a `vsetvli`. 3. Use segment load/store. 4. Restore `vtype` via `vsetvl`. But `vsetvl` is usually slow, so this PR is not in this way. Instead, we use wider whole load/store instructions if the register encoding is aligned. We have done the same optimization for COPY in https://github.com/llvm/llvm-project/pull/84455. We found this suboptimal implementation when porting some video codec kernels via RVV intrinsics.
This commit is contained in:
Pengcheng Wang
GitHub
parent
2e74cc6c04
commit
17a98f85c2
@ -382,7 +382,7 @@ void RISCVInstrInfo::copyPhysRegVector(
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MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
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const DebugLoc &DL, MCRegister DstReg, MCRegister SrcReg, bool KillSrc,
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const TargetRegisterClass *RegClass) const {
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const TargetRegisterInfo *TRI = STI.getRegisterInfo();
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const RISCVRegisterInfo *TRI = STI.getRegisterInfo();
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RISCVVType::VLMUL LMul = RISCVRI::getLMul(RegClass->TSFlags);
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unsigned NF = RISCVRI::getNF(RegClass->TSFlags);
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@ -444,13 +444,7 @@ void RISCVInstrInfo::copyPhysRegVector(
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return {RISCVVType::LMUL_1, RISCV::VRRegClass, RISCV::VMV1R_V,
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RISCV::PseudoVMV_V_V_M1, RISCV::PseudoVMV_V_I_M1};
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};
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auto FindRegWithEncoding = [TRI](const TargetRegisterClass &RegClass,
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uint16_t Encoding) {
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MCRegister Reg = RISCV::V0 + Encoding;
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if (RISCVRI::getLMul(RegClass.TSFlags) == RISCVVType::LMUL_1)
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return Reg;
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return TRI->getMatchingSuperReg(Reg, RISCV::sub_vrm1_0, &RegClass);
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};
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while (I != NumRegs) {
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// For non-segment copying, we only do this once as the registers are always
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// aligned.
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@ -470,9 +464,9 @@ void RISCVInstrInfo::copyPhysRegVector(
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// Emit actual copying.
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// For reversed copying, the encoding should be decreased.
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MCRegister ActualSrcReg = FindRegWithEncoding(
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MCRegister ActualSrcReg = TRI->findVRegWithEncoding(
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RegClass, ReversedCopy ? (SrcEncoding - NumCopied + 1) : SrcEncoding);
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MCRegister ActualDstReg = FindRegWithEncoding(
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MCRegister ActualDstReg = TRI->findVRegWithEncoding(
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RegClass, ReversedCopy ? (DstEncoding - NumCopied + 1) : DstEncoding);
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auto MIB = BuildMI(MBB, MBBI, DL, get(Opc), ActualDstReg);
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@ -389,9 +389,25 @@ void RISCVRegisterInfo::adjustReg(MachineBasicBlock &MBB,
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.setMIFlag(Flag);
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}
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// Split a VSPILLx_Mx pseudo into multiple whole register stores separated by
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// LMUL*VLENB bytes.
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void RISCVRegisterInfo::lowerVSPILL(MachineBasicBlock::iterator II) const {
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static std::tuple<RISCVVType::VLMUL, const TargetRegisterClass &, unsigned>
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getSpillReloadInfo(unsigned NumRemaining, uint16_t RegEncoding, bool IsSpill) {
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if (NumRemaining >= 8 && RegEncoding % 8 == 0)
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return {RISCVVType::LMUL_8, RISCV::VRM8RegClass,
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IsSpill ? RISCV::VS8R_V : RISCV::VL8RE8_V};
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if (NumRemaining >= 4 && RegEncoding % 4 == 0)
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return {RISCVVType::LMUL_4, RISCV::VRM4RegClass,
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IsSpill ? RISCV::VS4R_V : RISCV::VL4RE8_V};
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if (NumRemaining >= 2 && RegEncoding % 2 == 0)
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return {RISCVVType::LMUL_2, RISCV::VRM2RegClass,
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IsSpill ? RISCV::VS2R_V : RISCV::VL2RE8_V};
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return {RISCVVType::LMUL_1, RISCV::VRRegClass,
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IsSpill ? RISCV::VS1R_V : RISCV::VL1RE8_V};
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}
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// Split a VSPILLx_Mx/VSPILLx_Mx pseudo into multiple whole register stores
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// separated by LMUL*VLENB bytes.
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void RISCVRegisterInfo::lowerSegmentSpillReload(MachineBasicBlock::iterator II,
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bool IsSpill) const {
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DebugLoc DL = II->getDebugLoc();
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MachineBasicBlock &MBB = *II->getParent();
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MachineFunction &MF = *MBB.getParent();
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@ -403,47 +419,11 @@ void RISCVRegisterInfo::lowerVSPILL(MachineBasicBlock::iterator II) const {
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auto ZvlssegInfo = RISCV::isRVVSpillForZvlsseg(II->getOpcode());
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unsigned NF = ZvlssegInfo->first;
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unsigned LMUL = ZvlssegInfo->second;
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assert(NF * LMUL <= 8 && "Invalid NF/LMUL combinations.");
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unsigned Opcode, SubRegIdx;
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switch (LMUL) {
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default:
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llvm_unreachable("LMUL must be 1, 2, or 4.");
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case 1:
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Opcode = RISCV::VS1R_V;
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SubRegIdx = RISCV::sub_vrm1_0;
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break;
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case 2:
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Opcode = RISCV::VS2R_V;
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SubRegIdx = RISCV::sub_vrm2_0;
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break;
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case 4:
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Opcode = RISCV::VS4R_V;
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SubRegIdx = RISCV::sub_vrm4_0;
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break;
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}
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static_assert(RISCV::sub_vrm1_7 == RISCV::sub_vrm1_0 + 7,
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"Unexpected subreg numbering");
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static_assert(RISCV::sub_vrm2_3 == RISCV::sub_vrm2_0 + 3,
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"Unexpected subreg numbering");
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static_assert(RISCV::sub_vrm4_1 == RISCV::sub_vrm4_0 + 1,
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"Unexpected subreg numbering");
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unsigned NumRegs = NF * LMUL;
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assert(NumRegs <= 8 && "Invalid NF/LMUL combinations.");
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Register VL = MRI.createVirtualRegister(&RISCV::GPRRegClass);
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// Optimize for constant VLEN.
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if (auto VLEN = STI.getRealVLen()) {
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const int64_t VLENB = *VLEN / 8;
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int64_t Offset = VLENB * LMUL;
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STI.getInstrInfo()->movImm(MBB, II, DL, VL, Offset);
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} else {
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BuildMI(MBB, II, DL, TII->get(RISCV::PseudoReadVLENB), VL);
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uint32_t ShiftAmount = Log2_32(LMUL);
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if (ShiftAmount != 0)
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BuildMI(MBB, II, DL, TII->get(RISCV::SLLI), VL)
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.addReg(VL)
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.addImm(ShiftAmount);
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}
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Register SrcReg = II->getOperand(0).getReg();
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Register Reg = II->getOperand(0).getReg();
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uint16_t RegEncoding = TRI->getEncodingValue(Reg);
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Register Base = II->getOperand(1).getReg();
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bool IsBaseKill = II->getOperand(1).isKill();
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Register NewBase = MRI.createVirtualRegister(&RISCV::GPRRegClass);
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@ -451,100 +431,63 @@ void RISCVRegisterInfo::lowerVSPILL(MachineBasicBlock::iterator II) const {
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auto *OldMMO = *(II->memoperands_begin());
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LocationSize OldLoc = OldMMO->getSize();
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assert(OldLoc.isPrecise() && OldLoc.getValue().isKnownMultipleOf(NF));
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TypeSize NewSize = OldLoc.getValue().divideCoefficientBy(NF);
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auto *NewMMO = MF.getMachineMemOperand(OldMMO, OldMMO->getOffset(), NewSize);
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for (unsigned I = 0; I < NF; ++I) {
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TypeSize VRegSize = OldLoc.getValue().divideCoefficientBy(NumRegs);
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Register VLENB = 0;
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unsigned PreHandledNum = 0;
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unsigned I = 0;
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while (I != NumRegs) {
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auto [LMulHandled, RegClass, Opcode] =
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getSpillReloadInfo(NumRegs - I, RegEncoding, IsSpill);
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auto [RegNumHandled, _] = RISCVVType::decodeVLMUL(LMulHandled);
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bool IsLast = I + RegNumHandled == NumRegs;
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if (PreHandledNum) {
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Register Step;
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// Optimize for constant VLEN.
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if (auto VLEN = STI.getRealVLen()) {
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int64_t Offset = *VLEN / 8 * PreHandledNum;
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Step = MRI.createVirtualRegister(&RISCV::GPRRegClass);
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STI.getInstrInfo()->movImm(MBB, II, DL, Step, Offset);
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} else {
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if (!VLENB) {
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VLENB = MRI.createVirtualRegister(&RISCV::GPRRegClass);
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BuildMI(MBB, II, DL, TII->get(RISCV::PseudoReadVLENB), VLENB);
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}
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uint32_t ShiftAmount = Log2_32(PreHandledNum);
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if (ShiftAmount == 0)
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Step = VLENB;
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else {
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Step = MRI.createVirtualRegister(&RISCV::GPRRegClass);
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BuildMI(MBB, II, DL, TII->get(RISCV::SLLI), Step)
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.addReg(VLENB, getKillRegState(IsLast))
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.addImm(ShiftAmount);
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}
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}
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BuildMI(MBB, II, DL, TII->get(RISCV::ADD), NewBase)
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.addReg(Base, getKillRegState(I != 0 || IsBaseKill))
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.addReg(Step, getKillRegState(Step != VLENB || IsLast));
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Base = NewBase;
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}
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MCRegister ActualReg = findVRegWithEncoding(RegClass, RegEncoding);
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MachineInstrBuilder MIB =
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BuildMI(MBB, II, DL, TII->get(Opcode))
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.addReg(ActualReg, getDefRegState(!IsSpill))
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.addReg(Base, getKillRegState(IsLast))
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.addMemOperand(MF.getMachineMemOperand(OldMMO, OldMMO->getOffset(),
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VRegSize * RegNumHandled));
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// Adding implicit-use of super register to describe we are using part of
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// super register, that prevents machine verifier complaining when part of
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// subreg is undef, see comment in MachineVerifier::checkLiveness for more
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// detail.
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BuildMI(MBB, II, DL, TII->get(Opcode))
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.addReg(TRI->getSubReg(SrcReg, SubRegIdx + I))
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.addReg(Base, getKillRegState(I == NF - 1))
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.addMemOperand(NewMMO)
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.addReg(SrcReg, RegState::Implicit);
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if (I != NF - 1)
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BuildMI(MBB, II, DL, TII->get(RISCV::ADD), NewBase)
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.addReg(Base, getKillRegState(I != 0 || IsBaseKill))
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.addReg(VL, getKillRegState(I == NF - 2));
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Base = NewBase;
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}
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II->eraseFromParent();
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}
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if (IsSpill)
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MIB.addReg(Reg, RegState::Implicit);
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// Split a VSPILLx_Mx pseudo into multiple whole register loads separated by
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// LMUL*VLENB bytes.
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void RISCVRegisterInfo::lowerVRELOAD(MachineBasicBlock::iterator II) const {
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DebugLoc DL = II->getDebugLoc();
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MachineBasicBlock &MBB = *II->getParent();
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MachineFunction &MF = *MBB.getParent();
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MachineRegisterInfo &MRI = MF.getRegInfo();
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const RISCVSubtarget &STI = MF.getSubtarget<RISCVSubtarget>();
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const TargetInstrInfo *TII = STI.getInstrInfo();
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const TargetRegisterInfo *TRI = STI.getRegisterInfo();
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auto ZvlssegInfo = RISCV::isRVVSpillForZvlsseg(II->getOpcode());
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unsigned NF = ZvlssegInfo->first;
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unsigned LMUL = ZvlssegInfo->second;
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assert(NF * LMUL <= 8 && "Invalid NF/LMUL combinations.");
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unsigned Opcode, SubRegIdx;
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switch (LMUL) {
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default:
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llvm_unreachable("LMUL must be 1, 2, or 4.");
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case 1:
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Opcode = RISCV::VL1RE8_V;
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SubRegIdx = RISCV::sub_vrm1_0;
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break;
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case 2:
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Opcode = RISCV::VL2RE8_V;
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SubRegIdx = RISCV::sub_vrm2_0;
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break;
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case 4:
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Opcode = RISCV::VL4RE8_V;
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SubRegIdx = RISCV::sub_vrm4_0;
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break;
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}
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static_assert(RISCV::sub_vrm1_7 == RISCV::sub_vrm1_0 + 7,
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"Unexpected subreg numbering");
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static_assert(RISCV::sub_vrm2_3 == RISCV::sub_vrm2_0 + 3,
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"Unexpected subreg numbering");
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static_assert(RISCV::sub_vrm4_1 == RISCV::sub_vrm4_0 + 1,
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"Unexpected subreg numbering");
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Register VL = MRI.createVirtualRegister(&RISCV::GPRRegClass);
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// Optimize for constant VLEN.
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if (auto VLEN = STI.getRealVLen()) {
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const int64_t VLENB = *VLEN / 8;
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int64_t Offset = VLENB * LMUL;
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STI.getInstrInfo()->movImm(MBB, II, DL, VL, Offset);
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} else {
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BuildMI(MBB, II, DL, TII->get(RISCV::PseudoReadVLENB), VL);
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uint32_t ShiftAmount = Log2_32(LMUL);
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if (ShiftAmount != 0)
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BuildMI(MBB, II, DL, TII->get(RISCV::SLLI), VL)
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.addReg(VL)
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.addImm(ShiftAmount);
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}
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Register DestReg = II->getOperand(0).getReg();
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Register Base = II->getOperand(1).getReg();
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bool IsBaseKill = II->getOperand(1).isKill();
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Register NewBase = MRI.createVirtualRegister(&RISCV::GPRRegClass);
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auto *OldMMO = *(II->memoperands_begin());
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LocationSize OldLoc = OldMMO->getSize();
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assert(OldLoc.isPrecise() && OldLoc.getValue().isKnownMultipleOf(NF));
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TypeSize NewSize = OldLoc.getValue().divideCoefficientBy(NF);
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auto *NewMMO = MF.getMachineMemOperand(OldMMO, OldMMO->getOffset(), NewSize);
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for (unsigned I = 0; I < NF; ++I) {
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BuildMI(MBB, II, DL, TII->get(Opcode),
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TRI->getSubReg(DestReg, SubRegIdx + I))
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.addReg(Base, getKillRegState(I == NF - 1))
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.addMemOperand(NewMMO);
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if (I != NF - 1)
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BuildMI(MBB, II, DL, TII->get(RISCV::ADD), NewBase)
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.addReg(Base, getKillRegState(I != 0 || IsBaseKill))
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.addReg(VL, getKillRegState(I == NF - 2));
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Base = NewBase;
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PreHandledNum = RegNumHandled;
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RegEncoding += RegNumHandled;
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I += RegNumHandled;
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}
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II->eraseFromParent();
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}
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@ -635,9 +578,7 @@ bool RISCVRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
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}
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// Handle spill/fill of synthetic register classes for segment operations to
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// ensure correctness in the edge case one gets spilled. There are many
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// possible optimizations here, but given the extreme rarity of such spills,
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// we prefer simplicity of implementation for now.
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// ensure correctness in the edge case one gets spilled.
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switch (MI.getOpcode()) {
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case RISCV::PseudoVSPILL2_M1:
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case RISCV::PseudoVSPILL2_M2:
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@ -650,7 +591,7 @@ bool RISCVRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
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case RISCV::PseudoVSPILL6_M1:
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case RISCV::PseudoVSPILL7_M1:
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case RISCV::PseudoVSPILL8_M1:
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lowerVSPILL(II);
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lowerSegmentSpillReload(II, /*IsSpill=*/true);
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return true;
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case RISCV::PseudoVRELOAD2_M1:
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case RISCV::PseudoVRELOAD2_M2:
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@ -663,7 +604,7 @@ bool RISCVRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
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case RISCV::PseudoVRELOAD6_M1:
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case RISCV::PseudoVRELOAD7_M1:
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case RISCV::PseudoVRELOAD8_M1:
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lowerVRELOAD(II);
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lowerSegmentSpillReload(II, /*IsSpill=*/false);
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return true;
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}
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@ -1052,3 +993,12 @@ bool RISCVRegisterInfo::getRegAllocationHints(
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return BaseImplRetVal;
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}
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Register
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RISCVRegisterInfo::findVRegWithEncoding(const TargetRegisterClass &RegClass,
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uint16_t Encoding) const {
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MCRegister Reg = RISCV::V0 + Encoding;
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if (RISCVRI::getLMul(RegClass.TSFlags) == RISCVVType::LMUL_1)
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return Reg;
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return getMatchingSuperReg(Reg, RISCV::sub_vrm1_0, &RegClass);
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}
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@ -107,8 +107,8 @@ struct RISCVRegisterInfo : public RISCVGenRegisterInfo {
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int64_t getFrameIndexInstrOffset(const MachineInstr *MI,
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int Idx) const override;
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void lowerVSPILL(MachineBasicBlock::iterator II) const;
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void lowerVRELOAD(MachineBasicBlock::iterator II) const;
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void lowerSegmentSpillReload(MachineBasicBlock::iterator II,
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bool IsSpill) const;
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Register getFrameRegister(const MachineFunction &MF) const override;
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@ -144,6 +144,9 @@ struct RISCVRegisterInfo : public RISCVGenRegisterInfo {
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const MachineFunction &MF, const VirtRegMap *VRM,
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const LiveRegMatrix *Matrix) const override;
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Register findVRegWithEncoding(const TargetRegisterClass &RegClass,
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uint16_t Encoding) const;
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static bool isVRRegClass(const TargetRegisterClass *RC) {
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return RISCVRI::isVRegClass(RC->TSFlags) &&
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RISCVRI::getNF(RC->TSFlags) == 1;
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@ -40,15 +40,7 @@ define void @_Z3foov() {
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; CHECK-NEXT: addi a0, a0, %lo(.L__const._Z3foov.var_45)
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; CHECK-NEXT: vle16.v v12, (a0)
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; CHECK-NEXT: addi a0, sp, 16
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; CHECK-NEXT: csrr a1, vlenb
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; CHECK-NEXT: slli a1, a1, 1
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; CHECK-NEXT: vs2r.v v8, (a0) # vscale x 16-byte Folded Spill
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; CHECK-NEXT: add a0, a0, a1
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; CHECK-NEXT: vs2r.v v10, (a0) # vscale x 16-byte Folded Spill
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; CHECK-NEXT: add a0, a0, a1
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; CHECK-NEXT: vs2r.v v12, (a0) # vscale x 16-byte Folded Spill
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; CHECK-NEXT: add a0, a0, a1
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; CHECK-NEXT: vs2r.v v14, (a0) # vscale x 16-byte Folded Spill
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; CHECK-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
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; CHECK-NEXT: lui a0, %hi(.L__const._Z3foov.var_40)
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; CHECK-NEXT: addi a0, a0, %lo(.L__const._Z3foov.var_40)
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; CHECK-NEXT: #APP
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@ -59,15 +51,7 @@ define void @_Z3foov() {
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; CHECK-NEXT: addi a0, a0, 928
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; CHECK-NEXT: vmsbc.vx v0, v8, a0
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; CHECK-NEXT: addi a0, sp, 16
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; CHECK-NEXT: csrr a1, vlenb
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; CHECK-NEXT: slli a1, a1, 1
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; CHECK-NEXT: vl2r.v v8, (a0) # vscale x 16-byte Folded Reload
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; CHECK-NEXT: add a0, a0, a1
|
||||
; CHECK-NEXT: vl2r.v v10, (a0) # vscale x 16-byte Folded Reload
|
||||
; CHECK-NEXT: add a0, a0, a1
|
||||
; CHECK-NEXT: vl2r.v v12, (a0) # vscale x 16-byte Folded Reload
|
||||
; CHECK-NEXT: add a0, a0, a1
|
||||
; CHECK-NEXT: vl2r.v v14, (a0) # vscale x 16-byte Folded Reload
|
||||
; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
|
||||
; CHECK-NEXT: csrr a0, vlenb
|
||||
; CHECK-NEXT: slli a0, a0, 3
|
||||
; CHECK-NEXT: add a0, sp, a0
|
||||
|
||||
@ -32,11 +32,7 @@ define void @last_chance_recoloring_failure() {
|
||||
; CHECK-NEXT: slli a0, a0, 3
|
||||
; CHECK-NEXT: add a0, sp, a0
|
||||
; CHECK-NEXT: addi a0, a0, 16
|
||||
; CHECK-NEXT: csrr a1, vlenb
|
||||
; CHECK-NEXT: slli a1, a1, 2
|
||||
; CHECK-NEXT: vs4r.v v16, (a0) # vscale x 32-byte Folded Spill
|
||||
; CHECK-NEXT: add a0, a0, a1
|
||||
; CHECK-NEXT: vs4r.v v20, (a0) # vscale x 32-byte Folded Spill
|
||||
; CHECK-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
|
||||
; CHECK-NEXT: li s0, 36
|
||||
; CHECK-NEXT: vsetvli zero, s0, e16, m4, ta, ma
|
||||
; CHECK-NEXT: vfwadd.vv v16, v8, v12, v0.t
|
||||
@ -47,11 +43,7 @@ define void @last_chance_recoloring_failure() {
|
||||
; CHECK-NEXT: slli a0, a0, 3
|
||||
; CHECK-NEXT: add a0, sp, a0
|
||||
; CHECK-NEXT: addi a0, a0, 16
|
||||
; CHECK-NEXT: csrr a1, vlenb
|
||||
; CHECK-NEXT: slli a1, a1, 2
|
||||
; CHECK-NEXT: vl4r.v v16, (a0) # vscale x 32-byte Folded Reload
|
||||
; CHECK-NEXT: add a0, a0, a1
|
||||
; CHECK-NEXT: vl4r.v v20, (a0) # vscale x 32-byte Folded Reload
|
||||
; CHECK-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
|
||||
; CHECK-NEXT: addi a0, sp, 16
|
||||
; CHECK-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
|
||||
; CHECK-NEXT: vsetvli zero, s0, e16, m4, ta, ma
|
||||
@ -92,11 +84,7 @@ define void @last_chance_recoloring_failure() {
|
||||
; SUBREGLIVENESS-NEXT: slli a0, a0, 3
|
||||
; SUBREGLIVENESS-NEXT: add a0, sp, a0
|
||||
; SUBREGLIVENESS-NEXT: addi a0, a0, 16
|
||||
; SUBREGLIVENESS-NEXT: csrr a1, vlenb
|
||||
; SUBREGLIVENESS-NEXT: slli a1, a1, 2
|
||||
; SUBREGLIVENESS-NEXT: vs4r.v v16, (a0) # vscale x 32-byte Folded Spill
|
||||
; SUBREGLIVENESS-NEXT: add a0, a0, a1
|
||||
; SUBREGLIVENESS-NEXT: vs4r.v v20, (a0) # vscale x 32-byte Folded Spill
|
||||
; SUBREGLIVENESS-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
|
||||
; SUBREGLIVENESS-NEXT: li s0, 36
|
||||
; SUBREGLIVENESS-NEXT: vsetvli zero, s0, e16, m4, ta, ma
|
||||
; SUBREGLIVENESS-NEXT: vfwadd.vv v16, v8, v12, v0.t
|
||||
@ -107,11 +95,7 @@ define void @last_chance_recoloring_failure() {
|
||||
; SUBREGLIVENESS-NEXT: slli a0, a0, 3
|
||||
; SUBREGLIVENESS-NEXT: add a0, sp, a0
|
||||
; SUBREGLIVENESS-NEXT: addi a0, a0, 16
|
||||
; SUBREGLIVENESS-NEXT: csrr a1, vlenb
|
||||
; SUBREGLIVENESS-NEXT: slli a1, a1, 2
|
||||
; SUBREGLIVENESS-NEXT: vl4r.v v16, (a0) # vscale x 32-byte Folded Reload
|
||||
; SUBREGLIVENESS-NEXT: add a0, a0, a1
|
||||
; SUBREGLIVENESS-NEXT: vl4r.v v20, (a0) # vscale x 32-byte Folded Reload
|
||||
; SUBREGLIVENESS-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
|
||||
; SUBREGLIVENESS-NEXT: addi a0, sp, 16
|
||||
; SUBREGLIVENESS-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
|
||||
; SUBREGLIVENESS-NEXT: vsetvli zero, s0, e16, m4, ta, ma
|
||||
|
||||
@ -41,14 +41,11 @@ define <vscale x 1 x i32> @spill_zvlsseg_nxv1i32(ptr %base, i32 %vl) nounwind {
|
||||
; SPILL-O2-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
|
||||
; SPILL-O2-NEXT: vlseg2e32.v v8, (a0)
|
||||
; SPILL-O2-NEXT: addi a0, sp, 16
|
||||
; SPILL-O2-NEXT: csrr a1, vlenb
|
||||
; SPILL-O2-NEXT: vs1r.v v8, (a0) # vscale x 8-byte Folded Spill
|
||||
; SPILL-O2-NEXT: add a0, a0, a1
|
||||
; SPILL-O2-NEXT: vs1r.v v9, (a0) # vscale x 8-byte Folded Spill
|
||||
; SPILL-O2-NEXT: vs2r.v v8, (a0) # vscale x 16-byte Folded Spill
|
||||
; SPILL-O2-NEXT: #APP
|
||||
; SPILL-O2-NEXT: #NO_APP
|
||||
; SPILL-O2-NEXT: addi a0, sp, 16
|
||||
; SPILL-O2-NEXT: vl1r.v v7, (a0) # vscale x 8-byte Folded Reload
|
||||
; SPILL-O2-NEXT: csrr a1, vlenb
|
||||
; SPILL-O2-NEXT: add a0, a0, a1
|
||||
; SPILL-O2-NEXT: vl1r.v v8, (a0) # vscale x 8-byte Folded Reload
|
||||
; SPILL-O2-NEXT: csrr a0, vlenb
|
||||
@ -64,15 +61,11 @@ define <vscale x 1 x i32> @spill_zvlsseg_nxv1i32(ptr %base, i32 %vl) nounwind {
|
||||
; SPILL-O2-VLEN128-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
|
||||
; SPILL-O2-VLEN128-NEXT: vlseg2e32.v v8, (a0)
|
||||
; SPILL-O2-VLEN128-NEXT: addi a0, sp, 16
|
||||
; SPILL-O2-VLEN128-NEXT: li a1, 16
|
||||
; SPILL-O2-VLEN128-NEXT: vs1r.v v8, (a0) # vscale x 8-byte Folded Spill
|
||||
; SPILL-O2-VLEN128-NEXT: add a0, a0, a1
|
||||
; SPILL-O2-VLEN128-NEXT: vs1r.v v9, (a0) # vscale x 8-byte Folded Spill
|
||||
; SPILL-O2-VLEN128-NEXT: vs2r.v v8, (a0) # vscale x 16-byte Folded Spill
|
||||
; SPILL-O2-VLEN128-NEXT: #APP
|
||||
; SPILL-O2-VLEN128-NEXT: #NO_APP
|
||||
; SPILL-O2-VLEN128-NEXT: addi a0, sp, 16
|
||||
; SPILL-O2-VLEN128-NEXT: li a1, 16
|
||||
; SPILL-O2-VLEN128-NEXT: vl1r.v v7, (a0) # vscale x 8-byte Folded Reload
|
||||
; SPILL-O2-VLEN128-NEXT: li a1, 16
|
||||
; SPILL-O2-VLEN128-NEXT: add a0, a0, a1
|
||||
; SPILL-O2-VLEN128-NEXT: vl1r.v v8, (a0) # vscale x 8-byte Folded Reload
|
||||
; SPILL-O2-VLEN128-NEXT: addi sp, sp, 32
|
||||
@ -108,14 +101,11 @@ define <vscale x 1 x i32> @spill_zvlsseg_nxv1i32(ptr %base, i32 %vl) nounwind {
|
||||
; SPILL-O2-VSETVLI-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
|
||||
; SPILL-O2-VSETVLI-NEXT: vlseg2e32.v v8, (a0)
|
||||
; SPILL-O2-VSETVLI-NEXT: addi a0, sp, 16
|
||||
; SPILL-O2-VSETVLI-NEXT: csrr a1, vlenb
|
||||
; SPILL-O2-VSETVLI-NEXT: vs1r.v v8, (a0) # vscale x 8-byte Folded Spill
|
||||
; SPILL-O2-VSETVLI-NEXT: add a0, a0, a1
|
||||
; SPILL-O2-VSETVLI-NEXT: vs1r.v v9, (a0) # vscale x 8-byte Folded Spill
|
||||
; SPILL-O2-VSETVLI-NEXT: vs2r.v v8, (a0) # vscale x 16-byte Folded Spill
|
||||
; SPILL-O2-VSETVLI-NEXT: #APP
|
||||
; SPILL-O2-VSETVLI-NEXT: #NO_APP
|
||||
; SPILL-O2-VSETVLI-NEXT: addi a0, sp, 16
|
||||
; SPILL-O2-VSETVLI-NEXT: vl1r.v v7, (a0) # vscale x 8-byte Folded Reload
|
||||
; SPILL-O2-VSETVLI-NEXT: csrr a1, vlenb
|
||||
; SPILL-O2-VSETVLI-NEXT: add a0, a0, a1
|
||||
; SPILL-O2-VSETVLI-NEXT: vl1r.v v8, (a0) # vscale x 8-byte Folded Reload
|
||||
; SPILL-O2-VSETVLI-NEXT: vsetvli a0, zero, e8, m2, ta, ma
|
||||
@ -161,14 +151,11 @@ define <vscale x 2 x i32> @spill_zvlsseg_nxv2i32(ptr %base, i32 %vl) nounwind {
|
||||
; SPILL-O2-NEXT: vsetvli zero, a1, e32, m1, ta, ma
|
||||
; SPILL-O2-NEXT: vlseg2e32.v v8, (a0)
|
||||
; SPILL-O2-NEXT: addi a0, sp, 16
|
||||
; SPILL-O2-NEXT: csrr a1, vlenb
|
||||
; SPILL-O2-NEXT: vs1r.v v8, (a0) # vscale x 8-byte Folded Spill
|
||||
; SPILL-O2-NEXT: add a0, a0, a1
|
||||
; SPILL-O2-NEXT: vs1r.v v9, (a0) # vscale x 8-byte Folded Spill
|
||||
; SPILL-O2-NEXT: vs2r.v v8, (a0) # vscale x 16-byte Folded Spill
|
||||
; SPILL-O2-NEXT: #APP
|
||||
; SPILL-O2-NEXT: #NO_APP
|
||||
; SPILL-O2-NEXT: addi a0, sp, 16
|
||||
; SPILL-O2-NEXT: vl1r.v v7, (a0) # vscale x 8-byte Folded Reload
|
||||
; SPILL-O2-NEXT: csrr a1, vlenb
|
||||
; SPILL-O2-NEXT: add a0, a0, a1
|
||||
; SPILL-O2-NEXT: vl1r.v v8, (a0) # vscale x 8-byte Folded Reload
|
||||
; SPILL-O2-NEXT: csrr a0, vlenb
|
||||
@ -184,15 +171,11 @@ define <vscale x 2 x i32> @spill_zvlsseg_nxv2i32(ptr %base, i32 %vl) nounwind {
|
||||
; SPILL-O2-VLEN128-NEXT: vsetvli zero, a1, e32, m1, ta, ma
|
||||
; SPILL-O2-VLEN128-NEXT: vlseg2e32.v v8, (a0)
|
||||
; SPILL-O2-VLEN128-NEXT: addi a0, sp, 16
|
||||
; SPILL-O2-VLEN128-NEXT: li a1, 16
|
||||
; SPILL-O2-VLEN128-NEXT: vs1r.v v8, (a0) # vscale x 8-byte Folded Spill
|
||||
; SPILL-O2-VLEN128-NEXT: add a0, a0, a1
|
||||
; SPILL-O2-VLEN128-NEXT: vs1r.v v9, (a0) # vscale x 8-byte Folded Spill
|
||||
; SPILL-O2-VLEN128-NEXT: vs2r.v v8, (a0) # vscale x 16-byte Folded Spill
|
||||
; SPILL-O2-VLEN128-NEXT: #APP
|
||||
; SPILL-O2-VLEN128-NEXT: #NO_APP
|
||||
; SPILL-O2-VLEN128-NEXT: addi a0, sp, 16
|
||||
; SPILL-O2-VLEN128-NEXT: li a1, 16
|
||||
; SPILL-O2-VLEN128-NEXT: vl1r.v v7, (a0) # vscale x 8-byte Folded Reload
|
||||
; SPILL-O2-VLEN128-NEXT: li a1, 16
|
||||
; SPILL-O2-VLEN128-NEXT: add a0, a0, a1
|
||||
; SPILL-O2-VLEN128-NEXT: vl1r.v v8, (a0) # vscale x 8-byte Folded Reload
|
||||
; SPILL-O2-VLEN128-NEXT: addi sp, sp, 32
|
||||
@ -228,14 +211,11 @@ define <vscale x 2 x i32> @spill_zvlsseg_nxv2i32(ptr %base, i32 %vl) nounwind {
|
||||
; SPILL-O2-VSETVLI-NEXT: vsetvli zero, a1, e32, m1, ta, ma
|
||||
; SPILL-O2-VSETVLI-NEXT: vlseg2e32.v v8, (a0)
|
||||
; SPILL-O2-VSETVLI-NEXT: addi a0, sp, 16
|
||||
; SPILL-O2-VSETVLI-NEXT: csrr a1, vlenb
|
||||
; SPILL-O2-VSETVLI-NEXT: vs1r.v v8, (a0) # vscale x 8-byte Folded Spill
|
||||
; SPILL-O2-VSETVLI-NEXT: add a0, a0, a1
|
||||
; SPILL-O2-VSETVLI-NEXT: vs1r.v v9, (a0) # vscale x 8-byte Folded Spill
|
||||
; SPILL-O2-VSETVLI-NEXT: vs2r.v v8, (a0) # vscale x 16-byte Folded Spill
|
||||
; SPILL-O2-VSETVLI-NEXT: #APP
|
||||
; SPILL-O2-VSETVLI-NEXT: #NO_APP
|
||||
; SPILL-O2-VSETVLI-NEXT: addi a0, sp, 16
|
||||
; SPILL-O2-VSETVLI-NEXT: vl1r.v v7, (a0) # vscale x 8-byte Folded Reload
|
||||
; SPILL-O2-VSETVLI-NEXT: csrr a1, vlenb
|
||||
; SPILL-O2-VSETVLI-NEXT: add a0, a0, a1
|
||||
; SPILL-O2-VSETVLI-NEXT: vl1r.v v8, (a0) # vscale x 8-byte Folded Reload
|
||||
; SPILL-O2-VSETVLI-NEXT: vsetvli a0, zero, e8, m2, ta, ma
|
||||
@ -283,17 +263,12 @@ define <vscale x 4 x i32> @spill_zvlsseg_nxv4i32(ptr %base, i32 %vl) nounwind {
|
||||
; SPILL-O2-NEXT: vsetvli zero, a1, e32, m2, ta, ma
|
||||
; SPILL-O2-NEXT: vlseg2e32.v v8, (a0)
|
||||
; SPILL-O2-NEXT: addi a0, sp, 16
|
||||
; SPILL-O2-NEXT: csrr a1, vlenb
|
||||
; SPILL-O2-NEXT: slli a1, a1, 1
|
||||
; SPILL-O2-NEXT: vs2r.v v8, (a0) # vscale x 16-byte Folded Spill
|
||||
; SPILL-O2-NEXT: add a0, a0, a1
|
||||
; SPILL-O2-NEXT: vs2r.v v10, (a0) # vscale x 16-byte Folded Spill
|
||||
; SPILL-O2-NEXT: vs4r.v v8, (a0) # vscale x 32-byte Folded Spill
|
||||
; SPILL-O2-NEXT: #APP
|
||||
; SPILL-O2-NEXT: #NO_APP
|
||||
; SPILL-O2-NEXT: addi a0, sp, 16
|
||||
; SPILL-O2-NEXT: vl2r.v v6, (a0) # vscale x 16-byte Folded Reload
|
||||
; SPILL-O2-NEXT: csrr a1, vlenb
|
||||
; SPILL-O2-NEXT: slli a1, a1, 1
|
||||
; SPILL-O2-NEXT: vl2r.v v6, (a0) # vscale x 16-byte Folded Reload
|
||||
; SPILL-O2-NEXT: add a0, a0, a1
|
||||
; SPILL-O2-NEXT: vl2r.v v8, (a0) # vscale x 16-byte Folded Reload
|
||||
; SPILL-O2-NEXT: csrr a0, vlenb
|
||||
@ -309,15 +284,11 @@ define <vscale x 4 x i32> @spill_zvlsseg_nxv4i32(ptr %base, i32 %vl) nounwind {
|
||||
; SPILL-O2-VLEN128-NEXT: vsetvli zero, a1, e32, m2, ta, ma
|
||||
; SPILL-O2-VLEN128-NEXT: vlseg2e32.v v8, (a0)
|
||||
; SPILL-O2-VLEN128-NEXT: addi a0, sp, 16
|
||||
; SPILL-O2-VLEN128-NEXT: li a1, 32
|
||||
; SPILL-O2-VLEN128-NEXT: vs2r.v v8, (a0) # vscale x 16-byte Folded Spill
|
||||
; SPILL-O2-VLEN128-NEXT: add a0, a0, a1
|
||||
; SPILL-O2-VLEN128-NEXT: vs2r.v v10, (a0) # vscale x 16-byte Folded Spill
|
||||
; SPILL-O2-VLEN128-NEXT: vs4r.v v8, (a0) # vscale x 32-byte Folded Spill
|
||||
; SPILL-O2-VLEN128-NEXT: #APP
|
||||
; SPILL-O2-VLEN128-NEXT: #NO_APP
|
||||
; SPILL-O2-VLEN128-NEXT: addi a0, sp, 16
|
||||
; SPILL-O2-VLEN128-NEXT: li a1, 32
|
||||
; SPILL-O2-VLEN128-NEXT: vl2r.v v6, (a0) # vscale x 16-byte Folded Reload
|
||||
; SPILL-O2-VLEN128-NEXT: li a1, 32
|
||||
; SPILL-O2-VLEN128-NEXT: add a0, a0, a1
|
||||
; SPILL-O2-VLEN128-NEXT: vl2r.v v8, (a0) # vscale x 16-byte Folded Reload
|
||||
; SPILL-O2-VLEN128-NEXT: addi sp, sp, 64
|
||||
@ -353,17 +324,12 @@ define <vscale x 4 x i32> @spill_zvlsseg_nxv4i32(ptr %base, i32 %vl) nounwind {
|
||||
; SPILL-O2-VSETVLI-NEXT: vsetvli zero, a1, e32, m2, ta, ma
|
||||
; SPILL-O2-VSETVLI-NEXT: vlseg2e32.v v8, (a0)
|
||||
; SPILL-O2-VSETVLI-NEXT: addi a0, sp, 16
|
||||
; SPILL-O2-VSETVLI-NEXT: csrr a1, vlenb
|
||||
; SPILL-O2-VSETVLI-NEXT: slli a1, a1, 1
|
||||
; SPILL-O2-VSETVLI-NEXT: vs2r.v v8, (a0) # vscale x 16-byte Folded Spill
|
||||
; SPILL-O2-VSETVLI-NEXT: add a0, a0, a1
|
||||
; SPILL-O2-VSETVLI-NEXT: vs2r.v v10, (a0) # vscale x 16-byte Folded Spill
|
||||
; SPILL-O2-VSETVLI-NEXT: vs4r.v v8, (a0) # vscale x 32-byte Folded Spill
|
||||
; SPILL-O2-VSETVLI-NEXT: #APP
|
||||
; SPILL-O2-VSETVLI-NEXT: #NO_APP
|
||||
; SPILL-O2-VSETVLI-NEXT: addi a0, sp, 16
|
||||
; SPILL-O2-VSETVLI-NEXT: vl2r.v v6, (a0) # vscale x 16-byte Folded Reload
|
||||
; SPILL-O2-VSETVLI-NEXT: csrr a1, vlenb
|
||||
; SPILL-O2-VSETVLI-NEXT: slli a1, a1, 1
|
||||
; SPILL-O2-VSETVLI-NEXT: vl2r.v v6, (a0) # vscale x 16-byte Folded Reload
|
||||
; SPILL-O2-VSETVLI-NEXT: add a0, a0, a1
|
||||
; SPILL-O2-VSETVLI-NEXT: vl2r.v v8, (a0) # vscale x 16-byte Folded Reload
|
||||
; SPILL-O2-VSETVLI-NEXT: vsetvli a0, zero, e8, m4, ta, ma
|
||||
@ -411,17 +377,12 @@ define <vscale x 8 x i32> @spill_zvlsseg_nxv8i32(ptr %base, i32 %vl) nounwind {
|
||||
; SPILL-O2-NEXT: vsetvli zero, a1, e32, m4, ta, ma
|
||||
; SPILL-O2-NEXT: vlseg2e32.v v8, (a0)
|
||||
; SPILL-O2-NEXT: addi a0, sp, 16
|
||||
; SPILL-O2-NEXT: csrr a1, vlenb
|
||||
; SPILL-O2-NEXT: slli a1, a1, 2
|
||||
; SPILL-O2-NEXT: vs4r.v v8, (a0) # vscale x 32-byte Folded Spill
|
||||
; SPILL-O2-NEXT: add a0, a0, a1
|
||||
; SPILL-O2-NEXT: vs4r.v v12, (a0) # vscale x 32-byte Folded Spill
|
||||
; SPILL-O2-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
|
||||
; SPILL-O2-NEXT: #APP
|
||||
; SPILL-O2-NEXT: #NO_APP
|
||||
; SPILL-O2-NEXT: addi a0, sp, 16
|
||||
; SPILL-O2-NEXT: vl4r.v v4, (a0) # vscale x 32-byte Folded Reload
|
||||
; SPILL-O2-NEXT: csrr a1, vlenb
|
||||
; SPILL-O2-NEXT: slli a1, a1, 2
|
||||
; SPILL-O2-NEXT: vl4r.v v4, (a0) # vscale x 32-byte Folded Reload
|
||||
; SPILL-O2-NEXT: add a0, a0, a1
|
||||
; SPILL-O2-NEXT: vl4r.v v8, (a0) # vscale x 32-byte Folded Reload
|
||||
; SPILL-O2-NEXT: csrr a0, vlenb
|
||||
@ -437,15 +398,11 @@ define <vscale x 8 x i32> @spill_zvlsseg_nxv8i32(ptr %base, i32 %vl) nounwind {
|
||||
; SPILL-O2-VLEN128-NEXT: vsetvli zero, a1, e32, m4, ta, ma
|
||||
; SPILL-O2-VLEN128-NEXT: vlseg2e32.v v8, (a0)
|
||||
; SPILL-O2-VLEN128-NEXT: addi a0, sp, 16
|
||||
; SPILL-O2-VLEN128-NEXT: li a1, 64
|
||||
; SPILL-O2-VLEN128-NEXT: vs4r.v v8, (a0) # vscale x 32-byte Folded Spill
|
||||
; SPILL-O2-VLEN128-NEXT: add a0, a0, a1
|
||||
; SPILL-O2-VLEN128-NEXT: vs4r.v v12, (a0) # vscale x 32-byte Folded Spill
|
||||
; SPILL-O2-VLEN128-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
|
||||
; SPILL-O2-VLEN128-NEXT: #APP
|
||||
; SPILL-O2-VLEN128-NEXT: #NO_APP
|
||||
; SPILL-O2-VLEN128-NEXT: addi a0, sp, 16
|
||||
; SPILL-O2-VLEN128-NEXT: li a1, 64
|
||||
; SPILL-O2-VLEN128-NEXT: vl4r.v v4, (a0) # vscale x 32-byte Folded Reload
|
||||
; SPILL-O2-VLEN128-NEXT: li a1, 64
|
||||
; SPILL-O2-VLEN128-NEXT: add a0, a0, a1
|
||||
; SPILL-O2-VLEN128-NEXT: vl4r.v v8, (a0) # vscale x 32-byte Folded Reload
|
||||
; SPILL-O2-VLEN128-NEXT: addi sp, sp, 128
|
||||
@ -481,17 +438,12 @@ define <vscale x 8 x i32> @spill_zvlsseg_nxv8i32(ptr %base, i32 %vl) nounwind {
|
||||
; SPILL-O2-VSETVLI-NEXT: vsetvli zero, a1, e32, m4, ta, ma
|
||||
; SPILL-O2-VSETVLI-NEXT: vlseg2e32.v v8, (a0)
|
||||
; SPILL-O2-VSETVLI-NEXT: addi a0, sp, 16
|
||||
; SPILL-O2-VSETVLI-NEXT: csrr a1, vlenb
|
||||
; SPILL-O2-VSETVLI-NEXT: slli a1, a1, 2
|
||||
; SPILL-O2-VSETVLI-NEXT: vs4r.v v8, (a0) # vscale x 32-byte Folded Spill
|
||||
; SPILL-O2-VSETVLI-NEXT: add a0, a0, a1
|
||||
; SPILL-O2-VSETVLI-NEXT: vs4r.v v12, (a0) # vscale x 32-byte Folded Spill
|
||||
; SPILL-O2-VSETVLI-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
|
||||
; SPILL-O2-VSETVLI-NEXT: #APP
|
||||
; SPILL-O2-VSETVLI-NEXT: #NO_APP
|
||||
; SPILL-O2-VSETVLI-NEXT: addi a0, sp, 16
|
||||
; SPILL-O2-VSETVLI-NEXT: vl4r.v v4, (a0) # vscale x 32-byte Folded Reload
|
||||
; SPILL-O2-VSETVLI-NEXT: csrr a1, vlenb
|
||||
; SPILL-O2-VSETVLI-NEXT: slli a1, a1, 2
|
||||
; SPILL-O2-VSETVLI-NEXT: vl4r.v v4, (a0) # vscale x 32-byte Folded Reload
|
||||
; SPILL-O2-VSETVLI-NEXT: add a0, a0, a1
|
||||
; SPILL-O2-VSETVLI-NEXT: vl4r.v v8, (a0) # vscale x 32-byte Folded Reload
|
||||
; SPILL-O2-VSETVLI-NEXT: vsetvli a0, zero, e8, m8, ta, ma
|
||||
@ -540,23 +492,19 @@ define <vscale x 4 x i32> @spill_zvlsseg3_nxv4i32(ptr %base, i32 %vl) nounwind {
|
||||
; SPILL-O2-NEXT: vsetvli zero, a1, e32, m2, ta, ma
|
||||
; SPILL-O2-NEXT: vlseg3e32.v v8, (a0)
|
||||
; SPILL-O2-NEXT: addi a0, sp, 16
|
||||
; SPILL-O2-NEXT: vs4r.v v8, (a0) # vscale x 32-byte Folded Spill
|
||||
; SPILL-O2-NEXT: csrr a1, vlenb
|
||||
; SPILL-O2-NEXT: slli a1, a1, 1
|
||||
; SPILL-O2-NEXT: vs2r.v v8, (a0) # vscale x 16-byte Folded Spill
|
||||
; SPILL-O2-NEXT: add a0, a0, a1
|
||||
; SPILL-O2-NEXT: vs2r.v v10, (a0) # vscale x 16-byte Folded Spill
|
||||
; SPILL-O2-NEXT: slli a1, a1, 2
|
||||
; SPILL-O2-NEXT: add a0, a0, a1
|
||||
; SPILL-O2-NEXT: vs2r.v v12, (a0) # vscale x 16-byte Folded Spill
|
||||
; SPILL-O2-NEXT: #APP
|
||||
; SPILL-O2-NEXT: #NO_APP
|
||||
; SPILL-O2-NEXT: addi a0, sp, 16
|
||||
; SPILL-O2-NEXT: vl2r.v v6, (a0) # vscale x 16-byte Folded Reload
|
||||
; SPILL-O2-NEXT: csrr a1, vlenb
|
||||
; SPILL-O2-NEXT: slli a1, a1, 1
|
||||
; SPILL-O2-NEXT: vl2r.v v6, (a0) # vscale x 16-byte Folded Reload
|
||||
; SPILL-O2-NEXT: add a0, a0, a1
|
||||
; SPILL-O2-NEXT: vl2r.v v8, (a0) # vscale x 16-byte Folded Reload
|
||||
; SPILL-O2-NEXT: add a0, a0, a1
|
||||
; SPILL-O2-NEXT: vl2r.v v10, (a0) # vscale x 16-byte Folded Reload
|
||||
; SPILL-O2-NEXT: vl4r.v v8, (a0) # vscale x 32-byte Folded Reload
|
||||
; SPILL-O2-NEXT: csrr a0, vlenb
|
||||
; SPILL-O2-NEXT: li a1, 6
|
||||
; SPILL-O2-NEXT: mul a0, a0, a1
|
||||
@ -571,21 +519,17 @@ define <vscale x 4 x i32> @spill_zvlsseg3_nxv4i32(ptr %base, i32 %vl) nounwind {
|
||||
; SPILL-O2-VLEN128-NEXT: vsetvli zero, a1, e32, m2, ta, ma
|
||||
; SPILL-O2-VLEN128-NEXT: vlseg3e32.v v8, (a0)
|
||||
; SPILL-O2-VLEN128-NEXT: addi a0, sp, 16
|
||||
; SPILL-O2-VLEN128-NEXT: li a1, 32
|
||||
; SPILL-O2-VLEN128-NEXT: vs2r.v v8, (a0) # vscale x 16-byte Folded Spill
|
||||
; SPILL-O2-VLEN128-NEXT: add a0, a0, a1
|
||||
; SPILL-O2-VLEN128-NEXT: vs2r.v v10, (a0) # vscale x 16-byte Folded Spill
|
||||
; SPILL-O2-VLEN128-NEXT: vs4r.v v8, (a0) # vscale x 32-byte Folded Spill
|
||||
; SPILL-O2-VLEN128-NEXT: li a1, 64
|
||||
; SPILL-O2-VLEN128-NEXT: add a0, a0, a1
|
||||
; SPILL-O2-VLEN128-NEXT: vs2r.v v12, (a0) # vscale x 16-byte Folded Spill
|
||||
; SPILL-O2-VLEN128-NEXT: #APP
|
||||
; SPILL-O2-VLEN128-NEXT: #NO_APP
|
||||
; SPILL-O2-VLEN128-NEXT: addi a0, sp, 16
|
||||
; SPILL-O2-VLEN128-NEXT: li a1, 32
|
||||
; SPILL-O2-VLEN128-NEXT: vl2r.v v6, (a0) # vscale x 16-byte Folded Reload
|
||||
; SPILL-O2-VLEN128-NEXT: li a1, 32
|
||||
; SPILL-O2-VLEN128-NEXT: add a0, a0, a1
|
||||
; SPILL-O2-VLEN128-NEXT: vl2r.v v8, (a0) # vscale x 16-byte Folded Reload
|
||||
; SPILL-O2-VLEN128-NEXT: add a0, a0, a1
|
||||
; SPILL-O2-VLEN128-NEXT: vl2r.v v10, (a0) # vscale x 16-byte Folded Reload
|
||||
; SPILL-O2-VLEN128-NEXT: vl4r.v v8, (a0) # vscale x 32-byte Folded Reload
|
||||
; SPILL-O2-VLEN128-NEXT: addi sp, sp, 96
|
||||
; SPILL-O2-VLEN128-NEXT: addi sp, sp, 16
|
||||
; SPILL-O2-VLEN128-NEXT: ret
|
||||
@ -621,23 +565,19 @@ define <vscale x 4 x i32> @spill_zvlsseg3_nxv4i32(ptr %base, i32 %vl) nounwind {
|
||||
; SPILL-O2-VSETVLI-NEXT: vsetvli zero, a1, e32, m2, ta, ma
|
||||
; SPILL-O2-VSETVLI-NEXT: vlseg3e32.v v8, (a0)
|
||||
; SPILL-O2-VSETVLI-NEXT: addi a0, sp, 16
|
||||
; SPILL-O2-VSETVLI-NEXT: vs4r.v v8, (a0) # vscale x 32-byte Folded Spill
|
||||
; SPILL-O2-VSETVLI-NEXT: csrr a1, vlenb
|
||||
; SPILL-O2-VSETVLI-NEXT: slli a1, a1, 1
|
||||
; SPILL-O2-VSETVLI-NEXT: vs2r.v v8, (a0) # vscale x 16-byte Folded Spill
|
||||
; SPILL-O2-VSETVLI-NEXT: add a0, a0, a1
|
||||
; SPILL-O2-VSETVLI-NEXT: vs2r.v v10, (a0) # vscale x 16-byte Folded Spill
|
||||
; SPILL-O2-VSETVLI-NEXT: slli a1, a1, 2
|
||||
; SPILL-O2-VSETVLI-NEXT: add a0, a0, a1
|
||||
; SPILL-O2-VSETVLI-NEXT: vs2r.v v12, (a0) # vscale x 16-byte Folded Spill
|
||||
; SPILL-O2-VSETVLI-NEXT: #APP
|
||||
; SPILL-O2-VSETVLI-NEXT: #NO_APP
|
||||
; SPILL-O2-VSETVLI-NEXT: addi a0, sp, 16
|
||||
; SPILL-O2-VSETVLI-NEXT: vl2r.v v6, (a0) # vscale x 16-byte Folded Reload
|
||||
; SPILL-O2-VSETVLI-NEXT: csrr a1, vlenb
|
||||
; SPILL-O2-VSETVLI-NEXT: slli a1, a1, 1
|
||||
; SPILL-O2-VSETVLI-NEXT: vl2r.v v6, (a0) # vscale x 16-byte Folded Reload
|
||||
; SPILL-O2-VSETVLI-NEXT: add a0, a0, a1
|
||||
; SPILL-O2-VSETVLI-NEXT: vl2r.v v8, (a0) # vscale x 16-byte Folded Reload
|
||||
; SPILL-O2-VSETVLI-NEXT: add a0, a0, a1
|
||||
; SPILL-O2-VSETVLI-NEXT: vl2r.v v10, (a0) # vscale x 16-byte Folded Reload
|
||||
; SPILL-O2-VSETVLI-NEXT: vl4r.v v8, (a0) # vscale x 32-byte Folded Reload
|
||||
; SPILL-O2-VSETVLI-NEXT: vsetvli a0, zero, e8, m1, ta, ma
|
||||
; SPILL-O2-VSETVLI-NEXT: li a1, 6
|
||||
; SPILL-O2-VSETVLI-NEXT: mul a0, a0, a1
|
||||
|
||||
@ -41,14 +41,11 @@ define <vscale x 1 x i32> @spill_zvlsseg_nxv1i32(ptr %base, i64 %vl) nounwind {
|
||||
; SPILL-O2-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
|
||||
; SPILL-O2-NEXT: vlseg2e32.v v8, (a0)
|
||||
; SPILL-O2-NEXT: addi a0, sp, 16
|
||||
; SPILL-O2-NEXT: csrr a1, vlenb
|
||||
; SPILL-O2-NEXT: vs1r.v v8, (a0) # vscale x 8-byte Folded Spill
|
||||
; SPILL-O2-NEXT: add a0, a0, a1
|
||||
; SPILL-O2-NEXT: vs1r.v v9, (a0) # vscale x 8-byte Folded Spill
|
||||
; SPILL-O2-NEXT: vs2r.v v8, (a0) # vscale x 16-byte Folded Spill
|
||||
; SPILL-O2-NEXT: #APP
|
||||
; SPILL-O2-NEXT: #NO_APP
|
||||
; SPILL-O2-NEXT: addi a0, sp, 16
|
||||
; SPILL-O2-NEXT: vl1r.v v7, (a0) # vscale x 8-byte Folded Reload
|
||||
; SPILL-O2-NEXT: csrr a1, vlenb
|
||||
; SPILL-O2-NEXT: add a0, a0, a1
|
||||
; SPILL-O2-NEXT: vl1r.v v8, (a0) # vscale x 8-byte Folded Reload
|
||||
; SPILL-O2-NEXT: csrr a0, vlenb
|
||||
@ -64,15 +61,11 @@ define <vscale x 1 x i32> @spill_zvlsseg_nxv1i32(ptr %base, i64 %vl) nounwind {
|
||||
; SPILL-O2-VLEN128-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
|
||||
; SPILL-O2-VLEN128-NEXT: vlseg2e32.v v8, (a0)
|
||||
; SPILL-O2-VLEN128-NEXT: addi a0, sp, 16
|
||||
; SPILL-O2-VLEN128-NEXT: li a1, 16
|
||||
; SPILL-O2-VLEN128-NEXT: vs1r.v v8, (a0) # vscale x 8-byte Folded Spill
|
||||
; SPILL-O2-VLEN128-NEXT: add a0, a0, a1
|
||||
; SPILL-O2-VLEN128-NEXT: vs1r.v v9, (a0) # vscale x 8-byte Folded Spill
|
||||
; SPILL-O2-VLEN128-NEXT: vs2r.v v8, (a0) # vscale x 16-byte Folded Spill
|
||||
; SPILL-O2-VLEN128-NEXT: #APP
|
||||
; SPILL-O2-VLEN128-NEXT: #NO_APP
|
||||
; SPILL-O2-VLEN128-NEXT: addi a0, sp, 16
|
||||
; SPILL-O2-VLEN128-NEXT: li a1, 16
|
||||
; SPILL-O2-VLEN128-NEXT: vl1r.v v7, (a0) # vscale x 8-byte Folded Reload
|
||||
; SPILL-O2-VLEN128-NEXT: li a1, 16
|
||||
; SPILL-O2-VLEN128-NEXT: add a0, a0, a1
|
||||
; SPILL-O2-VLEN128-NEXT: vl1r.v v8, (a0) # vscale x 8-byte Folded Reload
|
||||
; SPILL-O2-VLEN128-NEXT: addi sp, sp, 32
|
||||
@ -108,14 +101,11 @@ define <vscale x 1 x i32> @spill_zvlsseg_nxv1i32(ptr %base, i64 %vl) nounwind {
|
||||
; SPILL-O2-VSETVLI-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
|
||||
; SPILL-O2-VSETVLI-NEXT: vlseg2e32.v v8, (a0)
|
||||
; SPILL-O2-VSETVLI-NEXT: addi a0, sp, 16
|
||||
; SPILL-O2-VSETVLI-NEXT: csrr a1, vlenb
|
||||
; SPILL-O2-VSETVLI-NEXT: vs1r.v v8, (a0) # vscale x 8-byte Folded Spill
|
||||
; SPILL-O2-VSETVLI-NEXT: add a0, a0, a1
|
||||
; SPILL-O2-VSETVLI-NEXT: vs1r.v v9, (a0) # vscale x 8-byte Folded Spill
|
||||
; SPILL-O2-VSETVLI-NEXT: vs2r.v v8, (a0) # vscale x 16-byte Folded Spill
|
||||
; SPILL-O2-VSETVLI-NEXT: #APP
|
||||
; SPILL-O2-VSETVLI-NEXT: #NO_APP
|
||||
; SPILL-O2-VSETVLI-NEXT: addi a0, sp, 16
|
||||
; SPILL-O2-VSETVLI-NEXT: vl1r.v v7, (a0) # vscale x 8-byte Folded Reload
|
||||
; SPILL-O2-VSETVLI-NEXT: csrr a1, vlenb
|
||||
; SPILL-O2-VSETVLI-NEXT: add a0, a0, a1
|
||||
; SPILL-O2-VSETVLI-NEXT: vl1r.v v8, (a0) # vscale x 8-byte Folded Reload
|
||||
; SPILL-O2-VSETVLI-NEXT: vsetvli a0, zero, e8, m2, ta, ma
|
||||
@ -161,14 +151,11 @@ define <vscale x 2 x i32> @spill_zvlsseg_nxv2i32(ptr %base, i64 %vl) nounwind {
|
||||
; SPILL-O2-NEXT: vsetvli zero, a1, e32, m1, ta, ma
|
||||
; SPILL-O2-NEXT: vlseg2e32.v v8, (a0)
|
||||
; SPILL-O2-NEXT: addi a0, sp, 16
|
||||
; SPILL-O2-NEXT: csrr a1, vlenb
|
||||
; SPILL-O2-NEXT: vs1r.v v8, (a0) # vscale x 8-byte Folded Spill
|
||||
; SPILL-O2-NEXT: add a0, a0, a1
|
||||
; SPILL-O2-NEXT: vs1r.v v9, (a0) # vscale x 8-byte Folded Spill
|
||||
; SPILL-O2-NEXT: vs2r.v v8, (a0) # vscale x 16-byte Folded Spill
|
||||
; SPILL-O2-NEXT: #APP
|
||||
; SPILL-O2-NEXT: #NO_APP
|
||||
; SPILL-O2-NEXT: addi a0, sp, 16
|
||||
; SPILL-O2-NEXT: vl1r.v v7, (a0) # vscale x 8-byte Folded Reload
|
||||
; SPILL-O2-NEXT: csrr a1, vlenb
|
||||
; SPILL-O2-NEXT: add a0, a0, a1
|
||||
; SPILL-O2-NEXT: vl1r.v v8, (a0) # vscale x 8-byte Folded Reload
|
||||
; SPILL-O2-NEXT: csrr a0, vlenb
|
||||
@ -184,15 +171,11 @@ define <vscale x 2 x i32> @spill_zvlsseg_nxv2i32(ptr %base, i64 %vl) nounwind {
|
||||
; SPILL-O2-VLEN128-NEXT: vsetvli zero, a1, e32, m1, ta, ma
|
||||
; SPILL-O2-VLEN128-NEXT: vlseg2e32.v v8, (a0)
|
||||
; SPILL-O2-VLEN128-NEXT: addi a0, sp, 16
|
||||
; SPILL-O2-VLEN128-NEXT: li a1, 16
|
||||
; SPILL-O2-VLEN128-NEXT: vs1r.v v8, (a0) # vscale x 8-byte Folded Spill
|
||||
; SPILL-O2-VLEN128-NEXT: add a0, a0, a1
|
||||
; SPILL-O2-VLEN128-NEXT: vs1r.v v9, (a0) # vscale x 8-byte Folded Spill
|
||||
; SPILL-O2-VLEN128-NEXT: vs2r.v v8, (a0) # vscale x 16-byte Folded Spill
|
||||
; SPILL-O2-VLEN128-NEXT: #APP
|
||||
; SPILL-O2-VLEN128-NEXT: #NO_APP
|
||||
; SPILL-O2-VLEN128-NEXT: addi a0, sp, 16
|
||||
; SPILL-O2-VLEN128-NEXT: li a1, 16
|
||||
; SPILL-O2-VLEN128-NEXT: vl1r.v v7, (a0) # vscale x 8-byte Folded Reload
|
||||
; SPILL-O2-VLEN128-NEXT: li a1, 16
|
||||
; SPILL-O2-VLEN128-NEXT: add a0, a0, a1
|
||||
; SPILL-O2-VLEN128-NEXT: vl1r.v v8, (a0) # vscale x 8-byte Folded Reload
|
||||
; SPILL-O2-VLEN128-NEXT: addi sp, sp, 32
|
||||
@ -228,14 +211,11 @@ define <vscale x 2 x i32> @spill_zvlsseg_nxv2i32(ptr %base, i64 %vl) nounwind {
|
||||
; SPILL-O2-VSETVLI-NEXT: vsetvli zero, a1, e32, m1, ta, ma
|
||||
; SPILL-O2-VSETVLI-NEXT: vlseg2e32.v v8, (a0)
|
||||
; SPILL-O2-VSETVLI-NEXT: addi a0, sp, 16
|
||||
; SPILL-O2-VSETVLI-NEXT: csrr a1, vlenb
|
||||
; SPILL-O2-VSETVLI-NEXT: vs1r.v v8, (a0) # vscale x 8-byte Folded Spill
|
||||
; SPILL-O2-VSETVLI-NEXT: add a0, a0, a1
|
||||
; SPILL-O2-VSETVLI-NEXT: vs1r.v v9, (a0) # vscale x 8-byte Folded Spill
|
||||
; SPILL-O2-VSETVLI-NEXT: vs2r.v v8, (a0) # vscale x 16-byte Folded Spill
|
||||
; SPILL-O2-VSETVLI-NEXT: #APP
|
||||
; SPILL-O2-VSETVLI-NEXT: #NO_APP
|
||||
; SPILL-O2-VSETVLI-NEXT: addi a0, sp, 16
|
||||
; SPILL-O2-VSETVLI-NEXT: vl1r.v v7, (a0) # vscale x 8-byte Folded Reload
|
||||
; SPILL-O2-VSETVLI-NEXT: csrr a1, vlenb
|
||||
; SPILL-O2-VSETVLI-NEXT: add a0, a0, a1
|
||||
; SPILL-O2-VSETVLI-NEXT: vl1r.v v8, (a0) # vscale x 8-byte Folded Reload
|
||||
; SPILL-O2-VSETVLI-NEXT: vsetvli a0, zero, e8, m2, ta, ma
|
||||
@ -283,17 +263,12 @@ define <vscale x 4 x i32> @spill_zvlsseg_nxv4i32(ptr %base, i64 %vl) nounwind {
|
||||
; SPILL-O2-NEXT: vsetvli zero, a1, e32, m2, ta, ma
|
||||
; SPILL-O2-NEXT: vlseg2e32.v v8, (a0)
|
||||
; SPILL-O2-NEXT: addi a0, sp, 16
|
||||
; SPILL-O2-NEXT: csrr a1, vlenb
|
||||
; SPILL-O2-NEXT: slli a1, a1, 1
|
||||
; SPILL-O2-NEXT: vs2r.v v8, (a0) # vscale x 16-byte Folded Spill
|
||||
; SPILL-O2-NEXT: add a0, a0, a1
|
||||
; SPILL-O2-NEXT: vs2r.v v10, (a0) # vscale x 16-byte Folded Spill
|
||||
; SPILL-O2-NEXT: vs4r.v v8, (a0) # vscale x 32-byte Folded Spill
|
||||
; SPILL-O2-NEXT: #APP
|
||||
; SPILL-O2-NEXT: #NO_APP
|
||||
; SPILL-O2-NEXT: addi a0, sp, 16
|
||||
; SPILL-O2-NEXT: vl2r.v v6, (a0) # vscale x 16-byte Folded Reload
|
||||
; SPILL-O2-NEXT: csrr a1, vlenb
|
||||
; SPILL-O2-NEXT: slli a1, a1, 1
|
||||
; SPILL-O2-NEXT: vl2r.v v6, (a0) # vscale x 16-byte Folded Reload
|
||||
; SPILL-O2-NEXT: add a0, a0, a1
|
||||
; SPILL-O2-NEXT: vl2r.v v8, (a0) # vscale x 16-byte Folded Reload
|
||||
; SPILL-O2-NEXT: csrr a0, vlenb
|
||||
@ -309,15 +284,11 @@ define <vscale x 4 x i32> @spill_zvlsseg_nxv4i32(ptr %base, i64 %vl) nounwind {
|
||||
; SPILL-O2-VLEN128-NEXT: vsetvli zero, a1, e32, m2, ta, ma
|
||||
; SPILL-O2-VLEN128-NEXT: vlseg2e32.v v8, (a0)
|
||||
; SPILL-O2-VLEN128-NEXT: addi a0, sp, 16
|
||||
; SPILL-O2-VLEN128-NEXT: li a1, 32
|
||||
; SPILL-O2-VLEN128-NEXT: vs2r.v v8, (a0) # vscale x 16-byte Folded Spill
|
||||
; SPILL-O2-VLEN128-NEXT: add a0, a0, a1
|
||||
; SPILL-O2-VLEN128-NEXT: vs2r.v v10, (a0) # vscale x 16-byte Folded Spill
|
||||
; SPILL-O2-VLEN128-NEXT: vs4r.v v8, (a0) # vscale x 32-byte Folded Spill
|
||||
; SPILL-O2-VLEN128-NEXT: #APP
|
||||
; SPILL-O2-VLEN128-NEXT: #NO_APP
|
||||
; SPILL-O2-VLEN128-NEXT: addi a0, sp, 16
|
||||
; SPILL-O2-VLEN128-NEXT: li a1, 32
|
||||
; SPILL-O2-VLEN128-NEXT: vl2r.v v6, (a0) # vscale x 16-byte Folded Reload
|
||||
; SPILL-O2-VLEN128-NEXT: li a1, 32
|
||||
; SPILL-O2-VLEN128-NEXT: add a0, a0, a1
|
||||
; SPILL-O2-VLEN128-NEXT: vl2r.v v8, (a0) # vscale x 16-byte Folded Reload
|
||||
; SPILL-O2-VLEN128-NEXT: addi sp, sp, 64
|
||||
@ -353,17 +324,12 @@ define <vscale x 4 x i32> @spill_zvlsseg_nxv4i32(ptr %base, i64 %vl) nounwind {
|
||||
; SPILL-O2-VSETVLI-NEXT: vsetvli zero, a1, e32, m2, ta, ma
|
||||
; SPILL-O2-VSETVLI-NEXT: vlseg2e32.v v8, (a0)
|
||||
; SPILL-O2-VSETVLI-NEXT: addi a0, sp, 16
|
||||
; SPILL-O2-VSETVLI-NEXT: csrr a1, vlenb
|
||||
; SPILL-O2-VSETVLI-NEXT: slli a1, a1, 1
|
||||
; SPILL-O2-VSETVLI-NEXT: vs2r.v v8, (a0) # vscale x 16-byte Folded Spill
|
||||
; SPILL-O2-VSETVLI-NEXT: add a0, a0, a1
|
||||
; SPILL-O2-VSETVLI-NEXT: vs2r.v v10, (a0) # vscale x 16-byte Folded Spill
|
||||
; SPILL-O2-VSETVLI-NEXT: vs4r.v v8, (a0) # vscale x 32-byte Folded Spill
|
||||
; SPILL-O2-VSETVLI-NEXT: #APP
|
||||
; SPILL-O2-VSETVLI-NEXT: #NO_APP
|
||||
; SPILL-O2-VSETVLI-NEXT: addi a0, sp, 16
|
||||
; SPILL-O2-VSETVLI-NEXT: vl2r.v v6, (a0) # vscale x 16-byte Folded Reload
|
||||
; SPILL-O2-VSETVLI-NEXT: csrr a1, vlenb
|
||||
; SPILL-O2-VSETVLI-NEXT: slli a1, a1, 1
|
||||
; SPILL-O2-VSETVLI-NEXT: vl2r.v v6, (a0) # vscale x 16-byte Folded Reload
|
||||
; SPILL-O2-VSETVLI-NEXT: add a0, a0, a1
|
||||
; SPILL-O2-VSETVLI-NEXT: vl2r.v v8, (a0) # vscale x 16-byte Folded Reload
|
||||
; SPILL-O2-VSETVLI-NEXT: vsetvli a0, zero, e8, m4, ta, ma
|
||||
@ -411,17 +377,12 @@ define <vscale x 8 x i32> @spill_zvlsseg_nxv8i32(ptr %base, i64 %vl) nounwind {
|
||||
; SPILL-O2-NEXT: vsetvli zero, a1, e32, m4, ta, ma
|
||||
; SPILL-O2-NEXT: vlseg2e32.v v8, (a0)
|
||||
; SPILL-O2-NEXT: addi a0, sp, 16
|
||||
; SPILL-O2-NEXT: csrr a1, vlenb
|
||||
; SPILL-O2-NEXT: slli a1, a1, 2
|
||||
; SPILL-O2-NEXT: vs4r.v v8, (a0) # vscale x 32-byte Folded Spill
|
||||
; SPILL-O2-NEXT: add a0, a0, a1
|
||||
; SPILL-O2-NEXT: vs4r.v v12, (a0) # vscale x 32-byte Folded Spill
|
||||
; SPILL-O2-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
|
||||
; SPILL-O2-NEXT: #APP
|
||||
; SPILL-O2-NEXT: #NO_APP
|
||||
; SPILL-O2-NEXT: addi a0, sp, 16
|
||||
; SPILL-O2-NEXT: vl4r.v v4, (a0) # vscale x 32-byte Folded Reload
|
||||
; SPILL-O2-NEXT: csrr a1, vlenb
|
||||
; SPILL-O2-NEXT: slli a1, a1, 2
|
||||
; SPILL-O2-NEXT: vl4r.v v4, (a0) # vscale x 32-byte Folded Reload
|
||||
; SPILL-O2-NEXT: add a0, a0, a1
|
||||
; SPILL-O2-NEXT: vl4r.v v8, (a0) # vscale x 32-byte Folded Reload
|
||||
; SPILL-O2-NEXT: csrr a0, vlenb
|
||||
@ -437,15 +398,11 @@ define <vscale x 8 x i32> @spill_zvlsseg_nxv8i32(ptr %base, i64 %vl) nounwind {
|
||||
; SPILL-O2-VLEN128-NEXT: vsetvli zero, a1, e32, m4, ta, ma
|
||||
; SPILL-O2-VLEN128-NEXT: vlseg2e32.v v8, (a0)
|
||||
; SPILL-O2-VLEN128-NEXT: addi a0, sp, 16
|
||||
; SPILL-O2-VLEN128-NEXT: li a1, 64
|
||||
; SPILL-O2-VLEN128-NEXT: vs4r.v v8, (a0) # vscale x 32-byte Folded Spill
|
||||
; SPILL-O2-VLEN128-NEXT: add a0, a0, a1
|
||||
; SPILL-O2-VLEN128-NEXT: vs4r.v v12, (a0) # vscale x 32-byte Folded Spill
|
||||
; SPILL-O2-VLEN128-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
|
||||
; SPILL-O2-VLEN128-NEXT: #APP
|
||||
; SPILL-O2-VLEN128-NEXT: #NO_APP
|
||||
; SPILL-O2-VLEN128-NEXT: addi a0, sp, 16
|
||||
; SPILL-O2-VLEN128-NEXT: li a1, 64
|
||||
; SPILL-O2-VLEN128-NEXT: vl4r.v v4, (a0) # vscale x 32-byte Folded Reload
|
||||
; SPILL-O2-VLEN128-NEXT: li a1, 64
|
||||
; SPILL-O2-VLEN128-NEXT: add a0, a0, a1
|
||||
; SPILL-O2-VLEN128-NEXT: vl4r.v v8, (a0) # vscale x 32-byte Folded Reload
|
||||
; SPILL-O2-VLEN128-NEXT: addi sp, sp, 128
|
||||
@ -481,17 +438,12 @@ define <vscale x 8 x i32> @spill_zvlsseg_nxv8i32(ptr %base, i64 %vl) nounwind {
|
||||
; SPILL-O2-VSETVLI-NEXT: vsetvli zero, a1, e32, m4, ta, ma
|
||||
; SPILL-O2-VSETVLI-NEXT: vlseg2e32.v v8, (a0)
|
||||
; SPILL-O2-VSETVLI-NEXT: addi a0, sp, 16
|
||||
; SPILL-O2-VSETVLI-NEXT: csrr a1, vlenb
|
||||
; SPILL-O2-VSETVLI-NEXT: slli a1, a1, 2
|
||||
; SPILL-O2-VSETVLI-NEXT: vs4r.v v8, (a0) # vscale x 32-byte Folded Spill
|
||||
; SPILL-O2-VSETVLI-NEXT: add a0, a0, a1
|
||||
; SPILL-O2-VSETVLI-NEXT: vs4r.v v12, (a0) # vscale x 32-byte Folded Spill
|
||||
; SPILL-O2-VSETVLI-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
|
||||
; SPILL-O2-VSETVLI-NEXT: #APP
|
||||
; SPILL-O2-VSETVLI-NEXT: #NO_APP
|
||||
; SPILL-O2-VSETVLI-NEXT: addi a0, sp, 16
|
||||
; SPILL-O2-VSETVLI-NEXT: vl4r.v v4, (a0) # vscale x 32-byte Folded Reload
|
||||
; SPILL-O2-VSETVLI-NEXT: csrr a1, vlenb
|
||||
; SPILL-O2-VSETVLI-NEXT: slli a1, a1, 2
|
||||
; SPILL-O2-VSETVLI-NEXT: vl4r.v v4, (a0) # vscale x 32-byte Folded Reload
|
||||
; SPILL-O2-VSETVLI-NEXT: add a0, a0, a1
|
||||
; SPILL-O2-VSETVLI-NEXT: vl4r.v v8, (a0) # vscale x 32-byte Folded Reload
|
||||
; SPILL-O2-VSETVLI-NEXT: vsetvli a0, zero, e8, m8, ta, ma
|
||||
@ -540,23 +492,19 @@ define <vscale x 4 x i32> @spill_zvlsseg3_nxv4i32(ptr %base, i64 %vl) nounwind {
|
||||
; SPILL-O2-NEXT: vsetvli zero, a1, e32, m2, ta, ma
|
||||
; SPILL-O2-NEXT: vlseg3e32.v v8, (a0)
|
||||
; SPILL-O2-NEXT: addi a0, sp, 16
|
||||
; SPILL-O2-NEXT: vs4r.v v8, (a0) # vscale x 32-byte Folded Spill
|
||||
; SPILL-O2-NEXT: csrr a1, vlenb
|
||||
; SPILL-O2-NEXT: slli a1, a1, 1
|
||||
; SPILL-O2-NEXT: vs2r.v v8, (a0) # vscale x 16-byte Folded Spill
|
||||
; SPILL-O2-NEXT: add a0, a0, a1
|
||||
; SPILL-O2-NEXT: vs2r.v v10, (a0) # vscale x 16-byte Folded Spill
|
||||
; SPILL-O2-NEXT: slli a1, a1, 2
|
||||
; SPILL-O2-NEXT: add a0, a0, a1
|
||||
; SPILL-O2-NEXT: vs2r.v v12, (a0) # vscale x 16-byte Folded Spill
|
||||
; SPILL-O2-NEXT: #APP
|
||||
; SPILL-O2-NEXT: #NO_APP
|
||||
; SPILL-O2-NEXT: addi a0, sp, 16
|
||||
; SPILL-O2-NEXT: vl2r.v v6, (a0) # vscale x 16-byte Folded Reload
|
||||
; SPILL-O2-NEXT: csrr a1, vlenb
|
||||
; SPILL-O2-NEXT: slli a1, a1, 1
|
||||
; SPILL-O2-NEXT: vl2r.v v6, (a0) # vscale x 16-byte Folded Reload
|
||||
; SPILL-O2-NEXT: add a0, a0, a1
|
||||
; SPILL-O2-NEXT: vl2r.v v8, (a0) # vscale x 16-byte Folded Reload
|
||||
; SPILL-O2-NEXT: add a0, a0, a1
|
||||
; SPILL-O2-NEXT: vl2r.v v10, (a0) # vscale x 16-byte Folded Reload
|
||||
; SPILL-O2-NEXT: vl4r.v v8, (a0) # vscale x 32-byte Folded Reload
|
||||
; SPILL-O2-NEXT: csrr a0, vlenb
|
||||
; SPILL-O2-NEXT: li a1, 6
|
||||
; SPILL-O2-NEXT: mul a0, a0, a1
|
||||
@ -571,21 +519,17 @@ define <vscale x 4 x i32> @spill_zvlsseg3_nxv4i32(ptr %base, i64 %vl) nounwind {
|
||||
; SPILL-O2-VLEN128-NEXT: vsetvli zero, a1, e32, m2, ta, ma
|
||||
; SPILL-O2-VLEN128-NEXT: vlseg3e32.v v8, (a0)
|
||||
; SPILL-O2-VLEN128-NEXT: addi a0, sp, 16
|
||||
; SPILL-O2-VLEN128-NEXT: li a1, 32
|
||||
; SPILL-O2-VLEN128-NEXT: vs2r.v v8, (a0) # vscale x 16-byte Folded Spill
|
||||
; SPILL-O2-VLEN128-NEXT: add a0, a0, a1
|
||||
; SPILL-O2-VLEN128-NEXT: vs2r.v v10, (a0) # vscale x 16-byte Folded Spill
|
||||
; SPILL-O2-VLEN128-NEXT: vs4r.v v8, (a0) # vscale x 32-byte Folded Spill
|
||||
; SPILL-O2-VLEN128-NEXT: li a1, 64
|
||||
; SPILL-O2-VLEN128-NEXT: add a0, a0, a1
|
||||
; SPILL-O2-VLEN128-NEXT: vs2r.v v12, (a0) # vscale x 16-byte Folded Spill
|
||||
; SPILL-O2-VLEN128-NEXT: #APP
|
||||
; SPILL-O2-VLEN128-NEXT: #NO_APP
|
||||
; SPILL-O2-VLEN128-NEXT: addi a0, sp, 16
|
||||
; SPILL-O2-VLEN128-NEXT: li a1, 32
|
||||
; SPILL-O2-VLEN128-NEXT: vl2r.v v6, (a0) # vscale x 16-byte Folded Reload
|
||||
; SPILL-O2-VLEN128-NEXT: li a1, 32
|
||||
; SPILL-O2-VLEN128-NEXT: add a0, a0, a1
|
||||
; SPILL-O2-VLEN128-NEXT: vl2r.v v8, (a0) # vscale x 16-byte Folded Reload
|
||||
; SPILL-O2-VLEN128-NEXT: add a0, a0, a1
|
||||
; SPILL-O2-VLEN128-NEXT: vl2r.v v10, (a0) # vscale x 16-byte Folded Reload
|
||||
; SPILL-O2-VLEN128-NEXT: vl4r.v v8, (a0) # vscale x 32-byte Folded Reload
|
||||
; SPILL-O2-VLEN128-NEXT: addi sp, sp, 96
|
||||
; SPILL-O2-VLEN128-NEXT: addi sp, sp, 16
|
||||
; SPILL-O2-VLEN128-NEXT: ret
|
||||
@ -621,23 +565,19 @@ define <vscale x 4 x i32> @spill_zvlsseg3_nxv4i32(ptr %base, i64 %vl) nounwind {
|
||||
; SPILL-O2-VSETVLI-NEXT: vsetvli zero, a1, e32, m2, ta, ma
|
||||
; SPILL-O2-VSETVLI-NEXT: vlseg3e32.v v8, (a0)
|
||||
; SPILL-O2-VSETVLI-NEXT: addi a0, sp, 16
|
||||
; SPILL-O2-VSETVLI-NEXT: vs4r.v v8, (a0) # vscale x 32-byte Folded Spill
|
||||
; SPILL-O2-VSETVLI-NEXT: csrr a1, vlenb
|
||||
; SPILL-O2-VSETVLI-NEXT: slli a1, a1, 1
|
||||
; SPILL-O2-VSETVLI-NEXT: vs2r.v v8, (a0) # vscale x 16-byte Folded Spill
|
||||
; SPILL-O2-VSETVLI-NEXT: add a0, a0, a1
|
||||
; SPILL-O2-VSETVLI-NEXT: vs2r.v v10, (a0) # vscale x 16-byte Folded Spill
|
||||
; SPILL-O2-VSETVLI-NEXT: slli a1, a1, 2
|
||||
; SPILL-O2-VSETVLI-NEXT: add a0, a0, a1
|
||||
; SPILL-O2-VSETVLI-NEXT: vs2r.v v12, (a0) # vscale x 16-byte Folded Spill
|
||||
; SPILL-O2-VSETVLI-NEXT: #APP
|
||||
; SPILL-O2-VSETVLI-NEXT: #NO_APP
|
||||
; SPILL-O2-VSETVLI-NEXT: addi a0, sp, 16
|
||||
; SPILL-O2-VSETVLI-NEXT: vl2r.v v6, (a0) # vscale x 16-byte Folded Reload
|
||||
; SPILL-O2-VSETVLI-NEXT: csrr a1, vlenb
|
||||
; SPILL-O2-VSETVLI-NEXT: slli a1, a1, 1
|
||||
; SPILL-O2-VSETVLI-NEXT: vl2r.v v6, (a0) # vscale x 16-byte Folded Reload
|
||||
; SPILL-O2-VSETVLI-NEXT: add a0, a0, a1
|
||||
; SPILL-O2-VSETVLI-NEXT: vl2r.v v8, (a0) # vscale x 16-byte Folded Reload
|
||||
; SPILL-O2-VSETVLI-NEXT: add a0, a0, a1
|
||||
; SPILL-O2-VSETVLI-NEXT: vl2r.v v10, (a0) # vscale x 16-byte Folded Reload
|
||||
; SPILL-O2-VSETVLI-NEXT: vl4r.v v8, (a0) # vscale x 32-byte Folded Reload
|
||||
; SPILL-O2-VSETVLI-NEXT: vsetvli a0, zero, e8, m1, ta, ma
|
||||
; SPILL-O2-VSETVLI-NEXT: li a1, 6
|
||||
; SPILL-O2-VSETVLI-NEXT: mul a0, a0, a1
|
||||
|
||||
@ -2,15 +2,15 @@
|
||||
# RUN: llc -mtriple=riscv64 -mattr=+v -stop-after=prologepilog %s -o - 2>&1 | FileCheck %s
|
||||
|
||||
--- |
|
||||
target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n64-S128"
|
||||
target triple = "riscv64"
|
||||
|
||||
define void @zvlsseg_spill(ptr %base, i64 %vl) {
|
||||
define void @zvlsseg_spill_0(ptr %base, i64 %vl) {
|
||||
ret void
|
||||
}
|
||||
define void @zvlsseg_spill_1(ptr %base, i64 %vl) {
|
||||
ret void
|
||||
}
|
||||
...
|
||||
---
|
||||
name: zvlsseg_spill
|
||||
name: zvlsseg_spill_0
|
||||
tracksRegLiveness: true
|
||||
stack:
|
||||
- { id: 0, offset: 0, size: 64, alignment: 8, stack-id: scalable-vector }
|
||||
@ -18,7 +18,7 @@ body: |
|
||||
bb.0:
|
||||
liveins: $x10, $x11
|
||||
|
||||
; CHECK-LABEL: name: zvlsseg_spill
|
||||
; CHECK-LABEL: name: zvlsseg_spill_0
|
||||
; CHECK: liveins: $x10, $x11
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: $x2 = frame-setup ADDI $x2, -16
|
||||
@ -30,35 +30,22 @@ body: |
|
||||
; CHECK-NEXT: dead $x0 = PseudoVSETVLI killed renamable $x11, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype
|
||||
; CHECK-NEXT: $v0_v1_v2_v3_v4_v5_v6 = PseudoVLSEG7E64_V_M1 undef $v0_v1_v2_v3_v4_v5_v6, renamable $x10, $noreg, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
|
||||
; CHECK-NEXT: $x11 = ADDI $x2, 16
|
||||
; CHECK-NEXT: VS4R_V $v0m4, $x11, implicit $v0_v1_v2_v3_v4_v5_v6 :: (store (<vscale x 1 x s256>) into %stack.0, align 8)
|
||||
; CHECK-NEXT: $x12 = PseudoReadVLENB
|
||||
; CHECK-NEXT: VS1R_V $v0, $x11, implicit $v0_v1_v2_v3_v4_v5_v6 :: (store (<vscale x 1 x s64>) into %stack.0)
|
||||
; CHECK-NEXT: $x11 = ADD killed $x11, $x12
|
||||
; CHECK-NEXT: VS1R_V $v1, $x11, implicit $v0_v1_v2_v3_v4_v5_v6 :: (store (<vscale x 1 x s64>) into %stack.0)
|
||||
; CHECK-NEXT: $x11 = ADD killed $x11, $x12
|
||||
; CHECK-NEXT: VS1R_V $v2, $x11, implicit $v0_v1_v2_v3_v4_v5_v6 :: (store (<vscale x 1 x s64>) into %stack.0)
|
||||
; CHECK-NEXT: $x11 = ADD killed $x11, $x12
|
||||
; CHECK-NEXT: VS1R_V $v3, $x11, implicit $v0_v1_v2_v3_v4_v5_v6 :: (store (<vscale x 1 x s64>) into %stack.0)
|
||||
; CHECK-NEXT: $x11 = ADD killed $x11, $x12
|
||||
; CHECK-NEXT: VS1R_V $v4, $x11, implicit $v0_v1_v2_v3_v4_v5_v6 :: (store (<vscale x 1 x s64>) into %stack.0)
|
||||
; CHECK-NEXT: $x11 = ADD killed $x11, $x12
|
||||
; CHECK-NEXT: VS1R_V $v5, $x11, implicit $v0_v1_v2_v3_v4_v5_v6 :: (store (<vscale x 1 x s64>) into %stack.0)
|
||||
; CHECK-NEXT: $x13 = SLLI $x12, 2
|
||||
; CHECK-NEXT: $x11 = ADD killed $x11, killed $x13
|
||||
; CHECK-NEXT: VS2R_V $v4m2, $x11, implicit $v0_v1_v2_v3_v4_v5_v6 :: (store (<vscale x 1 x s128>) into %stack.0, align 8)
|
||||
; CHECK-NEXT: $x12 = SLLI killed $x12, 1
|
||||
; CHECK-NEXT: $x11 = ADD killed $x11, killed $x12
|
||||
; CHECK-NEXT: VS1R_V $v6, killed $x11, implicit $v0_v1_v2_v3_v4_v5_v6 :: (store (<vscale x 1 x s64>) into %stack.0)
|
||||
; CHECK-NEXT: $x11 = ADDI $x2, 16
|
||||
; CHECK-NEXT: $x12 = PseudoReadVLENB
|
||||
; CHECK-NEXT: $v7 = VL1RE8_V $x11 :: (load (<vscale x 1 x s64>) from %stack.0)
|
||||
; CHECK-NEXT: $x12 = PseudoReadVLENB
|
||||
; CHECK-NEXT: $x11 = ADD killed $x11, $x12
|
||||
; CHECK-NEXT: $v8 = VL1RE8_V $x11 :: (load (<vscale x 1 x s64>) from %stack.0)
|
||||
; CHECK-NEXT: $x11 = ADD killed $x11, $x12
|
||||
; CHECK-NEXT: $v9 = VL1RE8_V $x11 :: (load (<vscale x 1 x s64>) from %stack.0)
|
||||
; CHECK-NEXT: $x11 = ADD killed $x11, $x12
|
||||
; CHECK-NEXT: $v10 = VL1RE8_V $x11 :: (load (<vscale x 1 x s64>) from %stack.0)
|
||||
; CHECK-NEXT: $x11 = ADD killed $x11, $x12
|
||||
; CHECK-NEXT: $v11 = VL1RE8_V $x11 :: (load (<vscale x 1 x s64>) from %stack.0)
|
||||
; CHECK-NEXT: $x11 = ADD killed $x11, $x12
|
||||
; CHECK-NEXT: $v12 = VL1RE8_V $x11 :: (load (<vscale x 1 x s64>) from %stack.0)
|
||||
; CHECK-NEXT: $v8m4 = VL4RE8_V $x11 :: (load (<vscale x 1 x s256>) from %stack.0, align 8)
|
||||
; CHECK-NEXT: $x12 = SLLI killed $x12, 2
|
||||
; CHECK-NEXT: $x11 = ADD killed $x11, killed $x12
|
||||
; CHECK-NEXT: $v13 = VL1RE8_V killed $x11 :: (load (<vscale x 1 x s64>) from %stack.0)
|
||||
; CHECK-NEXT: $v12m2 = VL2RE8_V killed $x11 :: (load (<vscale x 1 x s128>) from %stack.0, align 8)
|
||||
; CHECK-NEXT: VS1R_V killed $v8, killed renamable $x10
|
||||
; CHECK-NEXT: $x10 = frame-destroy PseudoReadVLENB
|
||||
; CHECK-NEXT: $x10 = frame-destroy SLLI killed $x10, 3
|
||||
@ -75,3 +62,56 @@ body: |
|
||||
VS1R_V killed $v8, %0:gpr
|
||||
PseudoRET
|
||||
...
|
||||
|
||||
---
|
||||
name: zvlsseg_spill_1
|
||||
tracksRegLiveness: true
|
||||
stack:
|
||||
- { id: 0, offset: 0, size: 64, alignment: 8, stack-id: scalable-vector }
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $x10, $x11
|
||||
; CHECK-LABEL: name: zvlsseg_spill_1
|
||||
; CHECK: liveins: $x10, $x11
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: $x2 = frame-setup ADDI $x2, -16
|
||||
; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 16
|
||||
; CHECK-NEXT: $x12 = frame-setup PseudoReadVLENB
|
||||
; CHECK-NEXT: $x12 = frame-setup SLLI killed $x12, 3
|
||||
; CHECK-NEXT: $x2 = frame-setup SUB $x2, killed $x12
|
||||
; CHECK-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22
|
||||
; CHECK-NEXT: dead $x0 = PseudoVSETVLI killed renamable $x11, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype
|
||||
; CHECK-NEXT: $v1_v2_v3_v4_v5_v6_v7 = PseudoVLSEG7E64_V_M1 undef $v1_v2_v3_v4_v5_v6_v7, renamable $x10, $noreg, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
|
||||
; CHECK-NEXT: $x11 = ADDI $x2, 16
|
||||
; CHECK-NEXT: VS1R_V $v1, $x11, implicit $v1_v2_v3_v4_v5_v6_v7 :: (store (<vscale x 1 x s64>) into %stack.0)
|
||||
; CHECK-NEXT: $x12 = PseudoReadVLENB
|
||||
; CHECK-NEXT: $x11 = ADD killed $x11, $x12
|
||||
; CHECK-NEXT: VS2R_V $v2m2, $x11, implicit $v1_v2_v3_v4_v5_v6_v7 :: (store (<vscale x 1 x s128>) into %stack.0, align 8)
|
||||
; CHECK-NEXT: $x12 = SLLI killed $x12, 1
|
||||
; CHECK-NEXT: $x11 = ADD killed $x11, killed $x12
|
||||
; CHECK-NEXT: VS4R_V $v4m4, killed $x11, implicit $v1_v2_v3_v4_v5_v6_v7 :: (store (<vscale x 1 x s256>) into %stack.0, align 8)
|
||||
; CHECK-NEXT: $x11 = ADDI $x2, 16
|
||||
; CHECK-NEXT: $v10m2 = VL2RE8_V $x11 :: (load (<vscale x 1 x s128>) from %stack.0, align 8)
|
||||
; CHECK-NEXT: $x12 = PseudoReadVLENB
|
||||
; CHECK-NEXT: $x13 = SLLI $x12, 1
|
||||
; CHECK-NEXT: $x11 = ADD killed $x11, killed $x13
|
||||
; CHECK-NEXT: $v12m4 = VL4RE8_V $x11 :: (load (<vscale x 1 x s256>) from %stack.0, align 8)
|
||||
; CHECK-NEXT: $x12 = SLLI killed $x12, 2
|
||||
; CHECK-NEXT: $x11 = ADD killed $x11, killed $x12
|
||||
; CHECK-NEXT: $v16 = VL1RE8_V killed $x11 :: (load (<vscale x 1 x s64>) from %stack.0)
|
||||
; CHECK-NEXT: VS1R_V killed $v10, killed renamable $x10
|
||||
; CHECK-NEXT: $x10 = frame-destroy PseudoReadVLENB
|
||||
; CHECK-NEXT: $x10 = frame-destroy SLLI killed $x10, 3
|
||||
; CHECK-NEXT: $x2 = frame-destroy ADD $x2, killed $x10
|
||||
; CHECK-NEXT: frame-destroy CFI_INSTRUCTION def_cfa $x2, 16
|
||||
; CHECK-NEXT: $x2 = frame-destroy ADDI $x2, 16
|
||||
; CHECK-NEXT: frame-destroy CFI_INSTRUCTION def_cfa_offset 0
|
||||
; CHECK-NEXT: PseudoRET
|
||||
%0:gpr = COPY $x10
|
||||
%1:gprnox0 = COPY $x11
|
||||
$v1_v2_v3_v4_v5_v6_v7 = PseudoVLSEG7E64_V_M1 undef $v1_v2_v3_v4_v5_v6_v7, %0, %1, 6, 0
|
||||
PseudoVSPILL7_M1 killed renamable $v1_v2_v3_v4_v5_v6_v7, %stack.0 :: (store (<vscale x 7 x s64>) into %stack.0, align 8)
|
||||
renamable $v10_v11_v12_v13_v14_v15_v16 = PseudoVRELOAD7_M1 %stack.0 :: (load (<vscale x 7 x s64>) from %stack.0, align 8)
|
||||
VS1R_V killed $v10, %0:gpr
|
||||
PseudoRET
|
||||
...
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user