diff --git a/llvm/docs/HowToUseInstrMappings.rst b/llvm/docs/HowToUseInstrMappings.rst index 17599da004ee..39ae169c0c50 100644 --- a/llvm/docs/HowToUseInstrMappings.rst +++ b/llvm/docs/HowToUseInstrMappings.rst @@ -61,7 +61,7 @@ Sample Example -------------- Let's say that we want to have a function -``int getPredOpcode(uint32_t Opcode, enum PredSense inPredSense)`` which +``int getPredOpcode(uint16_t Opcode, enum PredSense inPredSense)`` which takes a non-predicated instruction and returns its predicated true or false form depending on some input flag, ``inPredSense``. The first step in the process is to define a relationship model that relates predicated instructions to their @@ -107,7 +107,7 @@ instruction since they are the ones used to query the interface function. TableGen uses the above relationship model to emit relation table that maps non-predicated instructions with their predicated forms. It also outputs the interface function -``int getPredOpcode(uint32_t Opcode, enum PredSense inPredSense)`` to query +``int getPredOpcode(uint16_t Opcode, enum PredSense inPredSense)`` to query the table. Here, Function ``getPredOpcode`` takes two arguments, opcode of the current instruction and PredSense of the desired instruction, and returns predicated form of the instruction, if found in the relation table. diff --git a/llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h b/llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h index 6737ad1c8d42..78b189d44e28 100644 --- a/llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h +++ b/llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h @@ -1058,7 +1058,7 @@ bool GIMatchTableExecutor::executeMatchTable( case GIR_MutateOpcode: { uint64_t OldInsnID = readULEB(); uint64_t NewInsnID = readULEB(); - uint32_t NewOpcode = readU32(); + uint16_t NewOpcode = readU16(); if (NewInsnID >= OutMIs.size()) OutMIs.resize(NewInsnID + 1); @@ -1079,7 +1079,7 @@ bool GIMatchTableExecutor::executeMatchTable( case GIR_BuildRootMI: case GIR_BuildMI: { uint64_t NewInsnID = (MatcherOpcode == GIR_BuildRootMI) ? 0 : readULEB(); - uint32_t Opcode = readU32(); + uint16_t Opcode = readU16(); if (NewInsnID >= OutMIs.size()) OutMIs.resize(NewInsnID + 1); diff --git a/llvm/include/llvm/CodeGen/MachineInstr.h b/llvm/include/llvm/CodeGen/MachineInstr.h index 90a9967b9701..29da32c931ee 100644 --- a/llvm/include/llvm/CodeGen/MachineInstr.h +++ b/llvm/include/llvm/CodeGen/MachineInstr.h @@ -156,7 +156,7 @@ private: uint8_t AsmPrinterFlags; /// Cached opcode from MCID. - uint32_t Opcode; + uint16_t Opcode; /// Unique instruction number. Used by DBG_INSTR_REFs to refer to the values /// defined by this instruction. diff --git a/llvm/include/llvm/MC/MCInstrDesc.h b/llvm/include/llvm/MC/MCInstrDesc.h index 396995edc117..69dd3e284883 100644 --- a/llvm/include/llvm/MC/MCInstrDesc.h +++ b/llvm/include/llvm/MC/MCInstrDesc.h @@ -203,17 +203,17 @@ public: // the Insts table because they rely on knowing their own address to // find other information elsewhere in the same table. - uint32_t Opcode; // The opcode number. - uint16_t NumOperands; // Num of args (may be more if variable_ops) - uint8_t NumDefs; // Num of args that are definitions - uint8_t Size; // Number of bytes in encoding. - uint16_t SchedClass; // enum identifying instr sched class - uint8_t NumImplicitUses; // Num of regs implicitly used - uint8_t NumImplicitDefs; // Num of regs implicitly defined - uint16_t OpInfoOffset; // Offset to info about operands - uint16_t ImplicitOffset; // Offset to start of implicit op list - uint64_t Flags; // Flags identifying machine instr class - uint64_t TSFlags; // Target Specific Flag values + unsigned short Opcode; // The opcode number + unsigned short NumOperands; // Num of args (may be more if variable_ops) + unsigned char NumDefs; // Num of args that are definitions + unsigned char Size; // Number of bytes in encoding. + unsigned short SchedClass; // enum identifying instr sched class + unsigned char NumImplicitUses; // Num of regs implicitly used + unsigned char NumImplicitDefs; // Num of regs implicitly defined + unsigned short OpInfoOffset; // Offset to info about operands + unsigned short ImplicitOffset; // Offset to start of implicit op list + uint64_t Flags; // Flags identifying machine instr class + uint64_t TSFlags; // Target Specific Flag values /// Returns the value of the specified operand constraint if /// it is present. Returns -1 if it is not present. diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp index 1119060d74bf..ab70b200d296 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp @@ -4227,10 +4227,8 @@ void SelectionDAGISel::SelectCodeCommon(SDNode *NodeToMatch, case OPC_MorphNodeTo2GlueInput: case OPC_MorphNodeTo1GlueOutput: case OPC_MorphNodeTo2GlueOutput: { - uint32_t TargetOpc = MatcherTable[MatcherIndex++]; - TargetOpc |= (MatcherTable[MatcherIndex++] << 8); - TargetOpc |= (MatcherTable[MatcherIndex++] << 16); - TargetOpc |= (MatcherTable[MatcherIndex++] << 24); + uint16_t TargetOpc = MatcherTable[MatcherIndex++]; + TargetOpc |= static_cast(MatcherTable[MatcherIndex++]) << 8; unsigned EmitNodeInfo; if (Opcode >= OPC_EmitNode1None && Opcode <= OPC_EmitNode2Chain) { if (Opcode >= OPC_EmitNode0Chain && Opcode <= OPC_EmitNode2Chain) diff --git a/llvm/lib/MCA/InstrBuilder.cpp b/llvm/lib/MCA/InstrBuilder.cpp index 32b8cf5c38b4..ffd6a8d5c14a 100644 --- a/llvm/lib/MCA/InstrBuilder.cpp +++ b/llvm/lib/MCA/InstrBuilder.cpp @@ -563,7 +563,7 @@ InstrBuilder::createInstrDescImpl(const MCInst &MCI, "Itineraries are not yet supported!"); // Obtain the instruction descriptor from the opcode. - unsigned Opcode = MCI.getOpcode(); + unsigned short Opcode = MCI.getOpcode(); const MCInstrDesc &MCDesc = MCII.get(Opcode); const MCSchedModel &SM = STI.getSchedModel(); diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.h b/llvm/lib/Target/AArch64/AArch64InstrInfo.h index ac6b9dd5dbd6..2ccde3e661de 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrInfo.h +++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.h @@ -890,11 +890,11 @@ enum SMEMatrixType { #undef TSFLAG_INSTR_FLAGS #undef TSFLAG_SME_MATRIX_TYPE -int64_t getSVEPseudoMap(uint32_t Opcode); -int64_t getSVERevInstr(uint32_t Opcode); -int64_t getSVENonRevInstr(uint32_t Opcode); +int getSVEPseudoMap(uint16_t Opcode); +int getSVERevInstr(uint16_t Opcode); +int getSVENonRevInstr(uint16_t Opcode); -int64_t getSMEPseudoMap(uint32_t Opcode); +int getSMEPseudoMap(uint16_t Opcode); } } // end namespace llvm diff --git a/llvm/lib/Target/AMDGPU/MCA/AMDGPUCustomBehaviour.cpp b/llvm/lib/Target/AMDGPU/MCA/AMDGPUCustomBehaviour.cpp index 9ec12131d723..afaa19013bfc 100644 --- a/llvm/lib/Target/AMDGPU/MCA/AMDGPUCustomBehaviour.cpp +++ b/llvm/lib/Target/AMDGPU/MCA/AMDGPUCustomBehaviour.cpp @@ -322,13 +322,13 @@ bool AMDGPUCustomBehaviour::hasModifiersSet( } // taken from SIInstrInfo::isGWS() -bool AMDGPUCustomBehaviour::isGWS(uint32_t Opcode) const { +bool AMDGPUCustomBehaviour::isGWS(uint16_t Opcode) const { const MCInstrDesc &MCID = MCII.get(Opcode); return MCID.TSFlags & SIInstrFlags::GWS; } // taken from SIInstrInfo::isAlwaysGDS() -bool AMDGPUCustomBehaviour::isAlwaysGDS(uint32_t Opcode) const { +bool AMDGPUCustomBehaviour::isAlwaysGDS(uint16_t Opcode) const { return Opcode == AMDGPU::DS_ORDERED_COUNT || Opcode == AMDGPU::DS_ADD_GS_REG_RTN || Opcode == AMDGPU::DS_SUB_GS_REG_RTN || isGWS(Opcode); diff --git a/llvm/lib/Target/AMDGPU/MCA/AMDGPUCustomBehaviour.h b/llvm/lib/Target/AMDGPU/MCA/AMDGPUCustomBehaviour.h index aeb5c032daee..4d0c163c5ea7 100644 --- a/llvm/lib/Target/AMDGPU/MCA/AMDGPUCustomBehaviour.h +++ b/llvm/lib/Target/AMDGPU/MCA/AMDGPUCustomBehaviour.h @@ -68,9 +68,9 @@ class AMDGPUCustomBehaviour : public CustomBehaviour { bool hasModifiersSet(const std::unique_ptr &Inst, AMDGPU::OpName OpName) const; /// Helper function used in generateWaitCntInfo() - bool isGWS(uint32_t Opcode) const; + bool isGWS(uint16_t Opcode) const; /// Helper function used in generateWaitCntInfo() - bool isAlwaysGDS(uint32_t Opcode) const; + bool isAlwaysGDS(uint16_t Opcode) const; /// Helper function used in generateWaitCntInfo() bool isVMEM(const MCInstrDesc &MCID); /// This method gets called from checkCustomHazard when mca is attempting to diff --git a/llvm/lib/Target/AMDGPU/R600InstrInfo.h b/llvm/lib/Target/AMDGPU/R600InstrInfo.h index b96c17e13707..68bbac103cb9 100644 --- a/llvm/lib/Target/AMDGPU/R600InstrInfo.h +++ b/llvm/lib/Target/AMDGPU/R600InstrInfo.h @@ -326,7 +326,7 @@ public: namespace R600 { -int64_t getLDSNoRetOp(uint32_t Opcode); +int getLDSNoRetOp(uint16_t Opcode); } //End namespace AMDGPU diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp index 54331f4667ab..9211de81b5fb 100644 --- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp @@ -1155,7 +1155,7 @@ void SIInstrInfo::copyPhysReg(MachineBasicBlock &MBB, } int SIInstrInfo::commuteOpcode(unsigned Opcode) const { - int64_t NewOpc; + int NewOpc; // Try to map original to commuted opcode NewOpc = AMDGPU::getCommuteRev(Opcode); @@ -4510,7 +4510,7 @@ bool SIInstrInfo::isSchedulingBoundary(const MachineInstr &MI, changesVGPRIndexingMode(MI); } -bool SIInstrInfo::isAlwaysGDS(uint32_t Opcode) const { +bool SIInstrInfo::isAlwaysGDS(uint16_t Opcode) const { return Opcode == AMDGPU::DS_ORDERED_COUNT || Opcode == AMDGPU::DS_ADD_GS_REG_RTN || Opcode == AMDGPU::DS_SUB_GS_REG_RTN || isGWS(Opcode); @@ -5138,7 +5138,7 @@ bool SIInstrInfo::verifyCopy(const MachineInstr &MI, bool SIInstrInfo::verifyInstruction(const MachineInstr &MI, StringRef &ErrInfo) const { - uint32_t Opcode = MI.getOpcode(); + uint16_t Opcode = MI.getOpcode(); const MachineFunction *MF = MI.getMF(); const MachineRegisterInfo &MRI = MF->getRegInfo(); @@ -5395,7 +5395,7 @@ bool SIInstrInfo::verifyInstruction(const MachineInstr &MI, } } - uint32_t BasicOpcode = AMDGPU::getBasicFromSDWAOp(Opcode); + uint16_t BasicOpcode = AMDGPU::getBasicFromSDWAOp(Opcode); if (isVOPC(BasicOpcode)) { if (!ST.hasSDWASdst() && DstIdx != -1) { // Only vcc allowed as dst on VI for VOPC @@ -9946,7 +9946,7 @@ unsigned SIInstrInfo::getLiveRangeSplitOpcode(Register SrcReg, } bool SIInstrInfo::canAddToBBProlog(const MachineInstr &MI) const { - uint32_t Opcode = MI.getOpcode(); + uint16_t Opcode = MI.getOpcode(); // Check if it is SGPR spill or wwm-register spill Opcode. if (isSGPRSpill(Opcode) || isWWMRegSpillOpcode(Opcode)) return true; @@ -10347,9 +10347,9 @@ int SIInstrInfo::pseudoToMCOpcode(int Opcode) const { Opcode = MFMAOp; } - int64_t MCOp = AMDGPU::getMCOpcode(Opcode, Gen); + int MCOp = AMDGPU::getMCOpcode(Opcode, Gen); - if (MCOp == (uint32_t)-1 && ST.hasGFX1250Insts()) + if (MCOp == (uint16_t)-1 && ST.hasGFX1250Insts()) MCOp = AMDGPU::getMCOpcode(Opcode, SIEncodingFamily::GFX12); // -1 means that Opcode is already a native instruction. @@ -10357,20 +10357,20 @@ int SIInstrInfo::pseudoToMCOpcode(int Opcode) const { return Opcode; if (ST.hasGFX90AInsts()) { - uint32_t NMCOp = (uint32_t)-1; + uint16_t NMCOp = (uint16_t)-1; if (ST.hasGFX940Insts()) NMCOp = AMDGPU::getMCOpcode(Opcode, SIEncodingFamily::GFX940); - if (NMCOp == (uint32_t)-1) + if (NMCOp == (uint16_t)-1) NMCOp = AMDGPU::getMCOpcode(Opcode, SIEncodingFamily::GFX90A); - if (NMCOp == (uint32_t)-1) + if (NMCOp == (uint16_t)-1) NMCOp = AMDGPU::getMCOpcode(Opcode, SIEncodingFamily::GFX9); - if (NMCOp != (uint32_t)-1) + if (NMCOp != (uint16_t)-1) MCOp = NMCOp; } - // (uint32_t)-1 means that Opcode is a pseudo instruction that has + // (uint16_t)-1 means that Opcode is a pseudo instruction that has // no encoding in the given subtarget generation. - if (MCOp == (uint32_t)-1) + if (MCOp == (uint16_t)-1) return -1; if (isAsmOnlyOpcode(MCOp)) diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.h b/llvm/lib/Target/AMDGPU/SIInstrInfo.h index 0b54513bb611..85585cbfc628 100644 --- a/llvm/lib/Target/AMDGPU/SIInstrInfo.h +++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.h @@ -466,7 +466,7 @@ public: return MI.getDesc().TSFlags & SIInstrFlags::SALU; } - bool isSALU(uint32_t Opcode) const { + bool isSALU(uint16_t Opcode) const { return get(Opcode).TSFlags & SIInstrFlags::SALU; } @@ -474,7 +474,7 @@ public: return MI.getDesc().TSFlags & SIInstrFlags::VALU; } - bool isVALU(uint32_t Opcode) const { + bool isVALU(uint16_t Opcode) const { return get(Opcode).TSFlags & SIInstrFlags::VALU; } @@ -482,7 +482,7 @@ public: return isMIMG(MI) || isVSAMPLE(MI) || isVIMAGE(MI); } - bool isImage(uint32_t Opcode) const { + bool isImage(uint16_t Opcode) const { return isMIMG(Opcode) || isVSAMPLE(Opcode) || isVIMAGE(Opcode); } @@ -490,7 +490,7 @@ public: return isMUBUF(MI) || isMTBUF(MI) || isImage(MI) || isFLAT(MI); } - bool isVMEM(uint32_t Opcode) const { + bool isVMEM(uint16_t Opcode) const { return isMUBUF(Opcode) || isMTBUF(Opcode) || isImage(Opcode); } @@ -498,7 +498,7 @@ public: return MI.getDesc().TSFlags & SIInstrFlags::SOP1; } - bool isSOP1(uint32_t Opcode) const { + bool isSOP1(uint16_t Opcode) const { return get(Opcode).TSFlags & SIInstrFlags::SOP1; } @@ -506,7 +506,7 @@ public: return MI.getDesc().TSFlags & SIInstrFlags::SOP2; } - bool isSOP2(uint32_t Opcode) const { + bool isSOP2(uint16_t Opcode) const { return get(Opcode).TSFlags & SIInstrFlags::SOP2; } @@ -514,7 +514,7 @@ public: return MI.getDesc().TSFlags & SIInstrFlags::SOPC; } - bool isSOPC(uint32_t Opcode) const { + bool isSOPC(uint16_t Opcode) const { return get(Opcode).TSFlags & SIInstrFlags::SOPC; } @@ -522,7 +522,7 @@ public: return MI.getDesc().TSFlags & SIInstrFlags::SOPK; } - bool isSOPK(uint32_t Opcode) const { + bool isSOPK(uint16_t Opcode) const { return get(Opcode).TSFlags & SIInstrFlags::SOPK; } @@ -530,7 +530,7 @@ public: return MI.getDesc().TSFlags & SIInstrFlags::SOPP; } - bool isSOPP(uint32_t Opcode) const { + bool isSOPP(uint16_t Opcode) const { return get(Opcode).TSFlags & SIInstrFlags::SOPP; } @@ -538,7 +538,7 @@ public: return MI.getDesc().TSFlags & SIInstrFlags::IsPacked; } - bool isPacked(uint32_t Opcode) const { + bool isPacked(uint16_t Opcode) const { return get(Opcode).TSFlags & SIInstrFlags::IsPacked; } @@ -546,7 +546,7 @@ public: return MI.getDesc().TSFlags & SIInstrFlags::VOP1; } - bool isVOP1(uint32_t Opcode) const { + bool isVOP1(uint16_t Opcode) const { return get(Opcode).TSFlags & SIInstrFlags::VOP1; } @@ -554,7 +554,7 @@ public: return MI.getDesc().TSFlags & SIInstrFlags::VOP2; } - bool isVOP2(uint32_t Opcode) const { + bool isVOP2(uint16_t Opcode) const { return get(Opcode).TSFlags & SIInstrFlags::VOP2; } @@ -564,13 +564,13 @@ public: static bool isVOP3(const MachineInstr &MI) { return isVOP3(MI.getDesc()); } - bool isVOP3(uint32_t Opcode) const { return isVOP3(get(Opcode)); } + bool isVOP3(uint16_t Opcode) const { return isVOP3(get(Opcode)); } static bool isSDWA(const MachineInstr &MI) { return MI.getDesc().TSFlags & SIInstrFlags::SDWA; } - bool isSDWA(uint32_t Opcode) const { + bool isSDWA(uint16_t Opcode) const { return get(Opcode).TSFlags & SIInstrFlags::SDWA; } @@ -578,7 +578,7 @@ public: return MI.getDesc().TSFlags & SIInstrFlags::VOPC; } - bool isVOPC(uint32_t Opcode) const { + bool isVOPC(uint16_t Opcode) const { return get(Opcode).TSFlags & SIInstrFlags::VOPC; } @@ -586,7 +586,7 @@ public: return MI.getDesc().TSFlags & SIInstrFlags::MUBUF; } - bool isMUBUF(uint32_t Opcode) const { + bool isMUBUF(uint16_t Opcode) const { return get(Opcode).TSFlags & SIInstrFlags::MUBUF; } @@ -594,7 +594,7 @@ public: return MI.getDesc().TSFlags & SIInstrFlags::MTBUF; } - bool isMTBUF(uint32_t Opcode) const { + bool isMTBUF(uint16_t Opcode) const { return get(Opcode).TSFlags & SIInstrFlags::MTBUF; } @@ -606,7 +606,7 @@ public: return MI.getDesc().TSFlags & SIInstrFlags::SMRD; } - bool isSMRD(uint32_t Opcode) const { + bool isSMRD(uint16_t Opcode) const { return get(Opcode).TSFlags & SIInstrFlags::SMRD; } @@ -616,7 +616,7 @@ public: return MI.getDesc().TSFlags & SIInstrFlags::DS; } - bool isDS(uint32_t Opcode) const { + bool isDS(uint16_t Opcode) const { return get(Opcode).TSFlags & SIInstrFlags::DS; } @@ -625,7 +625,7 @@ public: (MI.getDesc().TSFlags & SIInstrFlags::TENSOR_CNT); } - bool isLDSDMA(uint32_t Opcode) { + bool isLDSDMA(uint16_t Opcode) { return (isVALU(Opcode) && (isMUBUF(Opcode) || isFLAT(Opcode))) || (get(Opcode).TSFlags & SIInstrFlags::TENSOR_CNT); } @@ -634,17 +634,17 @@ public: return MI.getDesc().TSFlags & SIInstrFlags::GWS; } - bool isGWS(uint32_t Opcode) const { + bool isGWS(uint16_t Opcode) const { return get(Opcode).TSFlags & SIInstrFlags::GWS; } - bool isAlwaysGDS(uint32_t Opcode) const; + bool isAlwaysGDS(uint16_t Opcode) const; static bool isMIMG(const MachineInstr &MI) { return MI.getDesc().TSFlags & SIInstrFlags::MIMG; } - bool isMIMG(uint32_t Opcode) const { + bool isMIMG(uint16_t Opcode) const { return get(Opcode).TSFlags & SIInstrFlags::MIMG; } @@ -652,7 +652,7 @@ public: return MI.getDesc().TSFlags & SIInstrFlags::VIMAGE; } - bool isVIMAGE(uint32_t Opcode) const { + bool isVIMAGE(uint16_t Opcode) const { return get(Opcode).TSFlags & SIInstrFlags::VIMAGE; } @@ -660,7 +660,7 @@ public: return MI.getDesc().TSFlags & SIInstrFlags::VSAMPLE; } - bool isVSAMPLE(uint32_t Opcode) const { + bool isVSAMPLE(uint16_t Opcode) const { return get(Opcode).TSFlags & SIInstrFlags::VSAMPLE; } @@ -668,7 +668,7 @@ public: return MI.getDesc().TSFlags & SIInstrFlags::Gather4; } - bool isGather4(uint32_t Opcode) const { + bool isGather4(uint16_t Opcode) const { return get(Opcode).TSFlags & SIInstrFlags::Gather4; } @@ -683,7 +683,7 @@ public: return Flags & (SIInstrFlags::FlatGlobal | SIInstrFlags::FlatScratch); } - bool isSegmentSpecificFLAT(uint32_t Opcode) const { + bool isSegmentSpecificFLAT(uint16_t Opcode) const { auto Flags = get(Opcode).TSFlags; return Flags & (SIInstrFlags::FlatGlobal | SIInstrFlags::FlatScratch); } @@ -692,7 +692,7 @@ public: return MI.getDesc().TSFlags & SIInstrFlags::FlatGlobal; } - bool isFLATGlobal(uint32_t Opcode) const { + bool isFLATGlobal(uint16_t Opcode) const { return get(Opcode).TSFlags & SIInstrFlags::FlatGlobal; } @@ -700,12 +700,12 @@ public: return MI.getDesc().TSFlags & SIInstrFlags::FlatScratch; } - bool isFLATScratch(uint32_t Opcode) const { + bool isFLATScratch(uint16_t Opcode) const { return get(Opcode).TSFlags & SIInstrFlags::FlatScratch; } // Any FLAT encoded instruction, including global_* and scratch_*. - bool isFLAT(uint32_t Opcode) const { + bool isFLAT(uint16_t Opcode) const { return get(Opcode).TSFlags & SIInstrFlags::FLAT; } @@ -721,7 +721,7 @@ public: /// \returns true for FLAT instructions that can access LDS. bool mayAccessLDSThroughFlat(const MachineInstr &MI) const; - static bool isBlockLoadStore(uint32_t Opcode) { + static bool isBlockLoadStore(uint16_t Opcode) { switch (Opcode) { case AMDGPU::SI_BLOCK_SPILL_V1024_SAVE: case AMDGPU::SI_BLOCK_SPILL_V1024_RESTORE: @@ -793,7 +793,7 @@ public: Target == AMDGPU::Exp::ET_DUAL_SRC_BLEND1; } - bool isEXP(uint32_t Opcode) const { + bool isEXP(uint16_t Opcode) const { return get(Opcode).TSFlags & SIInstrFlags::EXP; } @@ -801,7 +801,7 @@ public: return MI.getDesc().TSFlags & SIInstrFlags::IsAtomicNoRet; } - bool isAtomicNoRet(uint32_t Opcode) const { + bool isAtomicNoRet(uint16_t Opcode) const { return get(Opcode).TSFlags & SIInstrFlags::IsAtomicNoRet; } @@ -809,7 +809,7 @@ public: return MI.getDesc().TSFlags & SIInstrFlags::IsAtomicRet; } - bool isAtomicRet(uint32_t Opcode) const { + bool isAtomicRet(uint16_t Opcode) const { return get(Opcode).TSFlags & SIInstrFlags::IsAtomicRet; } @@ -818,7 +818,7 @@ public: SIInstrFlags::IsAtomicNoRet); } - bool isAtomic(uint32_t Opcode) const { + bool isAtomic(uint16_t Opcode) const { return get(Opcode).TSFlags & (SIInstrFlags::IsAtomicRet | SIInstrFlags::IsAtomicNoRet); } @@ -847,7 +847,7 @@ public: return MI.getDesc().TSFlags & SIInstrFlags::WQM; } - bool isWQM(uint32_t Opcode) const { + bool isWQM(uint16_t Opcode) const { return get(Opcode).TSFlags & SIInstrFlags::WQM; } @@ -855,7 +855,7 @@ public: return MI.getDesc().TSFlags & SIInstrFlags::DisableWQM; } - bool isDisableWQM(uint32_t Opcode) const { + bool isDisableWQM(uint16_t Opcode) const { return get(Opcode).TSFlags & SIInstrFlags::DisableWQM; } @@ -870,7 +870,7 @@ public: (isSpill(MI) && isVALU(MI)); } - bool isVGPRSpill(uint32_t Opcode) const { + bool isVGPRSpill(uint16_t Opcode) const { return Opcode != AMDGPU::SI_SPILL_S32_TO_VGPR && Opcode != AMDGPU::SI_RESTORE_S32_FROM_VGPR && (isSpill(Opcode) && isVALU(Opcode)); @@ -882,13 +882,13 @@ public: (isSpill(MI) && isSALU(MI)); } - bool isSGPRSpill(uint32_t Opcode) const { + bool isSGPRSpill(uint16_t Opcode) const { return Opcode == AMDGPU::SI_SPILL_S32_TO_VGPR || Opcode == AMDGPU::SI_RESTORE_S32_FROM_VGPR || (isSpill(Opcode) && isSALU(Opcode)); } - bool isSpill(uint32_t Opcode) const { + bool isSpill(uint16_t Opcode) const { return get(Opcode).TSFlags & SIInstrFlags::Spill; } @@ -898,7 +898,7 @@ public: static bool isSpill(const MachineInstr &MI) { return isSpill(MI.getDesc()); } - static bool isWWMRegSpillOpcode(uint32_t Opcode) { + static bool isWWMRegSpillOpcode(uint16_t Opcode) { return Opcode == AMDGPU::SI_SPILL_WWM_V32_SAVE || Opcode == AMDGPU::SI_SPILL_WWM_AV32_SAVE || Opcode == AMDGPU::SI_SPILL_WWM_V32_RESTORE || @@ -914,7 +914,7 @@ public: return MI.getDesc().TSFlags & SIInstrFlags::DPP; } - bool isDPP(uint32_t Opcode) const { + bool isDPP(uint16_t Opcode) const { return get(Opcode).TSFlags & SIInstrFlags::DPP; } @@ -922,7 +922,7 @@ public: return MI.getDesc().TSFlags & SIInstrFlags::TRANS; } - bool isTRANS(uint32_t Opcode) const { + bool isTRANS(uint16_t Opcode) const { return get(Opcode).TSFlags & SIInstrFlags::TRANS; } @@ -930,7 +930,7 @@ public: return MI.getDesc().TSFlags & SIInstrFlags::VOP3P; } - bool isVOP3P(uint32_t Opcode) const { + bool isVOP3P(uint16_t Opcode) const { return get(Opcode).TSFlags & SIInstrFlags::VOP3P; } @@ -938,7 +938,7 @@ public: return MI.getDesc().TSFlags & SIInstrFlags::VINTRP; } - bool isVINTRP(uint32_t Opcode) const { + bool isVINTRP(uint16_t Opcode) const { return get(Opcode).TSFlags & SIInstrFlags::VINTRP; } @@ -948,14 +948,14 @@ public: static bool isMAI(const MachineInstr &MI) { return isMAI(MI.getDesc()); } - bool isMAI(uint32_t Opcode) const { return isMAI(get(Opcode)); } + bool isMAI(uint16_t Opcode) const { return isMAI(get(Opcode)); } static bool isMFMA(const MachineInstr &MI) { return isMAI(MI) && MI.getOpcode() != AMDGPU::V_ACCVGPR_WRITE_B32_e64 && MI.getOpcode() != AMDGPU::V_ACCVGPR_READ_B32_e64; } - bool isMFMA(uint32_t Opcode) const { + bool isMFMA(uint16_t Opcode) const { return isMAI(Opcode) && Opcode != AMDGPU::V_ACCVGPR_WRITE_B32_e64 && Opcode != AMDGPU::V_ACCVGPR_READ_B32_e64; } @@ -968,7 +968,7 @@ public: return MI.getDesc().TSFlags & SIInstrFlags::IsWMMA; } - bool isWMMA(uint32_t Opcode) const { + bool isWMMA(uint16_t Opcode) const { return get(Opcode).TSFlags & SIInstrFlags::IsWMMA; } @@ -976,7 +976,7 @@ public: return isMFMA(MI) || isWMMA(MI) || isSWMMAC(MI); } - bool isMFMAorWMMA(uint32_t Opcode) const { + bool isMFMAorWMMA(uint16_t Opcode) const { return isMFMA(Opcode) || isWMMA(Opcode) || isSWMMAC(Opcode); } @@ -984,11 +984,11 @@ public: return MI.getDesc().TSFlags & SIInstrFlags::IsSWMMAC; } - bool isSWMMAC(uint32_t Opcode) const { + bool isSWMMAC(uint16_t Opcode) const { return get(Opcode).TSFlags & SIInstrFlags::IsSWMMAC; } - bool isDOT(uint32_t Opcode) const { + bool isDOT(uint16_t Opcode) const { return get(Opcode).TSFlags & SIInstrFlags::IsDOT; } @@ -1002,7 +1002,7 @@ public: return MI.getDesc().TSFlags & SIInstrFlags::LDSDIR; } - bool isLDSDIR(uint32_t Opcode) const { + bool isLDSDIR(uint16_t Opcode) const { return get(Opcode).TSFlags & SIInstrFlags::LDSDIR; } @@ -1010,7 +1010,7 @@ public: return MI.getDesc().TSFlags & SIInstrFlags::VINTERP; } - bool isVINTERP(uint32_t Opcode) const { + bool isVINTERP(uint16_t Opcode) const { return get(Opcode).TSFlags & SIInstrFlags::VINTERP; } @@ -1030,7 +1030,7 @@ public: return MI.getDesc().TSFlags & SIInstrFlags::ASYNC_CNT; } - bool usesASYNC_CNT(uint32_t Opcode) const { + bool usesASYNC_CNT(uint16_t Opcode) const { return get(Opcode).TSFlags & SIInstrFlags::ASYNC_CNT; } @@ -1050,7 +1050,7 @@ public: return MI.getDesc().TSFlags & SIInstrFlags::SCALAR_STORE; } - bool isScalarStore(uint32_t Opcode) const { + bool isScalarStore(uint16_t Opcode) const { return get(Opcode).TSFlags & SIInstrFlags::SCALAR_STORE; } @@ -1058,7 +1058,7 @@ public: return MI.getDesc().TSFlags & SIInstrFlags::FIXED_SIZE; } - bool isFixedSize(uint32_t Opcode) const { + bool isFixedSize(uint16_t Opcode) const { return get(Opcode).TSFlags & SIInstrFlags::FIXED_SIZE; } @@ -1066,7 +1066,7 @@ public: return MI.getDesc().TSFlags & SIInstrFlags::FPClamp; } - bool hasFPClamp(uint32_t Opcode) const { + bool hasFPClamp(uint16_t Opcode) const { return get(Opcode).TSFlags & SIInstrFlags::FPClamp; } @@ -1086,7 +1086,7 @@ public: return MI.getDesc().TSFlags & SIInstrFlags::FPDPRounding; } - bool usesFPDPRounding(uint32_t Opcode) const { + bool usesFPDPRounding(uint16_t Opcode) const { return get(Opcode).TSFlags & SIInstrFlags::FPDPRounding; } @@ -1094,7 +1094,7 @@ public: return MI.getDesc().TSFlags & SIInstrFlags::FPAtomic; } - bool isFPAtomic(uint32_t Opcode) const { + bool isFPAtomic(uint16_t Opcode) const { return get(Opcode).TSFlags & SIInstrFlags::FPAtomic; } @@ -1139,7 +1139,7 @@ public: return MI.getDesc().TSFlags & SIInstrFlags::TiedSourceNotRead; } - bool doesNotReadTiedSource(uint32_t Opcode) const { + bool doesNotReadTiedSource(uint16_t Opcode) const { return get(Opcode).TSFlags & SIInstrFlags::TiedSourceNotRead; } @@ -1382,7 +1382,7 @@ public: /// Return the size in bytes of the operand OpNo on the given // instruction opcode. - unsigned getOpSize(uint32_t Opcode, unsigned OpNo) const { + unsigned getOpSize(uint16_t Opcode, unsigned OpNo) const { const MCOperandInfo &OpInfo = get(Opcode).operands()[OpNo]; if (OpInfo.RegClass == -1) { @@ -1737,86 +1737,86 @@ bool execMayBeModifiedBeforeAnyUse(const MachineRegisterInfo &MRI, namespace AMDGPU { LLVM_READONLY - int64_t getVOPe64(uint32_t Opcode); + int getVOPe64(uint16_t Opcode); LLVM_READONLY - int64_t getVOPe32(uint32_t Opcode); + int getVOPe32(uint16_t Opcode); LLVM_READONLY - int64_t getSDWAOp(uint32_t Opcode); + int getSDWAOp(uint16_t Opcode); LLVM_READONLY - int64_t getDPPOp32(uint32_t Opcode); + int getDPPOp32(uint16_t Opcode); LLVM_READONLY - int64_t getDPPOp64(uint32_t Opcode); + int getDPPOp64(uint16_t Opcode); LLVM_READONLY - int64_t getBasicFromSDWAOp(uint32_t Opcode); + int getBasicFromSDWAOp(uint16_t Opcode); LLVM_READONLY - int64_t getCommuteRev(uint32_t Opcode); + int getCommuteRev(uint16_t Opcode); LLVM_READONLY - int64_t getCommuteOrig(uint32_t Opcode); + int getCommuteOrig(uint16_t Opcode); LLVM_READONLY - int64_t getAddr64Inst(uint32_t Opcode); + int getAddr64Inst(uint16_t Opcode); /// Check if \p Opcode is an Addr64 opcode. /// /// \returns \p Opcode if it is an Addr64 opcode, otherwise -1. LLVM_READONLY - int64_t getIfAddr64Inst(uint32_t Opcode); + int getIfAddr64Inst(uint16_t Opcode); LLVM_READONLY - int64_t getSOPKOp(uint32_t Opcode); + int getSOPKOp(uint16_t Opcode); /// \returns SADDR form of a FLAT Global instruction given an \p Opcode /// of a VADDR form. LLVM_READONLY - int64_t getGlobalSaddrOp(uint32_t Opcode); + int getGlobalSaddrOp(uint16_t Opcode); /// \returns VADDR form of a FLAT Global instruction given an \p Opcode /// of a SADDR form. LLVM_READONLY - int64_t getGlobalVaddrOp(uint32_t Opcode); + int getGlobalVaddrOp(uint16_t Opcode); LLVM_READONLY - int64_t getVCMPXNoSDstOp(uint32_t Opcode); + int getVCMPXNoSDstOp(uint16_t Opcode); /// \returns ST form with only immediate offset of a FLAT Scratch instruction /// given an \p Opcode of an SS (SADDR) form. LLVM_READONLY - int64_t getFlatScratchInstSTfromSS(uint32_t Opcode); + int getFlatScratchInstSTfromSS(uint16_t Opcode); /// \returns SV (VADDR) form of a FLAT Scratch instruction given an \p Opcode /// of an SVS (SADDR + VADDR) form. LLVM_READONLY - int64_t getFlatScratchInstSVfromSVS(uint32_t Opcode); + int getFlatScratchInstSVfromSVS(uint16_t Opcode); /// \returns SS (SADDR) form of a FLAT Scratch instruction given an \p Opcode /// of an SV (VADDR) form. LLVM_READONLY - int64_t getFlatScratchInstSSfromSV(uint32_t Opcode); + int getFlatScratchInstSSfromSV(uint16_t Opcode); /// \returns SV (VADDR) form of a FLAT Scratch instruction given an \p Opcode /// of an SS (SADDR) form. LLVM_READONLY - int64_t getFlatScratchInstSVfromSS(uint32_t Opcode); + int getFlatScratchInstSVfromSS(uint16_t Opcode); /// \returns earlyclobber version of a MAC MFMA is exists. LLVM_READONLY - int64_t getMFMAEarlyClobberOp(uint32_t Opcode); + int getMFMAEarlyClobberOp(uint16_t Opcode); /// \returns Version of an MFMA instruction which uses AGPRs for srcC and /// vdst, given an \p Opcode of an MFMA which uses VGPRs for srcC/vdst. LLVM_READONLY - int64_t getMFMASrcCVDstAGPROp(uint32_t Opcode); + int getMFMASrcCVDstAGPROp(uint16_t Opcode); /// \returns v_cmpx version of a v_cmp instruction. LLVM_READONLY - int64_t getVCMPXOpFromVCMP(uint32_t Opcode); + int getVCMPXOpFromVCMP(uint16_t Opcode); const uint64_t RSRC_DATA_FORMAT = 0xf00000000000LL; const uint64_t RSRC_ELEMENT_SIZE_SHIFT = (32 + 19); diff --git a/llvm/lib/Target/AMDGPU/SIPreEmitPeephole.cpp b/llvm/lib/Target/AMDGPU/SIPreEmitPeephole.cpp index 73aab4e721d1..3edc98f21a07 100644 --- a/llvm/lib/Target/AMDGPU/SIPreEmitPeephole.cpp +++ b/llvm/lib/Target/AMDGPU/SIPreEmitPeephole.cpp @@ -66,11 +66,11 @@ private: // this transformation. void performF32Unpacking(MachineInstr &I); // Select corresponding unpacked instruction - uint32_t mapToUnpackedOpcode(MachineInstr &I); + uint16_t mapToUnpackedOpcode(MachineInstr &I); // Creates the unpacked instruction to be inserted. Adds source modifiers to // the unpacked instructions based on the source modifiers in the packed // instruction. - MachineInstrBuilder createUnpackedMI(MachineInstr &I, uint32_t UnpackedOpcode, + MachineInstrBuilder createUnpackedMI(MachineInstr &I, uint16_t UnpackedOpcode, bool IsHiBits); // Process operands/source modifiers from packed instructions and insert the // appropriate source modifers and operands into the unpacked instructions. @@ -508,7 +508,7 @@ bool SIPreEmitPeephole::canUnpackingClobberRegister(const MachineInstr &MI) { return false; } -uint32_t SIPreEmitPeephole::mapToUnpackedOpcode(MachineInstr &I) { +uint16_t SIPreEmitPeephole::mapToUnpackedOpcode(MachineInstr &I) { unsigned Opcode = I.getOpcode(); // Use 64 bit encoding to allow use of VOP3 instructions. // VOP3 e64 instructions allow source modifiers @@ -521,7 +521,7 @@ uint32_t SIPreEmitPeephole::mapToUnpackedOpcode(MachineInstr &I) { case AMDGPU::V_PK_FMA_F32: return AMDGPU::V_FMA_F32_e64; default: - return std::numeric_limits::max(); + return std::numeric_limits::max(); } llvm_unreachable("Fully covered switch"); } @@ -592,9 +592,9 @@ void SIPreEmitPeephole::collectUnpackingCandidates( for (auto I = std::next(BeginMI.getIterator()); I != E; ++I) { MachineInstr &Instr = *I; - uint32_t UnpackedOpCode = mapToUnpackedOpcode(Instr); + uint16_t UnpackedOpCode = mapToUnpackedOpcode(Instr); bool IsUnpackable = - !(UnpackedOpCode == std::numeric_limits::max()); + !(UnpackedOpCode == std::numeric_limits::max()); if (Instr.isMetaInstruction()) continue; if ((Instr.isTerminator()) || @@ -642,8 +642,8 @@ void SIPreEmitPeephole::collectUnpackingCandidates( void SIPreEmitPeephole::performF32Unpacking(MachineInstr &I) { const MachineOperand &DstOp = I.getOperand(0); - uint32_t UnpackedOpcode = mapToUnpackedOpcode(I); - assert(UnpackedOpcode != std::numeric_limits::max() && + uint16_t UnpackedOpcode = mapToUnpackedOpcode(I); + assert(UnpackedOpcode != std::numeric_limits::max() && "Unsupported Opcode"); MachineInstrBuilder Op0LOp1L = @@ -666,7 +666,7 @@ void SIPreEmitPeephole::performF32Unpacking(MachineInstr &I) { } MachineInstrBuilder SIPreEmitPeephole::createUnpackedMI(MachineInstr &I, - uint32_t UnpackedOpcode, + uint16_t UnpackedOpcode, bool IsHiBits) { MachineBasicBlock &MBB = *I.getParent(); const DebugLoc &DL = I.getDebugLoc(); diff --git a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp index cc6e67cd1ec2..c9f84708d8b3 100644 --- a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp +++ b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp @@ -355,8 +355,8 @@ unsigned getAddrSizeMIMGOp(const MIMGBaseOpcodeInfo *BaseOpcode, } struct MUBUFInfo { - uint32_t Opcode; - uint32_t BaseOpcode; + uint16_t Opcode; + uint16_t BaseOpcode; uint8_t elements; bool has_vaddr; bool has_srsrc; @@ -366,8 +366,8 @@ struct MUBUFInfo { }; struct MTBUFInfo { - uint32_t Opcode; - uint32_t BaseOpcode; + uint16_t Opcode; + uint16_t BaseOpcode; uint8_t elements; bool has_vaddr; bool has_srsrc; @@ -375,25 +375,25 @@ struct MTBUFInfo { }; struct SMInfo { - uint32_t Opcode; + uint16_t Opcode; bool IsBuffer; }; struct VOPInfo { - uint32_t Opcode; + uint16_t Opcode; bool IsSingle; }; struct VOPC64DPPInfo { - uint32_t Opcode; + uint16_t Opcode; }; struct VOPCDPPAsmOnlyInfo { - uint32_t Opcode; + uint16_t Opcode; }; struct VOP3CDPPAsmOnlyInfo { - uint32_t Opcode; + uint16_t Opcode; }; struct VOPDComponentInfo { @@ -404,7 +404,7 @@ struct VOPDComponentInfo { }; struct VOPDInfo { - uint32_t Opcode; + uint16_t Opcode; uint16_t OpX; uint16_t OpY; uint16_t Subtarget; @@ -412,7 +412,7 @@ struct VOPDInfo { }; struct VOPTrue16Info { - uint32_t Opcode; + uint16_t Opcode; bool IsTrue16; }; @@ -420,12 +420,12 @@ struct VOPTrue16Info { #define GET_FP4FP8DstByteSelTable_IMPL struct DPMACCInstructionInfo { - uint32_t Opcode; + uint16_t Opcode; bool IsDPMACCInstruction; }; struct FP4FP8DstByteSelInfo { - uint32_t Opcode; + uint16_t Opcode; bool HasFP8DstByteSel; bool HasFP4DstByteSel; }; @@ -808,7 +808,7 @@ unsigned mapWMMA3AddrTo2AddrOpcode(unsigned Opc) { // Wrapper for Tablegen'd function. enum Subtarget is not defined in any // header files, so we need to wrap it in a function that takes unsigned // instead. -int64_t getMCOpcode(uint32_t Opcode, unsigned Gen) { +int getMCOpcode(uint16_t Opcode, unsigned Gen) { return getMCOpcodeGen(Opcode, static_cast(Gen)); } diff --git a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h index ab2d75656b29..0ecec79d08a3 100644 --- a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h +++ b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h @@ -98,7 +98,7 @@ struct GcnBufferFormatInfo { }; struct MAIInstInfo { - uint32_t Opcode; + uint16_t Opcode; bool is_dgemm; bool is_gfx940_xdl; }; @@ -121,7 +121,7 @@ struct True16D16Info { }; struct WMMAInstInfo { - uint32_t Opcode; + uint16_t Opcode; bool is_wmma_xdl; }; @@ -416,7 +416,7 @@ inline bool hasNamedOperand(uint64_t Opcode, OpName NamedIdx) { } LLVM_READONLY -int64_t getSOPPWithRelaxation(uint32_t Opcode); +int getSOPPWithRelaxation(uint16_t Opcode); struct MIMGBaseOpcodeInfo { MIMGBaseOpcode BaseOpcode; @@ -522,8 +522,8 @@ unsigned getAddrSizeMIMGOp(const MIMGBaseOpcodeInfo *BaseOpcode, bool IsG16Supported); struct MIMGInfo { - uint32_t Opcode; - uint32_t BaseOpcode; + uint16_t Opcode; + uint16_t BaseOpcode; uint8_t MIMGEncoding; uint8_t VDataDwords; uint8_t VAddrDwords; @@ -646,7 +646,7 @@ const GcnBufferFormatInfo *getGcnBufferFormatInfo(uint8_t Format, const MCSubtargetInfo &STI); LLVM_READONLY -int64_t getMCOpcode(uint32_t Opcode, unsigned Gen); +int getMCOpcode(uint16_t Opcode, unsigned Gen); LLVM_READONLY unsigned getVOPDOpcode(unsigned Opc, bool VOPD3); diff --git a/llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp b/llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp index afa1345fdb46..a942d2f9c7e8 100644 --- a/llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp +++ b/llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp @@ -78,7 +78,7 @@ bool PPCDispatchGroupSBHazardRecognizer::isBCTRAfterSet(SUnit *SU) { } // FIXME: Remove this when we don't need this: -namespace llvm { namespace PPC { extern int64_t getNonRecordFormOpcode(uint32_t); } } +namespace llvm { namespace PPC { extern int getNonRecordFormOpcode(uint16_t); } } // FIXME: A lot of code in PPCDispatchGroupSBHazardRecognizer is P7 specific. diff --git a/llvm/lib/Target/PowerPC/PPCVSXFMAMutate.cpp b/llvm/lib/Target/PowerPC/PPCVSXFMAMutate.cpp index f33d4bf89381..7e3ea606087b 100644 --- a/llvm/lib/Target/PowerPC/PPCVSXFMAMutate.cpp +++ b/llvm/lib/Target/PowerPC/PPCVSXFMAMutate.cpp @@ -47,7 +47,7 @@ static cl::opt DisableVSXFMAMutate( #define DEBUG_TYPE "ppc-vsx-fma-mutate" namespace llvm { namespace PPC { - int64_t getAltVSXFMAOpcode(uint32_t Opcode); + int getAltVSXFMAOpcode(uint16_t Opcode); } } namespace { diff --git a/llvm/lib/Target/SystemZ/SystemZInstrInfo.h b/llvm/lib/Target/SystemZ/SystemZInstrInfo.h index 8e834c74f503..29ae9e0ed80e 100644 --- a/llvm/lib/Target/SystemZ/SystemZInstrInfo.h +++ b/llvm/lib/Target/SystemZ/SystemZInstrInfo.h @@ -159,8 +159,8 @@ enum FusedCompareType { } // end namespace SystemZII namespace SystemZ { -int64_t getTwoOperandOpcode(uint32_t Opcode); -int64_t getTargetMemOpcode(uint32_t Opcode); +int getTwoOperandOpcode(uint16_t Opcode); +int getTargetMemOpcode(uint16_t Opcode); // Return a version of comparison CC mask CCMask in which the LT and GT // actions are swapped. diff --git a/llvm/lib/Target/WebAssembly/TargetInfo/WebAssemblyTargetInfo.h b/llvm/lib/Target/WebAssembly/TargetInfo/WebAssemblyTargetInfo.h index bbe3d4a89adc..741cc002f9e2 100644 --- a/llvm/lib/Target/WebAssembly/TargetInfo/WebAssemblyTargetInfo.h +++ b/llvm/lib/Target/WebAssembly/TargetInfo/WebAssemblyTargetInfo.h @@ -14,8 +14,6 @@ #ifndef LLVM_LIB_TARGET_WEBASSEMBLY_TARGETINFO_WEBASSEMBLYTARGETINFO_H #define LLVM_LIB_TARGET_WEBASSEMBLY_TARGETINFO_WEBASSEMBLYTARGETINFO_H -#include - namespace llvm { class Target; @@ -25,9 +23,9 @@ Target &getTheWebAssemblyTarget64(); namespace WebAssembly { -int64_t getStackOpcode(uint32_t Opcode); -int64_t getRegisterOpcode(uint32_t Opcode); -int64_t getWasm64Opcode(uint32_t Opcode); +int getStackOpcode(unsigned short Opcode); +int getRegisterOpcode(unsigned short Opcode); +int getWasm64Opcode(unsigned short Opcode); } // namespace WebAssembly diff --git a/llvm/test/TableGen/CPtrWildcard.td b/llvm/test/TableGen/CPtrWildcard.td index 1f1d82e96cde..6e09fce70d83 100644 --- a/llvm/test/TableGen/CPtrWildcard.td +++ b/llvm/test/TableGen/CPtrWildcard.td @@ -7,20 +7,20 @@ // CHECK-NEXT: /* 0*/ OPC_CheckOpcode, TARGET_VAL(ISD::INTRINSIC_WO_CHAIN), // CHECK-NEXT:/* 3*/ OPC_CheckChild0Integer, [[#]], // CHECK-NEXT:/* 5*/ OPC_RecordChild1, // #0 = $src -// CHECK-NEXT:/* 6*/ OPC_Scope /*2 children */, 11, // ->19 +// CHECK-NEXT:/* 6*/ OPC_Scope /*2 children */, 9, // ->17 // CHECK-NEXT:/* 8*/ OPC_CheckChild1Type, /*MVT::c64*/4|128,2/*260*/, -// CHECK-NEXT:/* 11*/ OPC_MorphNodeTo1None, TARGET_OUTPUT_VAL(MyTarget::C64_TO_I64), +// CHECK-NEXT:/* 11*/ OPC_MorphNodeTo1None, TARGET_VAL(MyTarget::C64_TO_I64), // CHECK-NEXT: MVT::i64, 1/*#Ops*/, /*OperandList*/0, // Ops = #0 // CHECK-NEXT: // Src: (intrinsic_wo_chain:{ *:[i64] } [[#]]:{ *:[iPTR] }, c64:{ *:[c64] }:$src) - Complexity = 8 // CHECK-NEXT: // Dst: (C64_TO_I64:{ *:[i64] } ?:{ *:[c64] }:$src) -// CHECK-NEXT:/* 19*/ /*Scope*/ 11, // ->31 -// CHECK-NEXT:/* 20*/ OPC_CheckChild1Type, /*MVT::c128*/5|128,2/*261*/, -// CHECK-NEXT:/* 23*/ OPC_MorphNodeTo1None, TARGET_OUTPUT_VAL(MyTarget::C128_TO_I64), +// CHECK-NEXT:/* 17*/ /*Scope*/ 9, // ->27 +// CHECK-NEXT:/* 18*/ OPC_CheckChild1Type, /*MVT::c128*/5|128,2/*261*/, +// CHECK-NEXT:/* 21*/ OPC_MorphNodeTo1None, TARGET_VAL(MyTarget::C128_TO_I64), // CHECK-NEXT: MVT::i64, 1/*#Ops*/, /*OperandList*/0, // Ops = #0 // CHECK-NEXT: // Src: (intrinsic_wo_chain:{ *:[i64] } [[#]]:{ *:[iPTR] }, c128:{ *:[c128] }:$src) - Complexity = 8 // CHECK-NEXT: // Dst: (C128_TO_I64:{ *:[i64] } ?:{ *:[c128] }:$src) -// CHECK-NEXT:/* 31*/ 0, // End of Scope -// CHECK-NEXT: }; // Total Array size is 32 bytes +// CHECK-NEXT:/* 27*/ 0, // End of Scope +// CHECK-NEXT: }; // Total Array size is 28 bytes // CHECK: static const uint8_t OperandLists[] = { // CHECK-NEXT: /* 0 */ 0, diff --git a/llvm/test/TableGen/DAGDefaultOps.td b/llvm/test/TableGen/DAGDefaultOps.td index 2325f235fba7..78cc58fcf979 100644 --- a/llvm/test/TableGen/DAGDefaultOps.td +++ b/llvm/test/TableGen/DAGDefaultOps.td @@ -77,20 +77,20 @@ def MulIRRPat : Pat<(mul i32:$x, i32:$y), (MulIRR Reg:$x, Reg:$y)>; // ADD-NEXT: OPC_RecordChild0 // ADD-NEXT: OPC_RecordChild1 // ADD-NEXT: OPC_EmitIntegerI32, 0 -// ADD-NEXT: OPC_MorphNodeTo1None, TARGET_OUTPUT_VAL(::AddRRI) +// ADD-NEXT: OPC_MorphNodeTo1None, TARGET_VAL(::AddRRI) // ADDINT: SwitchOpcode{{.*}}TARGET_VAL(ISD::INTRINSIC_WO_CHAIN) // ADDINT-NEXT: OPC_CheckChild0Integer // ADDINT-NEXT: OPC_RecordChild1 // ADDINT-NEXT: OPC_RecordChild2 // ADDINT-NEXT: OPC_EmitIntegerI32, 1 -// ADDINT-NEXT: OPC_MorphNodeTo1None, TARGET_OUTPUT_VAL(::AddRRI) +// ADDINT-NEXT: OPC_MorphNodeTo1None, TARGET_VAL(::AddRRI) // SUB: SwitchOpcode{{.*}}TARGET_VAL(ISD::SUB) // SUB-NEXT: OPC_RecordChild0 // SUB-NEXT: OPC_RecordChild1 // SUB-NEXT: OPC_EmitIntegerI32, 0 -// SUB-NEXT: OPC_MorphNodeTo1None, TARGET_OUTPUT_VAL(::SubRRI) +// SUB-NEXT: OPC_MorphNodeTo1None, TARGET_VAL(::SubRRI) // MULINT: SwitchOpcode{{.*}}TARGET_VAL(ISD::INTRINSIC_W_CHAIN) // MULINT-NEXT: OPC_RecordNode @@ -99,10 +99,10 @@ def MulIRRPat : Pat<(mul i32:$x, i32:$y), (MulIRR Reg:$x, Reg:$y)>; // MULINT-NEXT: OPC_RecordChild3 // MULINT-NEXT: OPC_RecordChild4 // MULINT-NEXT: OPC_EmitMergeInputChains -// MULINT-NEXT: OPC_MorphNodeTo1Chain, TARGET_OUTPUT_VAL(::MulRRI) +// MULINT-NEXT: OPC_MorphNodeTo1Chain, TARGET_VAL(::MulRRI) // MUL: SwitchOpcode{{.*}}TARGET_VAL(ISD::MUL) // MUL-NEXT: OPC_EmitIntegerI32, 0 // MUL-NEXT: OPC_RecordChild0 // MUL-NEXT: OPC_RecordChild1 -// MUL-NEXT: OPC_MorphNodeTo1Chain, TARGET_OUTPUT_VAL(::MulRRI) +// MUL-NEXT: OPC_MorphNodeTo1Chain, TARGET_VAL(::MulRRI) diff --git a/llvm/test/TableGen/GlobalISelCombinerEmitter/builtins/match-table-replacerreg.td b/llvm/test/TableGen/GlobalISelCombinerEmitter/builtins/match-table-replacerreg.td index 1e04dc1cc8fa..850c04130b86 100644 --- a/llvm/test/TableGen/GlobalISelCombinerEmitter/builtins/match-table-replacerreg.td +++ b/llvm/test/TableGen/GlobalISelCombinerEmitter/builtins/match-table-replacerreg.td @@ -50,7 +50,7 @@ def MyCombiner: GICombiner<"GenMyCombiner", [ // CHECK-NEXT: GIM_CheckIsSafeToFold, /*NumInsns*/1, // CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, // CHECK-NEXT: // Combiner Rule #1: ReplaceTemp -// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode4(TargetOpcode::G_UNMERGE_VALUES), +// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::G_UNMERGE_VALUES), // CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // a // CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast(RegState::Define)), // CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // y diff --git a/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-imms.td b/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-imms.td index 69346640c723..e0b802447ea2 100644 --- a/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-imms.td +++ b/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-imms.td @@ -46,7 +46,7 @@ def MyCombiner: GICombiner<"GenMyCombiner", [ // CHECK-NEXT: // No operand predicates // CHECK-NEXT: GIM_CheckConstantInt8, /*MI*/0, /*Op*/1, 0, // CHECK-NEXT: // Combiner Rule #0: InstTest0 -// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode4(TargetOpcode::COPY), +// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), // CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // a // CHECK-NEXT: GIR_AddImm8, /*InsnID*/0, /*Imm*/0, // CHECK-NEXT: GIR_EraseRootFromParent_Done, @@ -60,7 +60,7 @@ def MyCombiner: GICombiner<"GenMyCombiner", [ // CHECK-NEXT: // No operand predicates // CHECK-NEXT: GIM_CheckLiteralInt, /*MI*/0, /*Op*/1, GIMT_Encode8(0), // CHECK-NEXT: // Combiner Rule #2: CImmInstTest1 -// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode4(TargetOpcode::G_CONSTANT), +// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::G_CONSTANT), // CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // a // CHECK-NEXT: GIR_AddCImm, /*InsnID*/0, /*Type*/GILLT_s32, /*Imm*/GIMT_Encode8(42), // CHECK-NEXT: GIR_EraseRootFromParent_Done, @@ -76,7 +76,7 @@ def MyCombiner: GICombiner<"GenMyCombiner", [ // CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, // CHECK-NEXT: GIR_BuildConstant, /*TempRegID*/0, /*Val*/GIMT_Encode8(0), // CHECK-NEXT: // Combiner Rule #1: InstTest1 -// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode4(TargetOpcode::COPY), +// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), // CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // a // CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, // CHECK-NEXT: GIR_EraseRootFromParent_Done, diff --git a/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-intrinsics.td b/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-intrinsics.td index e0d0438b4893..22cb105355ab 100644 --- a/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-intrinsics.td +++ b/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-intrinsics.td @@ -43,10 +43,10 @@ def MyCombiner: GICombiner<"GenMyCombiner", [ // CHECK-NEXT: GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, // CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, // CHECK-NEXT: // Combiner Rule #0: IntrinTest0 -// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode4(TargetOpcode::G_INTRINSIC), +// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::G_INTRINSIC), // CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast(RegState::Define)), // CHECK-NEXT: GIR_AddIntrinsicID, /*MI*/0, GIMT_Encode2(Intrinsic::0in_1out), -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode4(TargetOpcode::G_INTRINSIC), +// CHECK-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::G_INTRINSIC), // CHECK-NEXT: GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, // a // CHECK-NEXT: GIR_AddIntrinsicID, /*MI*/1, GIMT_Encode2(Intrinsic::1in_1out), // CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, @@ -64,11 +64,11 @@ def MyCombiner: GICombiner<"GenMyCombiner", [ // CHECK-NEXT: // No operand predicates // CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, // CHECK-NEXT: // Combiner Rule #1: SpecialIntrins -// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode4(TargetOpcode::G_INTRINSIC_CONVERGENT), +// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::G_INTRINSIC_CONVERGENT), // CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast(RegState::Define)), // CHECK-NEXT: GIR_AddIntrinsicID, /*MI*/0, GIMT_Encode2(Intrinsic::convergent_1in_1out), // CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/2, // b -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode4(TargetOpcode::G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS), +// CHECK-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS), // CHECK-NEXT: GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, // a // CHECK-NEXT: GIR_AddIntrinsicID, /*MI*/1, GIMT_Encode2(Intrinsic::convergent_sideeffects_1in_1out), // CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, @@ -78,6 +78,6 @@ def MyCombiner: GICombiner<"GenMyCombiner", [ // CHECK-NEXT: GIM_Reject, // CHECK-NEXT: // Label 2: @[[L132]] // CHECK-NEXT: GIM_Reject, -// CHECK-NEXT: }; // Size: 133 bytes +// CHECK-NEXT: }; // Size: 125 bytes // CHECK-NEXT: return MatchTable0; // CHECK-NEXT: } diff --git a/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-miflags.td b/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-miflags.td index 65c2304b6473..24864e8aef45 100644 --- a/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-miflags.td +++ b/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-miflags.td @@ -17,7 +17,7 @@ def MyCombiner: GICombiner<"GenMyCombiner", [MIFlagsTest]>; // CHECK: const uint8_t *GenMyCombiner::getMatchTable() const { // CHECK-NEXT: constexpr static uint8_t MatchTable0[] = { -// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 0*/ GIMT_Encode4(65), // Rule ID 0 // +// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 0*/ GIMT_Encode4(63), // Rule ID 0 // // CHECK-NEXT: GIM_CheckSimplePredicate, GIMT_Encode2(GICXXPred_Simple_IsRule0Enabled), // CHECK-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_SEXT), // CHECK-NEXT: // MIs[0] dst @@ -31,7 +31,7 @@ def MyCombiner: GICombiner<"GenMyCombiner", [MIFlagsTest]>; // CHECK-NEXT: // No operand predicates // CHECK-NEXT: GIM_CheckIsSafeToFold, /*NumInsns*/1, // CHECK-NEXT: // Combiner Rule #0: MIFlagsTest -// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode4(TargetOpcode::G_MUL), +// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::G_MUL), // CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // dst // CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src // CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src @@ -39,7 +39,7 @@ def MyCombiner: GICombiner<"GenMyCombiner", [MIFlagsTest]>; // CHECK-NEXT: GIR_SetMIFlags, /*InsnID*/0, GIMT_Encode4(MachineInstr::FmReassoc), // CHECK-NEXT: GIR_UnsetMIFlags, /*InsnID*/0, GIMT_Encode4(MachineInstr::FmNsz | MachineInstr::FmArcp), // CHECK-NEXT: GIR_EraseRootFromParent_Done, -// CHECK-NEXT: // Label 0: @65 +// CHECK-NEXT: // Label 0: @63 // CHECK-NEXT: GIM_Reject, // CHECK-NEXT: }; // CHECK-NEXT: return MatchTable0; diff --git a/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-operand-types.td b/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-operand-types.td index 3d47c5cebca6..e359ddf73cd8 100644 --- a/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-operand-types.td +++ b/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-operand-types.td @@ -21,7 +21,7 @@ def MyCombiner: GICombiner<"GenMyCombiner", [ // CHECK: const uint8_t *GenMyCombiner::getMatchTable() const { // CHECK-NEXT: constexpr static uint8_t MatchTable0[] = { -// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 0*/ GIMT_Encode4(77), // Rule ID 0 // +// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 0*/ GIMT_Encode4(73), // Rule ID 0 // // CHECK-NEXT: GIM_CheckSimplePredicate, GIMT_Encode2(GICXXPred_Simple_IsRule0Enabled), // CHECK-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_MUL), // CHECK-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s8, @@ -35,17 +35,17 @@ def MyCombiner: GICombiner<"GenMyCombiner", [ // CHECK-NEXT: GIM_CheckIsSafeToFold, /*NumInsns*/1, // CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, // CHECK-NEXT: // Combiner Rule #0: InstTest0 -// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode4(TargetOpcode::G_ADD), +// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::G_ADD), // CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast(RegState::Define)), // CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/1, // b // CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // c -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode4(TargetOpcode::G_ADD), +// CHECK-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::G_ADD), // CHECK-NEXT: GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, // a // CHECK-NEXT: GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // b // CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, // CHECK-NEXT: GIR_EraseRootFromParent_Done, -// CHECK-NEXT: // Label 0: @77 +// CHECK-NEXT: // Label 0: @73 // CHECK-NEXT: GIM_Reject, -// CHECK-NEXT: }; // Size: 78 bytes +// CHECK-NEXT: }; // Size: 74 bytes // CHECK-NEXT: return MatchTable0; // CHECK-NEXT: } diff --git a/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-patfrag-root.td b/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-patfrag-root.td index 3294952e4ba3..5a8b51dfc832 100644 --- a/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-patfrag-root.td +++ b/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-patfrag-root.td @@ -42,7 +42,7 @@ def MyCombiner: GICombiner<"GenMyCombiner", [ // CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, // CHECK-NEXT: GIR_BuildConstant, /*TempRegID*/0, /*Val*/GIMT_Encode8(0), // CHECK-NEXT: // Combiner Rule #0: Test0 @ [__Test0_match_0[1]] -// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode4(TargetOpcode::COPY), +// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), // CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // root // CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, // CHECK-NEXT: GIR_EraseRootFromParent_Done, @@ -62,7 +62,7 @@ def MyCombiner: GICombiner<"GenMyCombiner", [ // CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, // CHECK-NEXT: GIR_BuildConstant, /*TempRegID*/0, /*Val*/GIMT_Encode8(0), // CHECK-NEXT: // Combiner Rule #0: Test0 @ [__Test0_match_0[0]] -// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode4(TargetOpcode::COPY), +// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), // CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // root // CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, // CHECK-NEXT: GIR_EraseRootFromParent_Done, @@ -78,7 +78,7 @@ def MyCombiner: GICombiner<"GenMyCombiner", [ // CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, // CHECK-NEXT: GIR_BuildConstant, /*TempRegID*/0, /*Val*/GIMT_Encode8(0), // CHECK-NEXT: // Combiner Rule #0: Test0 @ [__Test0_match_0[2]] -// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode4(TargetOpcode::COPY), +// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), // CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // root // CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, // CHECK-NEXT: GIR_EraseRootFromParent_Done, diff --git a/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-temp-defs.td b/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-temp-defs.td index 2f4e7516319b..23794fbc510a 100644 --- a/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-temp-defs.td +++ b/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-temp-defs.td @@ -36,21 +36,21 @@ def MyCombiner: GICombiner<"GenMyCombiner", [ ]>; // CHECK: // Combiner Rule #0: Test0 -// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode4(TargetOpcode::G_UDIVREM), +// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::G_UDIVREM), // CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast(RegState::Define)), // CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // dst // CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/1, // lhs // CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/2, // rhs // CHECK: // Combiner Rule #1: Test1 -// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode4(TargetOpcode::G_UDIVREM), +// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::G_UDIVREM), // CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // dst // CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast(RegState::Define)), // CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/1, // lhs // CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/2, // rhs // CHECK: // Combiner Rule #2: Test2 -// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode4(TargetOpcode::G_ADD), +// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::G_ADD), // CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast(RegState::Define)), // CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, // CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/1, // lhs diff --git a/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-typeof.td b/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-typeof.td index a1431fde01be..aca7e5ef42fd 100644 --- a/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-typeof.td +++ b/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-typeof.td @@ -16,7 +16,7 @@ def Test0 : GICombineRule< // CHECK: const uint8_t *GenMyCombiner::getMatchTable() const { // CHECK-NEXT: constexpr static uint8_t MatchTable0[] = { -// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 0*/ GIMT_Encode4(78), // Rule ID 0 // +// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 0*/ GIMT_Encode4(74), // Rule ID 0 // // CHECK-NEXT: GIM_CheckSimplePredicate, GIMT_Encode2(GICXXPred_Simple_IsRule0Enabled), // CHECK-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_MUL), // CHECK-NEXT: // MIs[0] dst @@ -29,17 +29,17 @@ def Test0 : GICombineRule< // CHECK-NEXT: GIR_BuildConstant, /*TempRegID*/1, /*Val*/GIMT_Encode8(0), // CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/255, // CHECK-NEXT: // Combiner Rule #0: Test0 -// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode4(TargetOpcode::G_CONSTANT), +// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::G_CONSTANT), // CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast(RegState::Define)), // CHECK-NEXT: GIR_AddCImm, /*InsnID*/0, /*Type*/254, /*Imm*/GIMT_Encode8(42), -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode4(TargetOpcode::G_SUB), +// CHECK-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::G_SUB), // CHECK-NEXT: GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, // dst // CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, // CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, // CHECK-NEXT: GIR_EraseRootFromParent_Done, -// CHECK-NEXT: // Label 0: @78 +// CHECK-NEXT: // Label 0: @74 // CHECK-NEXT: GIM_Reject, -// CHECK-NEXT: }; // Size: 79 bytes +// CHECK-NEXT: }; // Size: 75 bytes // CHECK-NEXT: return MatchTable0; // CHECK-NEXT: } diff --git a/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-variadics.td b/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-variadics.td index d9fb4dd5105a..3d2a1ddb0a32 100644 --- a/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-variadics.td +++ b/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-variadics.td @@ -128,7 +128,7 @@ def MyCombiner: GICombiner<"GenMyCombiner", [ // CHECK-NEXT: // MIs[0] b // CHECK-NEXT: // No operand predicates // CHECK-NEXT: // Combiner Rule #5: VariadicTypeTestReuse -// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode4(TargetOpcode::G_MERGE_VALUES), +// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::G_MERGE_VALUES), // CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // a // CHECK-NEXT: GIR_CopyRemaining, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // b // CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/1, // c @@ -151,6 +151,6 @@ def MyCombiner: GICombiner<"GenMyCombiner", [ // CHECK-NEXT: GIM_Reject, // CHECK-NEXT: // Label 2: @{{[0-9]+}} // CHECK-NEXT: GIM_Reject, -// CHECK-NEXT: }; // Size: 130 bytes +// CHECK-NEXT: }; // Size: 128 bytes // CHECK-NEXT: return MatchTable0; // CHECK-NEXT: } diff --git a/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table.td b/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table.td index 6edca9e7928a..8907cfe811ab 100644 --- a/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table.td +++ b/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table.td @@ -185,7 +185,7 @@ def MyCombiner: GICombiner<"GenMyCombiner", [ // CHECK-NEXT: GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 43, // CHECK-NEXT: GIM_CheckIsSafeToFold, /*NumInsns*/1, // CHECK-NEXT: // Combiner Rule #5: InOutInstTest1 -// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode4(TargetOpcode::G_TRUNC), +// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::G_TRUNC), // CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // dst // CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // z // CHECK-NEXT: GIR_EraseRootFromParent_Done, @@ -203,7 +203,7 @@ def MyCombiner: GICombiner<"GenMyCombiner", [ // CHECK-NEXT: // No operand predicates // CHECK-NEXT: GIM_CheckIsSafeToFold, /*NumInsns*/1, // CHECK-NEXT: // Combiner Rule #4: InOutInstTest0 -// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode4(TargetOpcode::G_STORE), +// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::G_STORE), // CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ext // CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/1, // ptr // CHECK-NEXT: GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, @@ -240,7 +240,7 @@ def MyCombiner: GICombiner<"GenMyCombiner", [ // CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, // CHECK-NEXT: GIR_BuildConstant, /*TempRegID*/0, /*Val*/GIMT_Encode8(0), // CHECK-NEXT: // Combiner Rule #6: PatFragTest0 @ [__PatFragTest0_match_1[0]] -// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode4(TargetOpcode::COPY), +// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), // CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // dst // CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, // CHECK-NEXT: GIR_EraseRootFromParent_Done, diff --git a/llvm/test/TableGen/GlobalISelEmitter/ContextlessPredicates.td b/llvm/test/TableGen/GlobalISelEmitter/ContextlessPredicates.td index 60982364d691..93525f751fa7 100644 --- a/llvm/test/TableGen/GlobalISelEmitter/ContextlessPredicates.td +++ b/llvm/test/TableGen/GlobalISelEmitter/ContextlessPredicates.td @@ -22,7 +22,7 @@ def : Pat<(test_atomic_op_frag GPR32:$ptr, GPR32:$val) , // CHECK_NOPT-LABEL: const uint8_t *MyTargetInstructionSelector::getMatchTable() const { // CHECK_NOPT-NEXT: constexpr static uint8_t MatchTable0[] = { -// CHECK_NOPT-NEXT: GIM_Try, /*On fail goto*//*Label 0*/ GIMT_Encode4(54), // Rule ID 0 // +// CHECK_NOPT-NEXT: GIM_Try, /*On fail goto*//*Label 0*/ GIMT_Encode4(52), // Rule ID 0 // // CHECK_NOPT-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/3, // CHECK_NOPT-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_ATOMICRMW_XCHG), // CHECK_NOPT-NEXT: GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), @@ -37,11 +37,11 @@ def : Pat<(test_atomic_op_frag GPR32:$ptr, GPR32:$val) , // CHECK_NOPT-NEXT: GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // CHECK_NOPT-NEXT: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_test_atomic_op_frag), // CHECK_NOPT-NEXT: // (atomic_swap:{ *:[i32] } GPR32:{ *:[i32] }:$ptr, GPR32:{ *:[i32] }:$val)<> => (INSN:{ *:[i32] } GPR32:{ *:[i32] }:$ptr, GPR32:{ *:[i32] }:$val) -// CHECK_NOPT-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode4(MyTarget::INSN), +// CHECK_NOPT-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::INSN), // CHECK_NOPT-NEXT: GIR_RootConstrainSelectedInstOperands, // CHECK_NOPT-NEXT: // GIR_Coverage, 0, // CHECK_NOPT-NEXT: GIR_Done, -// CHECK_NOPT-NEXT: // Label 0: @54 +// CHECK_NOPT-NEXT: // Label 0: @52 // CHECK_NOPT-NEXT: GIM_Reject, // CHECK_NOPT-NEXT: }; // CHECK_NOPT-NEXT: return MatchTable0; @@ -49,7 +49,7 @@ def : Pat<(test_atomic_op_frag GPR32:$ptr, GPR32:$val) , // CHECK_OPT-LABEL: const uint8_t *MyTargetInstructionSelector::getMatchTable() const { // CHECK_OPT-NEXT: constexpr static uint8_t MatchTable0[] = { -// CHECK_OPT-NEXT: GIM_Try, /*On fail goto*//*Label 0*/ GIMT_Encode4(51), // Rule ID 0 // +// CHECK_OPT-NEXT: GIM_Try, /*On fail goto*//*Label 0*/ GIMT_Encode4(49), // Rule ID 0 // // CHECK_OPT-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_ATOMICRMW_XCHG), // CHECK_OPT-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, // CHECK_OPT-NEXT: GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, @@ -61,11 +61,11 @@ def : Pat<(test_atomic_op_frag GPR32:$ptr, GPR32:$val) , // CHECK_OPT-NEXT: GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // CHECK_OPT-NEXT: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_test_atomic_op_frag), // CHECK_OPT-NEXT: // (atomic_swap:{ *:[i32] } GPR32:{ *:[i32] }:$ptr, GPR32:{ *:[i32] }:$val)<> => (INSN:{ *:[i32] } GPR32:{ *:[i32] }:$ptr, GPR32:{ *:[i32] }:$val) -// CHECK_OPT-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode4(MyTarget::INSN), +// CHECK_OPT-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::INSN), // CHECK_OPT-NEXT: GIR_RootConstrainSelectedInstOperands, // CHECK_OPT-NEXT: // GIR_Coverage, 0, // CHECK_OPT-NEXT: GIR_Done, -// CHECK_OPT-NEXT: // Label 0: @51 +// CHECK_OPT-NEXT: // Label 0: @49 // CHECK_OPT-NEXT: GIM_Reject, // CHECK_OPT-NEXT: }; // CHECK_OPT-NEXT: return MatchTable0; diff --git a/llvm/test/TableGen/GlobalISelEmitter/CustomPredicate.td b/llvm/test/TableGen/GlobalISelEmitter/CustomPredicate.td index 04ab25704a8d..41e4c6303629 100644 --- a/llvm/test/TableGen/GlobalISelEmitter/CustomPredicate.td +++ b/llvm/test/TableGen/GlobalISelEmitter/CustomPredicate.td @@ -77,7 +77,7 @@ def and_or_pat : PatFrag< let PredicateCodeUsesOperands = 1; } -// CHECK: GIM_Try, /*On fail goto*//*Label 0*/ GIMT_Encode4(99), // Rule ID 7 // +// CHECK: GIM_Try, /*On fail goto*//*Label 0*/ GIMT_Encode4(97), // Rule ID 7 // // CHECK-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/3, // CHECK-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_AND), // CHECK-NEXT: // MIs[0] DstI[dst] @@ -105,9 +105,9 @@ def and_or_pat : PatFrag< // CHECK-NEXT: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_and_or_pat), // CHECK-NEXT: GIM_CheckIsSafeToFold, /*NumInsns*/1, // CHECK-NEXT: // (and:{ *:[i32] } DOP:{ *:[i32] }:$src2:$pred:3:z, (or:{ *:[i32] } DOP:{ *:[i32] }:$src0:$pred:3:x, DOP:{ *:[i32] }:$src1:$pred:3:y))<> => (AND_OR:{ *:[i32] } DOP:{ *:[i32] }:$src0, DOP:{ *:[i32] }:$src1, DOP:{ *:[i32] }:$src2) -// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode4(MyTarget::AND_OR), +// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::AND_OR), -// CHECK: GIM_Try, /*On fail goto*//*Label 1*/ GIMT_Encode4(198), // Rule ID 3 // +// CHECK: GIM_Try, /*On fail goto*//*Label 1*/ GIMT_Encode4(194), // Rule ID 3 // // CHECK-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/3, // CHECK-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_AND), // CHECK-NEXT: // MIs[0] DstI[dst] @@ -135,7 +135,7 @@ def and_or_pat : PatFrag< // CHECK-NEXT: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_and_or_pat), // CHECK-NEXT: GIM_CheckIsSafeToFold, /*NumInsns*/1, // CHECK-NEXT: // (and:{ *:[i32] } (or:{ *:[i32] } DOP:{ *:[i32] }:$src0:$pred:3:x, DOP:{ *:[i32] }:$src1:$pred:3:y), DOP:{ *:[i32] }:$src2:$pred:3:z)<> => (AND_OR:{ *:[i32] } DOP:{ *:[i32] }:$src0, DOP:{ *:[i32] }:$src1, DOP:{ *:[i32] }:$src2) -// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode4(MyTarget::AND_OR), +// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::AND_OR), // Test commutative, standalone pattern. def : Pat< @@ -152,7 +152,7 @@ def mul_pat : PatFrag< let PredicateCodeUsesOperands = 1; } -// CHECK: GIM_Try, /*On fail goto*//*Label 2*/ GIMT_Encode4(293), // Rule ID 4 // +// CHECK: GIM_Try, /*On fail goto*//*Label 2*/ GIMT_Encode4(287), // Rule ID 4 // // CHECK-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/3, // CHECK-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_MUL), // CHECK-NEXT: // MIs[0] DstI[dst] @@ -179,9 +179,9 @@ def mul_pat : PatFrag< // CHECK-NEXT: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_mul_pat), // CHECK-NEXT: GIM_CheckIsSafeToFold, /*NumInsns*/1, // CHECK-NEXT: // (mul:{ *:[i32] } (or:{ *:[i32] } DOP:{ *:[i32] }:$src0, DOP:{ *:[i32] }:$src1):$pred:4:x, DOP:{ *:[i32] }:$src2:$pred:4:y)<> => (MUL_OR:{ *:[i32] } DOP:{ *:[i32] }:$src0, DOP:{ *:[i32] }:$src1, DOP:{ *:[i32] }:$src2) -// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode4(MyTarget::MUL_OR), +// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::MUL_OR), -// CHECK: GIM_Try, /*On fail goto*//*Label 3*/ GIMT_Encode4(388), // Rule ID 8 // +// CHECK: GIM_Try, /*On fail goto*//*Label 3*/ GIMT_Encode4(380), // Rule ID 8 // // CHECK-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/3, // CHECK-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_MUL), // CHECK-NEXT: // MIs[0] DstI[dst] @@ -208,7 +208,7 @@ def mul_pat : PatFrag< // CHECK-NEXT: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_mul_pat), // CHECK-NEXT: GIM_CheckIsSafeToFold, /*NumInsns*/1, // CHECK-NEXT: // (mul:{ *:[i32] } DOP:{ *:[i32] }:$src2:$pred:4:y, (or:{ *:[i32] } DOP:{ *:[i32] }:$src0, DOP:{ *:[i32] }:$src1):$pred:4:x)<> => (MUL_OR:{ *:[i32] } DOP:{ *:[i32] }:$src0, DOP:{ *:[i32] }:$src1, DOP:{ *:[i32] }:$src2) -// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode4(MyTarget::MUL_OR), +// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::MUL_OR), // Test commutative patterns where named operands in the source pattern are not // directly bound to PatFrag's operands. @@ -227,7 +227,7 @@ def sub3_pat : PatFrag< let PredicateCodeUsesOperands = 1; } -// CHECK: GIM_Try, /*On fail goto*//*Label 4*/ GIMT_Encode4(473), // Rule ID 0 // +// CHECK: GIM_Try, /*On fail goto*//*Label 4*/ GIMT_Encode4(463), // Rule ID 0 // // CHECK-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/3, // CHECK-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_SUB), // CHECK-NEXT: // MIs[0] DstI[dst] @@ -252,7 +252,7 @@ def sub3_pat : PatFrag< // CHECK-NEXT: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_sub3_pat), // CHECK-NEXT: GIM_CheckIsSafeToFold, /*NumInsns*/1, // CHECK-NEXT: // (sub:{ *:[i32] } (sub:{ *:[i32] } i32:{ *:[i32] }:$src0:$pred:1:x, i32:{ *:[i32] }:$src1:$pred:1:y), i32:{ *:[i32] }:$src2:$pred:1:z)<> => (SUB3:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2) -// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode4(MyTarget::SUB3) +// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::SUB3) // Test a non-commutative pattern. def SUB3 : I<(outs DRegs:$dst), @@ -273,16 +273,16 @@ def patfrags_test_pat : PatFrags< let PredicateCodeUsesOperands = 1; } -// CHECK: GIM_Try, /*On fail goto*//*Label 5*/ GIMT_Encode4(558), // Rule ID 1 // +// CHECK: GIM_Try, /*On fail goto*//*Label 5*/ GIMT_Encode4(546), // Rule ID 1 // // CHECK: // (xor:{ *:[i32] } (add:{ *:[i32] } i32:{ *:[i32] }:$src0:$pred:2:x, i32:{ *:[i32] }:$src1:$pred:2:y), i32:{ *:[i32] }:$src2:$pred:2:z)<> => (PATFRAGS:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2) -// CHECK: GIM_Try, /*On fail goto*//*Label 6*/ GIMT_Encode4(643), // Rule ID 2 // +// CHECK: GIM_Try, /*On fail goto*//*Label 6*/ GIMT_Encode4(629), // Rule ID 2 // // CHECK: // (xor:{ *:[i32] } (sub:{ *:[i32] } i32:{ *:[i32] }:$src0:$pred:2:x, i32:{ *:[i32] }:$src1:$pred:2:y), i32:{ *:[i32] }:$src2:$pred:2:z)<> => (PATFRAGS:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2) -// CHECK: GIM_Try, /*On fail goto*//*Label 7*/ GIMT_Encode4(728), // Rule ID 5 // +// CHECK: GIM_Try, /*On fail goto*//*Label 7*/ GIMT_Encode4(712), // Rule ID 5 // // CHECK: // (xor:{ *:[i32] } i32:{ *:[i32] }:$src2:$pred:2:z, (add:{ *:[i32] } i32:{ *:[i32] }:$src0:$pred:2:x, i32:{ *:[i32] }:$src1:$pred:2:y))<> => (PATFRAGS:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2) -// CHECK: GIM_Try, /*On fail goto*//*Label 8*/ GIMT_Encode4(813), // Rule ID 6 // +// CHECK: GIM_Try, /*On fail goto*//*Label 8*/ GIMT_Encode4(795), // Rule ID 6 // // CHECK: // (xor:{ *:[i32] } i32:{ *:[i32] }:$src2:$pred:2:z, (sub:{ *:[i32] } i32:{ *:[i32] }:$src0:$pred:2:x, i32:{ *:[i32] }:$src1:$pred:2:y))<> => (PATFRAGS:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2) diff --git a/llvm/test/TableGen/GlobalISelEmitter/DefaultOpsGlobalISel.td b/llvm/test/TableGen/GlobalISelEmitter/DefaultOpsGlobalISel.td index 0ceee58e946b..3bb1379b0ec2 100644 --- a/llvm/test/TableGen/GlobalISelEmitter/DefaultOpsGlobalISel.td +++ b/llvm/test/TableGen/GlobalISelEmitter/DefaultOpsGlobalISel.td @@ -33,7 +33,7 @@ def clamp : OperandWithDefaultOps ; // CHECK: const uint8_t *MyTargetInstructionSelector::getMatchTable() const { // CHECK-NEXT: constexpr static uint8_t MatchTable0[] = { -// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 0*/ GIMT_Encode4(71), // Rule ID 3 // +// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 0*/ GIMT_Encode4(69), // Rule ID 3 // // CHECK-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/3, // CHECK-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_FMAXNUM), // CHECK-NEXT: // MIs[0] DstI[dst] @@ -46,7 +46,7 @@ def clamp : OperandWithDefaultOps ; // CHECK-NEXT: GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, // CHECK-NEXT: GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_SelectSrcMods), // CHECK-NEXT: // (fmaxnum:{ *:[f32] } (SelectSrcMods:{ *:[f32] } f32:{ *:[f32] }:$src0, src_mods:{ *:[i32] }:$mods0), (SelectSrcMods:{ *:[f32] } f32:{ *:[f32] }:$src1, src_mods:{ *:[i32] }:$mods1)) => (FMAX:{ *:[f32] } src_mods:{ *:[i32] }:$mods0, f32:{ *:[f32] }:$src0, src_mods:{ *:[i32] }:$mods1, f32:{ *:[f32] }:$src1) -// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode4(MyTarget::FMAX), +// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::FMAX), // CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] // CHECK-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // mods0 // CHECK-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 @@ -56,8 +56,8 @@ def clamp : OperandWithDefaultOps ; // CHECK-NEXT: GIR_RootConstrainSelectedInstOperands, // CHECK-NEXT: // GIR_Coverage, 3, // CHECK-NEXT: GIR_EraseRootFromParent_Done, -// CHECK-NEXT: // Label 0: @71 -// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 1*/ GIMT_Encode4(124), // Rule ID 2 // +// CHECK-NEXT: // Label 0: @69 +// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 1*/ GIMT_Encode4(120), // Rule ID 2 // // CHECK-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/2, // CHECK-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_FFLOOR), // CHECK-NEXT: // MIs[0] DstI[dst] @@ -67,7 +67,7 @@ def clamp : OperandWithDefaultOps ; // CHECK-NEXT: GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, // CHECK-NEXT: GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_SelectClampOMod), // CHECK-NEXT: // (ffloor:{ *:[f32] } (SelectClampOMod:{ *:[f32] } f32:{ *:[f32] }:$src0, omod:{ *:[i32] }:$omod, i1:{ *:[i1] }:$clamp)) => (FLOMP:{ *:[f32] } f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp, omod:{ *:[i32] }:$omod) -// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode4(MyTarget::FLOMP), +// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::FLOMP), // CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] // CHECK-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 // CHECK-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp @@ -75,8 +75,8 @@ def clamp : OperandWithDefaultOps ; // CHECK-NEXT: GIR_RootConstrainSelectedInstOperands, // CHECK-NEXT: // GIR_Coverage, 2, // CHECK-NEXT: GIR_EraseRootFromParent_Done, -// CHECK-NEXT: // Label 1: @124 -// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 2*/ GIMT_Encode4(185), // Rule ID 8 // +// CHECK-NEXT: // Label 1: @120 +// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 2*/ GIMT_Encode4(179), // Rule ID 8 // // CHECK-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/2, // CHECK-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_FCANONICALIZE), // CHECK-NEXT: // MIs[0] DstI[dst] @@ -86,7 +86,7 @@ def clamp : OperandWithDefaultOps ; // CHECK-NEXT: GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, // CHECK-NEXT: GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_SelectSrcMods), // CHECK-NEXT: // (fcanonicalize:{ *:[f32] } (SelectSrcMods:{ *:[f32] } f32:{ *:[f32] }:$src, i32:{ *:[i32] }:$mods)) => (FMAX:{ *:[f32] } ?:{ *:[i32] }:$mods, ?:{ *:[f32] }:$src, ?:{ *:[i32] }:$mods, ?:{ *:[f32] }:$src, 0:{ *:[i1] }) -// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode4(MyTarget::FMAX), +// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::FMAX), // CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] // CHECK-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // mods // CHECK-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src @@ -96,8 +96,8 @@ def clamp : OperandWithDefaultOps ; // CHECK-NEXT: GIR_RootConstrainSelectedInstOperands, // CHECK-NEXT: // GIR_Coverage, 8, // CHECK-NEXT: GIR_EraseRootFromParent_Done, -// CHECK-NEXT: // Label 2: @185 -// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 3*/ GIMT_Encode4(236), // Rule ID 5 // +// CHECK-NEXT: // Label 2: @179 +// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 3*/ GIMT_Encode4(228), // Rule ID 5 // // CHECK-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/2, // CHECK-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_FCOS), // CHECK-NEXT: // MIs[0] DstI[dst] @@ -107,7 +107,7 @@ def clamp : OperandWithDefaultOps ; // CHECK-NEXT: GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, // CHECK-NEXT: GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_SelectOMod), // CHECK-NEXT: // (fcos:{ *:[f32] } (SelectOMod:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$omod)) => (FLAMP:{ *:[f32] } FPR32:{ *:[f32] }:$src0, omod:{ *:[i32] }:$omod) -// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode4(MyTarget::FLAMP), +// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::FLAMP), // CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] // CHECK-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 // CHECK-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // omod @@ -115,8 +115,8 @@ def clamp : OperandWithDefaultOps ; // CHECK-NEXT: GIR_RootConstrainSelectedInstOperands, // CHECK-NEXT: // GIR_Coverage, 5, // CHECK-NEXT: GIR_EraseRootFromParent_Done, -// CHECK-NEXT: // Label 3: @236 -// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 4*/ GIMT_Encode4(311), // Rule ID 7 // +// CHECK-NEXT: // Label 3: @228 +// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 4*/ GIMT_Encode4(299), // Rule ID 7 // // CHECK-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/2, // CHECK-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_FEXP2), // CHECK-NEXT: // MIs[0] DstI[dst] @@ -127,12 +127,12 @@ def clamp : OperandWithDefaultOps ; // CHECK-NEXT: GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_SelectClamp), // CHECK-NEXT: // (fexp2:{ *:[f32] } (SelectClamp:{ *:[f32] } f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp)) => (FEEPLE:{ *:[f32] } FPR32:{ *:[f32] }:$src0, (FFOO:{ *:[f32] } FPR32:{ *:[f32] }:$src0), clamp:{ *:[i1] }:$clamp) // CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode4(MyTarget::FFOO), +// CHECK-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(MyTarget::FFOO), // CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast(RegState::Define)), // CHECK-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 // CHECK-NEXT: GIR_AddImm8, /*InsnID*/1, /*Imm*/0, // CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/1, -// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode4(MyTarget::FEEPLE), +// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::FEEPLE), // CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] // CHECK-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 // CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, @@ -140,8 +140,8 @@ def clamp : OperandWithDefaultOps ; // CHECK-NEXT: GIR_RootConstrainSelectedInstOperands, // CHECK-NEXT: // GIR_Coverage, 7, // CHECK-NEXT: GIR_EraseRootFromParent_Done, -// CHECK-NEXT: // Label 4: @311 -// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 5*/ GIMT_Encode4(359), // Rule ID 0 // +// CHECK-NEXT: // Label 4: @299 +// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 5*/ GIMT_Encode4(345), // Rule ID 0 // // CHECK-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/2, // CHECK-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_FSIN), // CHECK-NEXT: // MIs[0] DstI[dst] @@ -151,15 +151,15 @@ def clamp : OperandWithDefaultOps ; // CHECK-NEXT: GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, // CHECK-NEXT: GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_SelectClamp), // CHECK-NEXT: // (fsin:{ *:[f32] } (SelectClamp:{ *:[f32] } f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp)) => (FFOO:{ *:[f32] } f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp) -// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode4(MyTarget::FFOO), +// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::FFOO), // CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] // CHECK-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 // CHECK-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // clamp // CHECK-NEXT: GIR_RootConstrainSelectedInstOperands, // CHECK-NEXT: // GIR_Coverage, 0, // CHECK-NEXT: GIR_EraseRootFromParent_Done, -// CHECK-NEXT: // Label 5: @359 -// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 6*/ GIMT_Encode4(410), // Rule ID 6 // +// CHECK-NEXT: // Label 5: @345 +// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 6*/ GIMT_Encode4(394), // Rule ID 6 // // CHECK-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/2, // CHECK-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_FSQRT), // CHECK-NEXT: // MIs[0] DstI[dst] @@ -169,7 +169,7 @@ def clamp : OperandWithDefaultOps ; // CHECK-NEXT: GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, // CHECK-NEXT: GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_SelectClamp), // CHECK-NEXT: // (fsqrt:{ *:[f32] } (SelectClamp:{ *:[f32] } f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp)) => (FLAMP:{ *:[f32] } FPR32:{ *:[f32] }:$src0, 93:{ *:[i32] }, clamp:{ *:[i1] }:$clamp) -// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode4(MyTarget::FLAMP), +// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::FLAMP), // CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] // CHECK-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 // CHECK-NEXT: GIR_AddImm8, /*InsnID*/0, /*Imm*/93, @@ -177,8 +177,8 @@ def clamp : OperandWithDefaultOps ; // CHECK-NEXT: GIR_RootConstrainSelectedInstOperands, // CHECK-NEXT: // GIR_Coverage, 6, // CHECK-NEXT: GIR_EraseRootFromParent_Done, -// CHECK-NEXT: // Label 6: @410 -// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 7*/ GIMT_Encode4(446), // Rule ID 1 // +// CHECK-NEXT: // Label 6: @394 +// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 7*/ GIMT_Encode4(428), // Rule ID 1 // // CHECK-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/2, // CHECK-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_INTRINSIC_ROUND), // CHECK-NEXT: // MIs[0] DstI[dst] @@ -187,15 +187,15 @@ def clamp : OperandWithDefaultOps ; // CHECK-NEXT: // MIs[0] src0 // CHECK-NEXT: GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, // CHECK-NEXT: // (fround:{ *:[f32] } f32:{ *:[f32] }:$src0) => (FBAR:{ *:[f32] } f32:{ *:[f32] }:$src0) -// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode4(MyTarget::FBAR), +// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::FBAR), // CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] // CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/1, // src0 // CHECK-NEXT: GIR_AddImm8, /*InsnID*/0, /*Imm*/0, // CHECK-NEXT: GIR_RootConstrainSelectedInstOperands, // CHECK-NEXT: // GIR_Coverage, 1, // CHECK-NEXT: GIR_EraseRootFromParent_Done, -// CHECK-NEXT: // Label 7: @446 -// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 8*/ GIMT_Encode4(482), // Rule ID 4 // +// CHECK-NEXT: // Label 7: @428 +// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 8*/ GIMT_Encode4(462), // Rule ID 4 // // CHECK-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/2, // CHECK-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_INTRINSIC_TRUNC), // CHECK-NEXT: // MIs[0] DstI[dst] @@ -204,16 +204,16 @@ def clamp : OperandWithDefaultOps ; // CHECK-NEXT: // MIs[0] src0 // CHECK-NEXT: GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, // CHECK-NEXT: // (ftrunc:{ *:[f32] } f32:{ *:[f32] }:$src0) => (FFOO:{ *:[f32] } FPR32:{ *:[f32] }:$src0) -// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode4(MyTarget::FFOO), +// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::FFOO), // CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] // CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/1, // src0 // CHECK-NEXT: GIR_AddImm8, /*InsnID*/0, /*Imm*/0, // CHECK-NEXT: GIR_RootConstrainSelectedInstOperands, // CHECK-NEXT: // GIR_Coverage, 4, // CHECK-NEXT: GIR_EraseRootFromParent_Done, -// CHECK-NEXT: // Label 8: @482 +// CHECK-NEXT: // Label 8: @462 // CHECK-NEXT: GIM_Reject, -// CHECK-NEXT: }; // Size: 483 bytes +// CHECK-NEXT: }; // Size: 463 bytes // CHECK-NEXT: return MatchTable0; // CHECK-NEXT: } diff --git a/llvm/test/TableGen/GlobalISelEmitter/GlobalISelEmitter.td b/llvm/test/TableGen/GlobalISelEmitter/GlobalISelEmitter.td index f7d98bad138b..9b30760c31aa 100644 --- a/llvm/test/TableGen/GlobalISelEmitter/GlobalISelEmitter.td +++ b/llvm/test/TableGen/GlobalISelEmitter/GlobalISelEmitter.td @@ -306,14 +306,14 @@ def HasC : Predicate<"Subtarget->hasC()"> { let RecomputePerFunction = 1; } // R19O-NEXT: GIM_CheckComplexPattern, /*MI*/1, /*Op*/3, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_complex), // R19C-NEXT: // (select:{ *:[i32] } GPR32:{ *:[i32] }:$src1, (complex_rr:{ *:[i32] } GPR32:{ *:[i32] }:$src2a, GPR32:{ *:[i32] }:$src2b), (select:{ *:[i32] } GPR32:{ *:[i32] }:$src3, complex:{ *:[i32] }:$src4, (complex:{ *:[i32] } i32imm:{ *:[i32] }:$src5a, i32imm:{ *:[i32] }:$src5b))) => (INSN3:{ *:[i32] } GPR32:{ *:[i32] }:$src1, GPR32:{ *:[i32] }:$src2b, GPR32:{ *:[i32] }:$src2a, (INSN4:{ *:[i32] } GPR32:{ *:[i32] }:$src3, complex:{ *:[i32] }:$src4, i32imm:{ *:[i32] }:$src5a, i32imm:{ *:[i32] }:$src5b)) // R19C-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, -// R19C-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode4(MyTarget::INSN4), +// R19C-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(MyTarget::INSN4), // R19C-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast(RegState::Define)), // R19C-NEXT: GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // src3 // R19C-NEXT: GIR_ComplexRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(1), // R19C-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src5a // R19C-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src5b // R19C-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/1, -// R19C-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode4(MyTarget::INSN3), +// R19C-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::INSN3), // R19C-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] // R19C-NEXT: GIR_RootToRootCopy, /*OpIdx*/1, // src1 // R19C-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2b @@ -381,7 +381,7 @@ def : Pat<(select GPR32:$src1, (complex_rr GPR32:$src2a, GPR32:$src2b), // R21N-NEXT: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_frag), // R21C-NEXT: // (select:{ *:[i32] } GPR32:{ *:[i32] }:$src1, complex:{ *:[i32] }:$src2, complex:{ *:[i32] }:$src3)<> => (INSN2:{ *:[i32] } GPR32:{ *:[i32] }:$src1, complex:{ *:[i32] }:$src3, complex:{ *:[i32] }:$src2) -// R21C-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode4(MyTarget::INSN2), +// R21C-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::INSN2), // R21C-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] // R21C-NEXT: GIR_RootToRootCopy, /*OpIdx*/1, // src1 // R21C-NEXT: GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), @@ -431,7 +431,7 @@ def : Pat<(select GPR32:$src1, (complex_rr GPR32:$src2a, GPR32:$src2b), // R20O-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // R20C-NEXT: GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_complex), // R20C-NEXT: // (sub:{ *:[i32] } GPR32:{ *:[i32] }:$src1, complex:{ *:[i32] }:$src2) => (INSN1:{ *:[i32] } GPR32:{ *:[i32] }:$src1, complex:{ *:[i32] }:$src2) -// R20C-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode4(MyTarget::INSN1), +// R20C-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::INSN1), // R20C-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] // R20C-NEXT: GIR_RootToRootCopy, /*OpIdx*/1, // src1 // R20C-NEXT: GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), @@ -520,7 +520,7 @@ def : Pat<(frag GPR32:$src1, complex:$src2, complex:$src3), // R00O-NEXT: GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // R00C-NEXT: GIM_CheckIsSafeToFold, /*NumInsns*/2, // R00C-NEXT: // (sub:{ *:[i32] } (sub:{ *:[i32] } GPR32:{ *:[i32] }:$src1, GPR32:{ *:[i32] }:$src2), (sub:{ *:[i32] } GPR32:{ *:[i32] }:$src3, GPR32:{ *:[i32] }:$src4)) => (INSNBOB:{ *:[i32] } GPR32:{ *:[i32] }:$src1, GPR32:{ *:[i32] }:$src2, GPR32:{ *:[i32] }:$src3, GPR32:{ *:[i32] }:$src4) -// R00C-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode4(MyTarget::INSNBOB), +// R00C-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::INSNBOB), // R00C-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] // R00C-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 // R00C-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src2 @@ -536,7 +536,7 @@ def : Pat<(frag GPR32:$src1, complex:$src2, complex:$src3), // R00O-NEXT: GIM_Reject, // R00O: // Label [[DEFAULT_NUM]]: @[[DEFAULT]] // R00O-NEXT: GIM_Reject, -// R00O-NEXT: }; // Size: 1980 bytes +// R00O-NEXT: }; // Size: 1918 bytes def INSNBOB : I<(outs GPR32:$dst), (ins GPR32:$src1, GPR32:$src2, GPR32:$src3, GPR32:$src4), [(set GPR32:$dst, @@ -573,7 +573,7 @@ def INSNBOB : I<(outs GPR32:$dst), (ins GPR32:$src1, GPR32:$src2, GPR32:$src3, G // // R01C-NEXT: GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // R01C-NEXT: // (intrinsic_wo_chain:{ *:[i32] } [[ID:[0-9]+]]:{ *:[iPTR] }, GPR32:{ *:[i32] }:$src1) => (MOV:{ *:[i32] } GPR32:{ *:[i32] }:$src1) -// R01C-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode4(MyTarget::MOV), +// R01C-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::MOV), // R01C-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] // R01C-NEXT: GIR_RootToRootCopy, /*OpIdx*/2, // src1 // R01C-NEXT: GIR_RootConstrainSelectedInstOperands, @@ -620,7 +620,7 @@ def MOV : I<(outs GPR32:$dst), (ins GPR32:$src1), // // R02C-NEXT: GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 254, // R02C-NEXT: // (xor:{ *:[i32] } GPR32:{ *:[i32] }:$src1, -2:{ *:[i32] }) => (XORI:{ *:[i32] } GPR32:{ *:[i32] }:$src1) -// R02C-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode4(MyTarget::XORI), +// R02C-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::XORI), // R02C-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] // R02C-NEXT: GIR_AddImm8, /*InsnID*/0, /*Imm*/255, // R02C-NEXT: GIR_RootToRootCopy, /*OpIdx*/1, // src1 @@ -651,7 +651,7 @@ def XORI : I<(outs GPR32:$dst), (ins m1:$src2, GPR32:$src1), // NOOPT-NEXT: GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, // NOOPT-NEXT: GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 253, // NOOPT-NEXT: // (xor:{ *:[i32] } GPR32:{ *:[i32] }:$src1, -3:{ *:[i32] }) => (XOR:{ *:[i32] } GPR32:{ *:[i32] }:$src1) -// NOOPT-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode4(MyTarget::XOR), +// NOOPT-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::XOR), // NOOPT-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] // NOOPT-NEXT: GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(MyTarget::R0), // NOOPT-NEXT: GIR_RootToRootCopy, /*OpIdx*/1, // src1 @@ -679,7 +679,7 @@ def XOR : I<(outs GPR32:$dst), (ins Z:$src2, GPR32:$src1), // NOOPT-NEXT: GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, // NOOPT-NEXT: GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 252, // NOOPT-NEXT: // (xor:{ *:[i32] } GPR32:{ *:[i32] }:$src1, -4:{ *:[i32] }) => (XORlike:{ *:[i32] } GPR32:{ *:[i32] }:$src1) -// NOOPT-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode4(MyTarget::XORlike), +// NOOPT-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::XORlike), // NOOPT-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] // NOOPT-NEXT: GIR_AddImm8, /*InsnID*/0, /*Imm*/255, // NOOPT-NEXT: GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(MyTarget::R0), @@ -708,7 +708,7 @@ def XORlike : I<(outs GPR32:$dst), (ins m1Z:$src2, GPR32:$src1), // NOOPT-NEXT: GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, // NOOPT-NEXT: GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 251, // NOOPT-NEXT: // (xor:{ *:[i32] } GPR32:{ *:[i32] }:$src1, -5:{ *:[i32] }) => (XORManyDefaults:{ *:[i32] } GPR32:{ *:[i32] }:$src1) -// NOOPT-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode4(MyTarget::XORManyDefaults), +// NOOPT-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::XORManyDefaults), // NOOPT-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] // NOOPT-NEXT: GIR_AddImm8, /*InsnID*/0, /*Imm*/255, // NOOPT-NEXT: GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(MyTarget::R0), @@ -738,7 +738,7 @@ def XORManyDefaults : I<(outs GPR32:$dst), (ins m1Z:$src3, Z:$src2, GPR32:$src1) // NOOPT-NEXT: GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, // NOOPT-NEXT: GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 250, // NOOPT-NEXT: // (xor:{ *:[i32] } GPR32:{ *:[i32] }:$src1, -6:{ *:[i32] }) => (XORIb:{ *:[i32] } GPR32:{ *:[i32] }:$src1) -// NOOPT-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode4(MyTarget::XORIb), +// NOOPT-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::XORIb), // NOOPT-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] // NOOPT-NEXT: GIR_AddImm8, /*InsnID*/0, /*Imm*/13, // NOOPT-NEXT: GIR_RootToRootCopy, /*OpIdx*/1, // src1 @@ -769,7 +769,7 @@ def XORIb : I<(outs GPR32:$dst), (ins mb:$src2, GPR32:$src1), // NOOPT-NEXT: GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, // NOOPT-NEXT: GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 255, // NOOPT-NEXT: // (xor:{ *:[i32] } GPR32:{ *:[i32] }:$Wm, -1:{ *:[i32] }) => (ORN:{ *:[i32] } R0:{ *:[i32] }, GPR32:{ *:[i32] }:$Wm) -// NOOPT-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode4(MyTarget::ORN), +// NOOPT-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::ORN), // NOOPT-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] // NOOPT-NEXT: GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(MyTarget::R0), // NOOPT-NEXT: GIR_RootToRootCopy, /*OpIdx*/1, // Wm @@ -808,7 +808,7 @@ def : Pat<(not GPR32:$Wm), (ORN R0, GPR32:$Wm)>; // NOOPT-NEXT: GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // NOOPT-NEXT: GIM_CheckIsSafeToFold, /*NumInsns*/1, // NOOPT-NEXT: // (mul:{ *:[i32] } (add:{ *:[i32] } GPR32:{ *:[i32] }:$src1, GPR32:{ *:[i32] }:$src2), GPR32:{ *:[i32] }:$src3) => (MULADD:{ *:[i32] } GPR32:{ *:[i32] }:$src1, GPR32:{ *:[i32] }:$src2, GPR32:{ *:[i32] }:$src3) -// NOOPT-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode4(MyTarget::MULADD), +// NOOPT-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::MULADD), // NOOPT-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] // NOOPT-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 // NOOPT-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src2 @@ -845,7 +845,7 @@ def : Pat<(not GPR32:$Wm), (ORN R0, GPR32:$Wm)>; // NOOPT-NEXT: GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // NOOPT-NEXT: GIM_CheckIsSafeToFold, /*NumInsns*/1, // NOOPT-NEXT: // (mul:{ *:[i32] } GPR32:{ *:[i32] }:$src3, (add:{ *:[i32] } GPR32:{ *:[i32] }:$src1, GPR32:{ *:[i32] }:$src2)) => (MULADD:{ *:[i32] } GPR32:{ *:[i32] }:$src1, GPR32:{ *:[i32] }:$src2, GPR32:{ *:[i32] }:$src3) -// NOOPT-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode4(MyTarget::MULADD), +// NOOPT-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::MULADD), // NOOPT-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] // NOOPT-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 // NOOPT-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src2 @@ -862,24 +862,24 @@ def MULADD : I<(outs GPR32:$dst), (ins GPR32:$src1, GPR32:$src2, GPR32:$src3), //===- Test a simple pattern with a PatLeaf and a predicate. ---------===// // -// NOOPT-NEXT: /* 910 */ GIM_Try, /*On fail goto*//*Label 13*/ GIMT_Encode4(954), // Rule ID 24 // -// NOOPT-NEXT: /* 915 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/3, -// NOOPT-NEXT: /* 918 */ GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_SUB), -// NOOPT-NEXT: /* 922 */ // MIs[0] DstI[dst] -// NOOPT-NEXT: /* 922 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, -// NOOPT-NEXT: /* 925 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), -// NOOPT-NEXT: /* 929 */ // MIs[0] src1 -// NOOPT-NEXT: /* 929 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, -// NOOPT-NEXT: /* 932 */ GIM_CheckLeafOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_MO_Predicate_leaf), -// NOOPT-NEXT: /* 937 */ // MIs[0] src2 -// NOOPT-NEXT: /* 937 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, -// NOOPT-NEXT: /* 940 */ GIM_CheckLeafOperandPredicate, /*MI*/0, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_MO_Predicate_leaf), -// NOOPT-NEXT: /* 945 */ // (sub:{ *:[i32] } GPR32:{ *:[i32] }<>:$src1, GPR32:{ *:[i32] }<>:$src2) => (INSN5:{ *:[i32] } GPR32:{ *:[i32] }:$src1, GPR32:{ *:[i32] }:$src2) -// NOOPT-NEXT: /* 945 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode4(MyTarget::INSN5), -// NOOPT-NEXT: /* 952 */ GIR_RootConstrainSelectedInstOperands, -// NOOPT-NEXT: /* 953 */ // GIR_Coverage, 24, -// NOOPT-NEXT: /* 953 */ GIR_Done, -// NOOPT-NEXT: /* 954 */ // Label 13: @954 +// NOOPT-NEXT: /* 882 */ GIM_Try, /*On fail goto*//*Label 13*/ GIMT_Encode4(924), // Rule ID 24 // +// NOOPT-NEXT: /* 887 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/3, +// NOOPT-NEXT: /* 890 */ GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_SUB), +// NOOPT-NEXT: /* 894 */ // MIs[0] DstI[dst] +// NOOPT-NEXT: /* 894 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, +// NOOPT-NEXT: /* 897 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), +// NOOPT-NEXT: /* 901 */ // MIs[0] src1 +// NOOPT-NEXT: /* 901 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, +// NOOPT-NEXT: /* 904 */ GIM_CheckLeafOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_MO_Predicate_leaf), +// NOOPT-NEXT: /* 909 */ // MIs[0] src2 +// NOOPT-NEXT: /* 909 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, +// NOOPT-NEXT: /* 912 */ GIM_CheckLeafOperandPredicate, /*MI*/0, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_MO_Predicate_leaf), +// NOOPT-NEXT: /* 917 */ // (sub:{ *:[i32] } GPR32:{ *:[i32] }<>:$src1, GPR32:{ *:[i32] }<>:$src2) => (INSN5:{ *:[i32] } GPR32:{ *:[i32] }:$src1, GPR32:{ *:[i32] }:$src2) +// NOOPT-NEXT: /* 917 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::INSN5), +// NOOPT-NEXT: /* 922 */ GIR_RootConstrainSelectedInstOperands, +// NOOPT-NEXT: /* 923 */ // GIR_Coverage, 24, +// NOOPT-NEXT: /* 923 */ GIR_Done, +// NOOPT-NEXT: /* 924 */ // Label 13: @924 def leaf: PatLeaf<(i32 GPR32:$src), [{ return true; // C++ code }]> { let GISelLeafPredicateCode = [{ return true; }]; @@ -900,7 +900,7 @@ def : Pat<(sub leaf:$src1, leaf:$src2), (INSN5 GPR32:$src1, GPR32:$src2)>; // NOOPT-NEXT: // MIs[0] Operand 1 // NOOPT-NEXT: GIM_CheckLiteralInt, /*MI*/0, /*Op*/1, GIMT_Encode8(1), // NOOPT-NEXT: // 1:{ *:[i32] } => (MOV1:{ *:[i32] }) -// NOOPT-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode4(MyTarget::MOV1), +// NOOPT-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::MOV1), // NOOPT-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] // NOOPT-NEXT: GIR_RootConstrainSelectedInstOperands, // NOOPT-NEXT: // GIR_Coverage, 8, @@ -921,7 +921,7 @@ def MOV1 : I<(outs GPR32:$dst), (ins), [(set GPR32:$dst, 1)]>; // NOOPT-NEXT: // MIs[0] Operand 1 // NOOPT-NEXT: // No operand predicates // NOOPT-NEXT: // (imm:{ *:[i32] })<>:$imm => (MOVimm8:{ *:[i32] } (imm:{ *:[i32] }):$imm) -// NOOPT-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode4(MyTarget::MOVimm8), +// NOOPT-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::MOVimm8), // NOOPT-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] // NOOPT-NEXT: GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm // NOOPT-NEXT: GIR_RootConstrainSelectedInstOperands, @@ -944,7 +944,7 @@ def MOVimm8 : I<(outs GPR32:$dst), (ins i32imm:$imm), [(set GPR32:$dst, simm8:$i // NOOPT-NEXT: // MIs[0] Operand 1 // NOOPT-NEXT: // No operand predicates // NOOPT-NEXT: // (imm:{ *:[i32] })<>:$imm => (MOVimm9:{ *:[i32] } (imm:{ *:[i32] }):$imm) -// NOOPT-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode4(MyTarget::MOVimm9), +// NOOPT-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::MOVimm9), // NOOPT-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] // NOOPT-NEXT: GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm // NOOPT-NEXT: GIR_RootConstrainSelectedInstOperands, @@ -967,7 +967,7 @@ def MOVimm9 : I<(outs GPR32:$dst), (ins i32imm:$imm), [(set GPR32:$dst, simm9:$i // NOOPT-NEXT: // MIs[0] Operand 1 // NOOPT-NEXT: // No operand predicates // NOOPT-NEXT: // (imm:{ *:[i32] })<><>:$imm => (MOVcimm8:{ *:[i32] } (cimm8_xform:{ *:[i32] } (imm:{ *:[i32] }):$imm)) -// NOOPT-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode4(MyTarget::MOVcimm8), +// NOOPT-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::MOVcimm8), // NOOPT-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] // NOOPT-NEXT: GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/0, /*Renderer*/GIMT_Encode2(GICR_renderImm), // imm // NOOPT-NEXT: GIR_RootConstrainSelectedInstOperands, @@ -989,7 +989,7 @@ def MOVcimm8 : I<(outs GPR32:$dst), (ins i32imm:$imm), [(set GPR32:$dst, cimm8:$ // NOOPT-NEXT: // MIs[0] Operand 1 // NOOPT-NEXT: // No operand predicates // NOOPT-NEXT: // (fpimm:{ *:[f32] })<>:$imm => (MOVfpimmz:{ *:[f32] } (fpimm:{ *:[f32] }):$imm) -// NOOPT-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode4(MyTarget::MOVfpimmz), +// NOOPT-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::MOVfpimmz), // NOOPT-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] // NOOPT-NEXT: GIR_CopyFConstantAsFPImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm // NOOPT-NEXT: GIR_RootConstrainSelectedInstOperands, @@ -1011,7 +1011,7 @@ def MOVcimm8 : I<(outs GPR32:$dst), (ins i32imm:$imm), [(set GPR32:$dst, cimm8:$ // NOOPT-NEXT: GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, // NOOPT-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // NOOPT-NEXT: // (ld:{ *:[i32] } GPR32:{ *:[i32] }:$src1)<><> => (LOAD:{ *:[i32] } GPR32:{ *:[i32] }:$src1) -// NOOPT-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode4(MyTarget::LOAD), +// NOOPT-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::LOAD), // NOOPT-NEXT: GIR_RootConstrainSelectedInstOperands, // NOOPT-NEXT: // GIR_Coverage, 12, // NOOPT-NEXT: GIR_Done, @@ -1034,7 +1034,7 @@ def LOAD : I<(outs GPR32:$dst), (ins GPR32:$src1), // NOOPT-NEXT: GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, // NOOPT-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // NOOPT-NEXT: // (ld:{ *:[i32] } GPR32:{ *:[i32] }:$src)<><> => (LOAD:{ *:[i32] } GPR32:{ *:[i32] }:$src) -// NOOPT-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode4(MyTarget::LOAD), +// NOOPT-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::LOAD), // NOOPT-NEXT: GIR_RootConstrainSelectedInstOperands, // NOOPT-NEXT: // GIR_Coverage, 25, // NOOPT-NEXT: GIR_Done, @@ -1057,7 +1057,7 @@ def : Pat<(load GPR32:$src), // NOOPT-NEXT: GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, // NOOPT-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // NOOPT-NEXT: // (ld:{ *:[i32] } GPR32:{ *:[i32] }:$src1)<><><> => (SEXTLOAD:{ *:[i32] } GPR32:{ *:[i32] }:$src1) -// NOOPT-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode4(MyTarget::SEXTLOAD), +// NOOPT-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::SEXTLOAD), // NOOPT-NEXT: GIR_RootConstrainSelectedInstOperands, // NOOPT-NEXT: // GIR_Coverage, 13, // NOOPT-NEXT: GIR_Done, @@ -1081,7 +1081,7 @@ def SEXTLOAD : I<(outs GPR32:$dst), (ins GPR32:$src1), // NOOPT-NEXT: GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, // NOOPT-NEXT: GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // NOOPT-NEXT: // (add:{ *:[i32] } GPR32:{ *:[i32] }:$src1, GPR32:{ *:[i32] }:$src2) => (ADD:{ *:[i32] } GPR32:{ *:[i32] }:$src1, GPR32:{ *:[i32] }:$src2) -// NOOPT-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode4(MyTarget::ADD), +// NOOPT-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::ADD), // NOOPT-NEXT: GIR_RootConstrainSelectedInstOperands, // NOOPT-NEXT: // GIR_Coverage, 14, // NOOPT-NEXT: GIR_Done, @@ -1104,7 +1104,7 @@ def ADD : I<(outs GPR32:$dst), (ins GPR32:$src1, GPR32:$src2), // NOOPT-NEXT: // MIs[0] src{{$}} // NOOPT-NEXT: GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/0, /*OtherOpIdx*/1, // NOOPT-NEXT: // (add:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src) => (DOUBLE:{ *:[i32] } GPR32:{ *:[i32] }:$src) -// NOOPT-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode4(MyTarget::DOUBLE), +// NOOPT-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::DOUBLE), // NOOPT-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] // NOOPT-NEXT: GIR_RootToRootCopy, /*OpIdx*/1, // src // NOOPT-NEXT: GIR_RootConstrainSelectedInstOperands, @@ -1133,7 +1133,7 @@ def DOUBLE : I<(outs GPR32:$dst), (ins GPR32:$src), [(set GPR32:$dst, (add GPR32 // NOOPT-NEXT: // MIs[0] othername // NOOPT-NEXT: GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, // NOOPT-NEXT: // (add:{ *:[i32] } i32:{ *:[i32] }:$samename, i32:{ *:[i32] }:$othername) => (InsnWithSpeciallyNamedDef:{ *:[i32] } i32:{ *:[i32] }:$samename, i32:{ *:[i32] }:$othername) -// NOOPT-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode4(MyTarget::InsnWithSpeciallyNamedDef), +// NOOPT-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::InsnWithSpeciallyNamedDef), // NOOPT-NEXT: GIR_RootConstrainSelectedInstOperands, // NOOPT-NEXT: // GIR_Coverage, 26, // NOOPT-NEXT: GIR_Done, @@ -1156,7 +1156,7 @@ def : Pat<(add i32:$samename, i32:$othername), // NOOPT-NEXT: // MIs[0] src2 // NOOPT-NEXT: GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, // NOOPT-NEXT: // (add:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2) => (ADD:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2) -// NOOPT-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode4(MyTarget::ADD), +// NOOPT-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::ADD), // NOOPT-NEXT: GIR_RootConstrainSelectedInstOperands, // NOOPT-NEXT: // GIR_Coverage, 27, // NOOPT-NEXT: GIR_Done, @@ -1181,7 +1181,7 @@ def : Pat<(add i32:$src1, i32:$src2), // NOOPT-NEXT: GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, // NOOPT-NEXT: GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // NOOPT-NEXT: // (mul:{ *:[i32] } GPR32:{ *:[i32] }:$src1, GPR32:{ *:[i32] }:$src2) => (MUL:{ *:[i32] } GPR32:{ *:[i32] }:$src2, GPR32:{ *:[i32] }:$src1) -// NOOPT-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode4(MyTarget::MUL), +// NOOPT-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::MUL), // NOOPT-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] // NOOPT-NEXT: GIR_RootToRootCopy, /*OpIdx*/2, // src2 // NOOPT-NEXT: GIR_RootToRootCopy, /*OpIdx*/1, // src1 @@ -1207,7 +1207,7 @@ def MUL : I<(outs GPR32:$dst), (ins GPR32:$src2, GPR32:$src1), // NOOPT-NEXT: GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, // NOOPT-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::FPR32RegClassID), // NOOPT-NEXT: // (bitconvert:{ *:[i32] } FPR32:{ *:[f32] }:$src1) => (COPY_TO_REGCLASS:{ *:[i32] } FPR32:{ *:[f32] }:$src1, GPR32:{ *:[i32] }) -// NOOPT-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode4(TargetOpcode::COPY), +// NOOPT-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), // NOOPT-NEXT: GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(MyTarget::GPR32RegClassID), // NOOPT-NEXT: // GIR_Coverage, 28, // NOOPT-NEXT: GIR_Done, @@ -1227,7 +1227,7 @@ def : Pat<(i32 (bitconvert FPR32:$src1)), // NOOPT-NEXT: // MIs[0] Operand 1 // NOOPT-NEXT: // No operand predicates // NOOPT-NEXT: // (imm:{ *:[i32] }):$imm => (MOVimm:{ *:[i32] } (imm:{ *:[i32] }):$imm) -// NOOPT-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode4(MyTarget::MOVimm), +// NOOPT-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::MOVimm), // NOOPT-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] // NOOPT-NEXT: GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm // NOOPT-NEXT: GIR_RootConstrainSelectedInstOperands, @@ -1248,7 +1248,7 @@ def MOVfpimmz : I<(outs FPR32:$dst), (ins f32imm:$imm), [(set FPR32:$dst, fpimmz // NOOPT-NEXT: // MIs[0] target // NOOPT-NEXT: GIM_CheckIsMBB, /*MI*/0, /*Op*/0, // NOOPT-NEXT: // (br (bb:{ *:[Other] }):$target) => (BR (bb:{ *:[Other] }):$target) -// NOOPT-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode4(MyTarget::BR), +// NOOPT-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::BR), // NOOPT-NEXT: GIR_RootConstrainSelectedInstOperands, // NOOPT-NEXT: // GIR_Coverage, 19, // NOOPT-NEXT: GIR_Done, @@ -1258,5 +1258,5 @@ def BR : I<(outs), (ins unknown:$target), [(br bb:$target)]>; // NOOPT-NEXT: GIM_Reject, -// NOOPT-NEXT: }; // Size: 1563 bytes +// NOOPT-NEXT: }; // Size: 1501 bytes // NOOPT-NEXT: return MatchTable0; diff --git a/llvm/test/TableGen/GlobalISelEmitter/HwModes.td b/llvm/test/TableGen/GlobalISelEmitter/HwModes.td index 932e662e0461..56d62ca07088 100644 --- a/llvm/test/TableGen/GlobalISelEmitter/HwModes.td +++ b/llvm/test/TableGen/GlobalISelEmitter/HwModes.td @@ -141,7 +141,7 @@ class I Pat> // CHECK-NEXT: GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, // CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPRRegClassID), // CHECK-NEXT: // (ld:{ *:[i64] } GPR:{ *:[i64] }:$src1)<><> => (LOAD:{ *:[i64] } GPR:{ *:[i64] }:$src1) -// CHECK-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode4(MyTarget::LOAD), +// CHECK-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::LOAD), // CHECK-NEXT: GIR_RootConstrainSelectedInstOperands, // CHECK-NEXT: // GIR_Coverage, 0, // CHECK-NEXT: GIR_Done, @@ -159,7 +159,7 @@ class I Pat> // CHECK-NEXT: GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, // CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPRRegClassID), // CHECK-NEXT: // (ld:{ *:[i32] } GPR:{ *:[i32] }:$src1)<><> => (LOAD:{ *:[i32] } GPR:{ *:[i32] }:$src1) -// CHECK-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode4(MyTarget::LOAD), +// CHECK-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::LOAD), // CHECK-NEXT: GIR_RootConstrainSelectedInstOperands, // CHECK-NEXT: // GIR_Coverage, 1, // CHECK-NEXT: GIR_Done, @@ -183,7 +183,7 @@ def LOAD : I<(outs GPR:$dst), (ins GPR:$src1), // CHECK-NEXT: GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, // CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPRRegClassID), // CHECK-NEXT: // (ld:{ *:[i64] } GPR:{ *:[i64] }:$src)<><> => (LOAD:{ *:[i64] } GPR:{ *:[i64] }:$src) -// CHECK-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode4(MyTarget::LOAD), +// CHECK-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::LOAD), // CHECK-NEXT: GIR_RootConstrainSelectedInstOperands, // CHECK-NEXT: // GIR_Coverage, 2, // CHECK-NEXT: GIR_Done, @@ -201,7 +201,7 @@ def LOAD : I<(outs GPR:$dst), (ins GPR:$src1), // CHECK-NEXT: GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, // CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPRRegClassID), // CHECK-NEXT: // (ld:{ *:[i32] } GPR:{ *:[i32] }:$src)<><> => (LOAD:{ *:[i32] } GPR:{ *:[i32] }:$src) -// CHECK-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode4(MyTarget::LOAD), +// CHECK-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::LOAD), // CHECK-NEXT: GIR_RootConstrainSelectedInstOperands, // CHECK-NEXT: // GIR_Coverage, 3, // CHECK-NEXT: GIR_Done, diff --git a/llvm/test/TableGen/GlobalISelEmitter/MatchTableOptimizer.td b/llvm/test/TableGen/GlobalISelEmitter/MatchTableOptimizer.td index ad81058221ea..6ac6703991c2 100644 --- a/llvm/test/TableGen/GlobalISelEmitter/MatchTableOptimizer.td +++ b/llvm/test/TableGen/GlobalISelEmitter/MatchTableOptimizer.td @@ -17,7 +17,7 @@ def LOAD32 : I<(outs GPR8:$dst), (ins GPR32:$src), []>; // CHECK-NEXT: GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/8, // CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR8RegClassID), // CHECK-NEXT: // (ld:{ *:[i8] } GPR8:{ *:[i8] }:$src)<><> => (LOAD8:{ *:[i8] } GPR8:{ *:[i8] }:$src) -// CHECK-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode4(MyTarget::LOAD8), +// CHECK-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::LOAD8), // CHECK-NEXT: GIR_RootConstrainSelectedInstOperands, // CHECK-NEXT: // GIR_Coverage, 0, // CHECK-NEXT: GIR_Done, @@ -27,7 +27,7 @@ def LOAD32 : I<(outs GPR8:$dst), (ins GPR32:$src), []>; // CHECK-NEXT: GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, // CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // CHECK-NEXT: // (ld:{ *:[i8] } GPR32:{ *:[i32] }:$src)<><> => (LOAD32:{ *:[i8] } GPR32:{ *:[i32] }:$src) -// CHECK-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode4(MyTarget::LOAD32), +// CHECK-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::LOAD32), // CHECK-NEXT: GIR_RootConstrainSelectedInstOperands, // CHECK-NEXT: // GIR_Coverage, 1, // CHECK-NEXT: GIR_Done, @@ -60,7 +60,7 @@ def LOAD16Imm : I<(outs GPR16:$dst), (ins GPR16:$src), []>; // CHECK-NEXT: GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 10, // CHECK-NEXT: GIM_CheckIsSafeToFold, /*NumInsns*/1, // CHECK-NEXT: // (ld:{ *:[i16] } (add:{ *:[i16] } GPR16:{ *:[i16] }:$src, 10:{ *:[i16] }))<><> => (LOAD16Imm:{ *:[i16] } GPR16:{ *:[i16] }:$src) -// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode4(MyTarget::LOAD16Imm), +// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::LOAD16Imm), // CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] // CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src // CHECK-NEXT: GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, @@ -71,7 +71,7 @@ def LOAD16Imm : I<(outs GPR16:$dst), (ins GPR16:$src), []>; // CHECK-NEXT: GIM_Try, /*On fail goto*//*Label [[L3_ID:[0-9]+]]*/ GIMT_Encode4([[L3_AT:[0-9]+]]), // CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR16RegClassID), // CHECK-NEXT: // (ld:{ *:[i16] } GPR16:{ *:[i16] }:$src)<><> => (LOAD16:{ *:[i16] } GPR16:{ *:[i16] }:$src) -// CHECK-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode4(MyTarget::LOAD16), +// CHECK-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::LOAD16), // CHECK-NEXT: GIR_RootConstrainSelectedInstOperands, // CHECK-NEXT: // GIR_Coverage, 2, // CHECK-NEXT: GIR_Done, diff --git a/llvm/test/TableGen/GlobalISelEmitter/MatchTableOptimizerSameOperand-invalid.td b/llvm/test/TableGen/GlobalISelEmitter/MatchTableOptimizerSameOperand-invalid.td index fb152ce7dfea..18ae76720518 100644 --- a/llvm/test/TableGen/GlobalISelEmitter/MatchTableOptimizerSameOperand-invalid.td +++ b/llvm/test/TableGen/GlobalISelEmitter/MatchTableOptimizerSameOperand-invalid.td @@ -5,15 +5,15 @@ include "GlobalISelEmitterCommon.td" def InstTwoOperands : I<(outs GPR32:$dst), (ins GPR32:$src1, GPR32:$src2), []>; def InstThreeOperands : I<(outs GPR32:$dst), (ins GPR32:$cond, GPR32:$src,GPR32:$src2), []>; -// CHECK: GIM_Try, /*On fail goto*//*Label 0*/ GIMT_Encode4(235), +// CHECK: GIM_Try, /*On fail goto*//*Label 0*/ GIMT_Encode4(229), // CHECK-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_SELECT), // CHECK-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, // CHECK-NEXT: GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, // CHECK-NEXT: GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, -// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 1*/ GIMT_Encode4(201), +// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 1*/ GIMT_Encode4(197), // CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // CHECK-NEXT: GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/3, /*OtherMI*/2, /*OtherOpIdx*/2, -// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 2*/ GIMT_Encode4(116), // Rule ID 1 // +// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 2*/ GIMT_Encode4(114), // Rule ID 1 // // CHECK-NEXT: GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] // CHECK-NEXT: GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP), // CHECK-NEXT: GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, @@ -30,7 +30,7 @@ def InstThreeOperands : I<(outs GPR32:$dst), (ins GPR32:$cond, GPR32:$src,GPR32: // CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // CHECK-NEXT: GIM_CheckIsSafeToFold, /*NumInsns*/2, // CHECK-NEXT: // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$cond, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), (sub:{ *:[i32] } GPR32:{ *:[i32] }:$src1, GPR32:{ *:[i32] }:$src2), GPR32:{ *:[i32] }:$src2) => (InstThreeOperands:{ *:[i32] } GPR32:{ *:[i32] }:$cond, GPR32:{ *:[i32] }:$src1, GPR32:{ *:[i32] }:$src2) -// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode4(MyTarget::InstThreeOperands), +// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::InstThreeOperands), // CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] // CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // cond // CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1 @@ -38,8 +38,8 @@ def InstThreeOperands : I<(outs GPR32:$dst), (ins GPR32:$cond, GPR32:$src,GPR32: // CHECK-NEXT: GIR_RootConstrainSelectedInstOperands, // CHECK-NEXT: // GIR_Coverage, 1, // CHECK-NEXT: GIR_EraseRootFromParent_Done, -// CHECK-NEXT: // Label 2: @116 -// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 3*/ GIMT_Encode4(200), // Rule ID 2 // +// CHECK-NEXT: // Label 2: @114 +// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 3*/ GIMT_Encode4(196), // Rule ID 2 // // CHECK-NEXT: GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] // CHECK-NEXT: GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP), // CHECK-NEXT: GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, @@ -56,7 +56,7 @@ def InstThreeOperands : I<(outs GPR32:$dst), (ins GPR32:$cond, GPR32:$src,GPR32: // CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // CHECK-NEXT: GIM_CheckIsSafeToFold, /*NumInsns*/2, // CHECK-NEXT: // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$cond, 0:{ *:[i32] }, SETNE:{ *:[Other] }), (sub:{ *:[i32] } GPR32:{ *:[i32] }:$src1, GPR32:{ *:[i32] }:$src2), GPR32:{ *:[i32] }:$src2) => (InstThreeOperands:{ *:[i32] } GPR32:{ *:[i32] }:$cond, GPR32:{ *:[i32] }:$src1, GPR32:{ *:[i32] }:$src2) -// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode4(MyTarget::InstThreeOperands), +// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::InstThreeOperands), // CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] // CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // cond // CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1 @@ -64,23 +64,23 @@ def InstThreeOperands : I<(outs GPR32:$dst), (ins GPR32:$cond, GPR32:$src,GPR32: // CHECK-NEXT: GIR_RootConstrainSelectedInstOperands, // CHECK-NEXT: // GIR_Coverage, 2, // CHECK-NEXT: GIR_EraseRootFromParent_Done, -// CHECK-NEXT: // Label 3: @200 +// CHECK-NEXT: // Label 3: @196 // CHECK-NEXT: GIM_Reject, -// CHECK-NEXT: // Label 1: @201 -// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 4*/ GIMT_Encode4(234), // Rule ID 0 // +// CHECK-NEXT: // Label 1: @197 +// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 4*/ GIMT_Encode4(228), // Rule ID 0 // // CHECK-NEXT: GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, // CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // CHECK-NEXT: // (select:{ *:[i32] } GPR32:{ *:[i32] }:$cond, GPR32:{ *:[i32] }:$src1, GPR32:{ *:[i32] }:$src2) => (InstThreeOperands:{ *:[i32] } GPR32:{ *:[i32] }:$cond, GPR32:{ *:[i32] }:$src1, GPR32:{ *:[i32] }:$src2) -// CHECK-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode4(MyTarget::InstThreeOperands), +// CHECK-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::InstThreeOperands), // CHECK-NEXT: GIR_RootConstrainSelectedInstOperands, // CHECK-NEXT: // GIR_Coverage, 0, // CHECK-NEXT: GIR_Done, -// CHECK-NEXT: // Label 4: @234 +// CHECK-NEXT: // Label 4: @228 // CHECK-NEXT: GIM_Reject, -// CHECK-NEXT: // Label 0: @235 +// CHECK-NEXT: // Label 0: @229 // CHECK-NEXT: GIM_Reject, def : Pat<(i32 (select GPR32:$cond, GPR32:$src1, GPR32:$src2)), (InstThreeOperands GPR32:$cond, GPR32:$src1, GPR32:$src2)>; diff --git a/llvm/test/TableGen/GlobalISelEmitter/OverloadedPtr.td b/llvm/test/TableGen/GlobalISelEmitter/OverloadedPtr.td index b2f14f1c8761..43a121f94bd6 100644 --- a/llvm/test/TableGen/GlobalISelEmitter/OverloadedPtr.td +++ b/llvm/test/TableGen/GlobalISelEmitter/OverloadedPtr.td @@ -20,7 +20,7 @@ let TargetPrefix = "mytarget" in { // CHECK-NEXT: GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, // CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPRRegClassID), // CHECK-NEXT: // (ld:{ *:[i32] } GPR:{ *:[iPTR] }:$src1)<><> => (ANYLOAD:{ *:[i32] } GPR:{ *:[iPTR] }:$src1) -// CHECK-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode4(MyTarget::ANYLOAD), +// CHECK-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::ANYLOAD), // CHECK-NEXT: GIR_RootConstrainSelectedInstOperands, // CHECK-NEXT: // GIR_Coverage, 0, // CHECK-NEXT: GIR_Done, @@ -41,7 +41,7 @@ let hasSideEffects = 1 in { // CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // CHECK-NEXT: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_frag_anyptr), // CHECK-NEXT: // (intrinsic_w_chain:{ *:[i32] } {{[0-9]+}}:{ *:[iPTR] }, GPR32:{ *:[i32] }:$src)<> => (ANYLOAD:{ *:[i32] } GPR32:{ *:[i32] }:$src) -// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode4(MyTarget::ANYLOAD), +// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::ANYLOAD), def frag_anyptr : PatFrag<(ops node:$src), (int_mytarget_anyptr node:$src), diff --git a/llvm/test/TableGen/GlobalISelEmitter/RegSequence.td b/llvm/test/TableGen/GlobalISelEmitter/RegSequence.td index 73ca1adad4ca..0567c876cfe1 100644 --- a/llvm/test/TableGen/GlobalISelEmitter/RegSequence.td +++ b/llvm/test/TableGen/GlobalISelEmitter/RegSequence.td @@ -40,16 +40,16 @@ def SUBSOME_INSN : I<(outs SRegs:$dst), (ins SOP:$src), []>; // CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Test::SRegsRegClassID), // CHECK-NEXT: // (sext:{ *:[i32] } SOP:{ *:[i16] }:$src) => (REG_SEQUENCE:{ *:[i32] } DRegs:{ *:[i32] }, (SUBSOME_INSN:{ *:[i16] } SOP:{ *:[i16] }:$src), sub0:{ *:[i32] }, (SUBSOME_INSN:{ *:[i16] } SOP:{ *:[i16] }:$src), sub1:{ *:[i32] }) // CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16, -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode4(MyTarget::SUBSOME_INSN), +// CHECK-NEXT: GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(MyTarget::SUBSOME_INSN), // CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast(RegState::Define)), // CHECK-NEXT: GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src // CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/2, // CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode4(MyTarget::SUBSOME_INSN), +// CHECK-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(MyTarget::SUBSOME_INSN), // CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast(RegState::Define)), // CHECK-NEXT: GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src // CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/1, -// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode4(TargetOpcode::REG_SEQUENCE), +// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), // CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] // CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, // CHECK-NEXT: GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/1, @@ -66,7 +66,7 @@ def : Pat<(i32 (sext SOP:$src)), // CHECK: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_ZEXT), -// CHECK: GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode4(TargetOpcode::REG_SEQUENCE), +// CHECK: GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), // CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast(RegState::Define)), // CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, // CHECK-NEXT: GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/1, @@ -75,7 +75,7 @@ def : Pat<(i32 (sext SOP:$src)), // CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(Test::DRegsRegClassID), // CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(Test::SRegsRegClassID), // CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(Test::SRegsRegClassID), -// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode4(MyTarget::SOME_INSN), +// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::SOME_INSN), // Make sure operands are constrained when REG_SEQUENCE isn't the root instruction. def : Pat<(i32 (zext SOP:$src)), (SOME_INSN (REG_SEQUENCE DRegs, (SUBSOME_INSN SOP:$src), sub0, diff --git a/llvm/test/TableGen/GlobalISelEmitter/Subreg.td b/llvm/test/TableGen/GlobalISelEmitter/Subreg.td index c78ba5e3f748..777fabb8fdef 100644 --- a/llvm/test/TableGen/GlobalISelEmitter/Subreg.td +++ b/llvm/test/TableGen/GlobalISelEmitter/Subreg.td @@ -60,18 +60,18 @@ def : Pat<(sub (complex DOP:$src1, DOP:$src2), 77), (EXTRACT_SUBREG DOP:$src2, sub1))>; // CHECK-LABEL: // (sub:{ *:[i32] } (complex:{ *:[i32] } DOP:{ *:[i32] }:$src1, DOP:{ *:[i32] }:$src2), 77:{ *:[i32] }) => (SOME_INSN2:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i32] } DOP:{ *:[i32] }:$src1, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } DOP:{ *:[i32] }:$src2, sub1:{ *:[i32] })) // CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode4(TargetOpcode::COPY), +// CHECK-NEXT: GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), // CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast(RegState::Define)), // CHECK-NEXT: GIR_ComplexSubOperandSubRegRenderer, /*InsnID*/2, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, /*SubRegIdx*/GIMT_Encode2(2), // src2 // CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Test::SRegsRegClassID), // CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(Test::DRegsRegClassID), // CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode4(TargetOpcode::COPY), +// CHECK-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), // CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast(RegState::Define)), // CHECK-NEXT: GIR_ComplexSubOperandSubRegRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, /*SubRegIdx*/GIMT_Encode2(1), // src1 // CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(Test::SRegsRegClassID), // CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(Test::DRegsRegClassID), -// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode4(MyTarget::SOME_INSN2), +// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::SOME_INSN2), // CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] // CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, // CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, @@ -84,10 +84,10 @@ def : Pat<(sub (complex DOP:$src1, DOP:$src2), 77), def : Pat<(i32 (anyext i16:$src)), (INSERT_SUBREG (i32 (IMPLICIT_DEF)), SOP:$src, sub0)>; // CHECK-LABEL: (anyext:{ *:[i32] } i16:{ *:[i16] }:$src) => (INSERT_SUBREG:{ *:[i32] } (IMPLICIT_DEF:{ *:[i32] }), SOP:{ *:[i16] }:$src, sub0:{ *:[i32] }) // CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode4(TargetOpcode::IMPLICIT_DEF), +// CHECK-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), // CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast(RegState::Define)), // CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/1, -// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode4(TargetOpcode::INSERT_SUBREG), +// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), // CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] // CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, // CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/1, // src @@ -104,11 +104,11 @@ def : Pat<(i32 (anyext i16:$src)), (INSERT_SUBREG (i32 (IMPLICIT_DEF)), SOP:$src def : Pat<(i32 (anyext i16:$src)), (SOME_INSN (INSERT_SUBREG (i32 (IMPLICIT_DEF)), SOP:$src, sub0))>; // CHECK-LABEL: (anyext:{ *:[i32] } i16:{ *:[i16] }:$src) => (SOME_INSN:{ *:[i32] } (INSERT_SUBREG:{ *:[i32] } (IMPLICIT_DEF:{ *:[i32] }), SOP:{ *:[i16] }:$src, sub0:{ *:[i32] })) // CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode4(TargetOpcode::IMPLICIT_DEF), +// CHECK-NEXT: GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), // CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast(RegState::Define)), // CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/2, // CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode4(TargetOpcode::INSERT_SUBREG), +// CHECK-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), // CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast(RegState::Define)), // CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, // CHECK-NEXT: GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src @@ -116,7 +116,7 @@ def : Pat<(i32 (anyext i16:$src)), (SOME_INSN (INSERT_SUBREG (i32 (IMPLICIT_DEF) // CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(Test::DRegsRegClassID), // CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(Test::DRegsRegClassID), // CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(Test::SRegsRegClassID), -// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode4(MyTarget::SOME_INSN), +// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::SOME_INSN), // CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] // CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, // CHECK-NEXT: GIR_RootConstrainSelectedInstOperands, @@ -129,7 +129,7 @@ def : Pat<(i32 (anyext i16:$src)), (SOME_INSN (INSERT_SUBREG (i32 (IMPLICIT_DEF) // not a D register. def : Pat<(i32 (anyext i16:$src)), (INSERT_SUBREG (i32 (COPY_TO_REGCLASS SOP:$src, ERegs)), SOP:$src, sub0)>; // CHECK-LABEL: (anyext:{ *:[i32] } i16:{ *:[i16] }:$src) => (INSERT_SUBREG:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } SOP:{ *:[i16] }:$src, ERegs:{ *:[i32] }), SOP:{ *:[i16] }:$src, sub0:{ *:[i32] }) -// CHECK: GIR_BuildRootMI, /*Opcode*/GIMT_Encode4(TargetOpcode::INSERT_SUBREG), +// CHECK: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), // CHECK-DAG: GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Test::ERegsRegClassID), // CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(Test::ERegsRegClassID), // CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(Test::SRegsRegClassID), @@ -139,15 +139,15 @@ def : Pat<(i32 (anyext i16:$src)), (INSERT_SUBREG (i32 (COPY_TO_REGCLASS SOP:$sr def : Pat<(i32 (anyext i16:$src)), (INSERT_SUBREG (i32 (IMPLICIT_DEF)), (SUBSOME_INSN SOP:$src), sub0)>; // CHECK-LABEL: (anyext:{ *:[i32] } i16:{ *:[i16] }:$src) => (INSERT_SUBREG:{ *:[i32] } (IMPLICIT_DEF:{ *:[i32] }), (SUBSOME_INSN:{ *:[i16] } SOP:{ *:[i16] }:$src), sub0:{ *:[i32] }) // CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16, -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode4(MyTarget::SUBSOME_INSN), +// CHECK-NEXT: GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(MyTarget::SUBSOME_INSN), // CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast(RegState::Define)), // CHECK-NEXT: GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src // CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/2, // CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode4(TargetOpcode::IMPLICIT_DEF), +// CHECK-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), // CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast(RegState::Define)), // CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/1, -// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode4(TargetOpcode::INSERT_SUBREG), +// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), // CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] // CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, // CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, @@ -165,12 +165,12 @@ def : Pat<(i16 (trunc (not DOP:$src))), (SUBSOME_INSN (EXTRACT_SUBREG DOP:$src, sub0))>; // CHECK-LABEL: // (trunc:{ *:[i16] } (xor:{ *:[i32] } DOP:{ *:[i32] }:$src, -1:{ *:[i32] })) => (SUBSOME_INSN:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i16] } DOP:{ *:[i32] }:$src, sub0:{ *:[i32] })) // CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode4(TargetOpcode::COPY), +// CHECK-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), // CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast(RegState::Define)), // CHECK-NEXT: GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(1), // src // CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(Test::SRegsRegClassID), // CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(Test::DRegsRegClassID), -// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode4(MyTarget::SUBSOME_INSN), +// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::SUBSOME_INSN), // Test an extract from an output instruction result (nonleaf) def : Pat<(i16 (trunc (bitreverse DOP:$src))), @@ -181,11 +181,11 @@ def : Pat<(i16 (trunc (bitreverse DOP:$src))), // CHECK-NEXT: GIM_CheckIsSafeToFold, /*NumInsns*/1, // CHECK-NEXT: // (trunc:{ *:[i16] } (bitreverse:{ *:[i32] } DOP:{ *:[i32] }:$src)) => (EXTRACT_SUBREG:{ *:[i16] } (SOME_INSN:{ *:[i32] } DOP:{ *:[i32] }:$src), sub0:{ *:[i32] }) // CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode4(MyTarget::SOME_INSN), +// CHECK-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(MyTarget::SOME_INSN), // CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast(RegState::Define)), // CHECK-NEXT: GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // src // CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/1, -// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode4(TargetOpcode::COPY), +// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), // CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] // CHECK-NEXT: GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(sub0), // CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Test::SRegsRegClassID), @@ -201,17 +201,17 @@ def : Pat<(i16 (trunc (bitreverse DOP:$src))), // CHECK-NEXT: GIM_CheckIsSafeToFold, /*NumInsns*/1, // CHECK-NEXT: // (trunc:{ *:[i16] } (ctpop:{ *:[i32] } DOP:{ *:[i32] }:$src)) => (SUBSOME_INSN2:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i16] } (SOME_INSN:{ *:[i32] } DOP:{ *:[i32] }:$src), sub0:{ *:[i32] })) // CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode4(MyTarget::SOME_INSN), +// CHECK-NEXT: GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(MyTarget::SOME_INSN), // CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast(RegState::Define)), // CHECK-NEXT: GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src // CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/2, // CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode4(TargetOpcode::COPY), +// CHECK-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), // CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast(RegState::Define)), // CHECK-NEXT: GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(sub0), // CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(Test::SRegsRegClassID), // CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(Test::DRegsRegClassID), -// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode4(MyTarget::SUBSOME_INSN2), +// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::SUBSOME_INSN2), // CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] // CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, // CHECK-NEXT: GIR_RootConstrainSelectedInstOperands, @@ -224,7 +224,7 @@ def : Pat<(i16 (trunc (ctpop DOP:$src))), def : Pat<(i16 (trunc DOP:$src)), (EXTRACT_SUBREG DOP:$src, sub0)>; // CHECK-LABEL: // (trunc:{ *:[i16] } DOP:{ *:[i32] }:$src) => (EXTRACT_SUBREG:{ *:[i16] } DOP:{ *:[i32] }:$src, sub0:{ *:[i32] }) -// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode4(TargetOpcode::COPY), +// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), // CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] // CHECK-NEXT: GIR_CopySubReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(1), // src // CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Test::SRegsRegClassID), @@ -237,11 +237,11 @@ def : Pat<(i32 (zext SOP:$src)), (SUBREG_TO_REG (SUBSOME_INSN SOP:$src), sub0)>; // CHECK-LABEL: (zext:{ *:[i32] } SOP:{ *:[i16] }:$src) => (SUBREG_TO_REG:{ *:[i32] } (SUBSOME_INSN:{ *:[i16] } SOP:{ *:[i16] }:$src), sub0:{ *:[i32] }) // CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode4(MyTarget::SUBSOME_INSN), +// CHECK-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(MyTarget::SUBSOME_INSN), // CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast(RegState::Define)), // CHECK-NEXT: GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src // CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/1, -// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode4(TargetOpcode::SUBREG_TO_REG), +// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG), // CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] // CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, // CHECK-NEXT: GIR_AddImm8, /*InsnID*/0, /*Imm*/1, diff --git a/llvm/test/TableGen/GlobalISelEmitter/Variadic.td b/llvm/test/TableGen/GlobalISelEmitter/Variadic.td index 8c1dd55e2714..b3c80526af81 100644 --- a/llvm/test/TableGen/GlobalISelEmitter/Variadic.td +++ b/llvm/test/TableGen/GlobalISelEmitter/Variadic.td @@ -31,7 +31,7 @@ def : Pat<(build_vector GPR32:$src1, GPR32:$src2), // CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // CHECK-NEXT: // (build_vector:{ *:[i32] } GPR32:{ *:[i32] }:$src1) => (ONE:{ *:[i32] } GPR32:{ *:[i32] }:$src1) -// CHECK-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode4(MyTarget::ONE), +// CHECK-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::ONE), // CHECK-NEXT: GIR_RootConstrainSelectedInstOperands, // CHECK-NEXT: // GIR_Coverage, 0, // CHECK-NEXT: GIR_Done, @@ -45,7 +45,7 @@ def : Pat<(build_vector GPR32:$src1, GPR32:$src2), // CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // CHECK-NEXT: // (build_vector:{ *:[i32] } GPR32:{ *:[i32] }:$src1, GPR32:{ *:[i32] }:$src2) => (TWO:{ *:[i32] } GPR32:{ *:[i32] }:$src1, GPR32:{ *:[i32] }:$src2) -// CHECK-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode4(MyTarget::TWO), +// CHECK-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::TWO), // CHECK-NEXT: GIR_RootConstrainSelectedInstOperands, // CHECK-NEXT: // GIR_Coverage, 1, // CHECK-NEXT: GIR_Done, diff --git a/llvm/test/TableGen/GlobalISelEmitter/atomic-store.td b/llvm/test/TableGen/GlobalISelEmitter/atomic-store.td index 8b97a1399318..99869cc4e8ef 100644 --- a/llvm/test/TableGen/GlobalISelEmitter/atomic-store.td +++ b/llvm/test/TableGen/GlobalISelEmitter/atomic-store.td @@ -13,7 +13,7 @@ def ST_ATOM_B32 : I<(outs), (ins GPR32Op:$val, GPR32Op:$ptr), []>; // GISEL-NEXT: // MIs[0] ptr // GISEL-NEXT: GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, // GISEL-NEXT: // (atomic_store i32:{ *:[i32] }:$val, iPTR:{ *:[iPTR] }:$ptr)<> => (ST_ATOM_B32 GPR32Op:{ *:[i32] }:$val, GPR32Op:{ *:[i32] }:$ptr) -// GISEL-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode4(MyTarget::ST_ATOM_B32), +// GISEL-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::ST_ATOM_B32), def : Pat< // (atomic_store_8 iPTR:$ptr, i32:$val), (atomic_store_8 i32:$val, iPTR:$ptr), diff --git a/llvm/test/TableGen/GlobalISelEmitter/dead-def.td b/llvm/test/TableGen/GlobalISelEmitter/dead-def.td index b20f6d644846..f05d7ec1c5a3 100644 --- a/llvm/test/TableGen/GlobalISelEmitter/dead-def.td +++ b/llvm/test/TableGen/GlobalISelEmitter/dead-def.td @@ -14,12 +14,12 @@ def : Pat<(abs i32:$x), (I1 (I2 $x))>; // CHECK-LABEL: // (abs:{ *:[i32] } i32:{ *:[i32] }:$x) => (I1:{ *:[i32] } (I2:{ *:[i32] }:{ *:[i32] } ?:{ *:[i32] }:$x)) // CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, // CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode4(MyTarget::I2), +// CHECK-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(MyTarget::I2), // CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast(RegState::Define)), // CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast(RegState::Define|RegState::Dead)), // CHECK-NEXT: GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // x // CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/1, -// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode4(MyTarget::I1), +// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::I1), // CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[same_name] // CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, // CHECK-NEXT: GIR_RootConstrainSelectedInstOperands, diff --git a/llvm/test/TableGen/GlobalISelEmitter/frameindex.td b/llvm/test/TableGen/GlobalISelEmitter/frameindex.td index e3c7763af48a..27784526a65b 100644 --- a/llvm/test/TableGen/GlobalISelEmitter/frameindex.td +++ b/llvm/test/TableGen/GlobalISelEmitter/frameindex.td @@ -15,7 +15,7 @@ def : Pat<(frameindex:$fi), (ADDI (to_tframeindex $fi), 0)>; def : Pat<(ptradd frameindex:$fi, (i32 imm:$offset)), (ADDI (to_tframeindex $fi), imm:$offset)>; -// CHECK-LABEL: GIM_Try, /*On fail goto*//*Label 0*/ GIMT_Encode4(76), // Rule ID 1 // +// CHECK-LABEL: GIM_Try, /*On fail goto*//*Label 0*/ GIMT_Encode4(74), // Rule ID 1 // // CHECK-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/3, // CHECK-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_PTR_ADD), // CHECK-NEXT: // MIs[0] DstI[dst] @@ -41,7 +41,7 @@ def : Pat<(ptradd frameindex:$fi, (i32 imm:$offset)), // CHECK-NEXT: // No operand predicates // CHECK-NEXT: GIM_CheckIsSafeToFold, /*NumInsns*/2, // CHECK-NEXT: // (ptradd:{ *:[i32] } (frameindex:{ *:[i32] }):$fi, (imm:{ *:[i32] }):$offset) => (ADDI:{ *:[i32] } (to_tframeindex:{ *:[i32] } ?:{ *:[i32] }:$fi), (imm:{ *:[i32] }):$offset) -// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode4(MyTarget::ADDI), +// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::ADDI), // CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] // CHECK-NEXT: GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/1, /*Renderer*/GIMT_Encode2(GICR_renderFrameIndex), // fi // CHECK-NEXT: GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // offset @@ -49,7 +49,7 @@ def : Pat<(ptradd frameindex:$fi, (i32 imm:$offset)), // CHECK-NEXT: // GIR_Coverage, 1, // CHECK-NEXT: GIR_EraseRootFromParent_Done, -// CHECK-LABEL: GIM_Try, /*On fail goto*//*Label 1*/ GIMT_Encode4(113), // Rule ID 0 // +// CHECK-LABEL: GIM_Try, /*On fail goto*//*Label 1*/ GIMT_Encode4(109), // Rule ID 0 // // CHECK-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/2, // CHECK-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_FRAME_INDEX), // CHECK-NEXT: // MIs[0] DstI[dst] @@ -58,7 +58,7 @@ def : Pat<(ptradd frameindex:$fi, (i32 imm:$offset)), // CHECK-NEXT: // MIs[0] Operand 1 // CHECK-NEXT: // No operand predicates // CHECK-NEXT: // (frameindex:{ *:[i32] }):$fi => (ADDI:{ *:[i32] } (to_tframeindex:{ *:[i32] } ?:{ *:[i32] }:$fi), 0:{ *:[i32] }) -// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode4(MyTarget::ADDI), +// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::ADDI), // CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] // CHECK-NEXT: GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/0, /*Renderer*/GIMT_Encode2(GICR_renderFrameIndex), // fi // CHECK-NEXT: GIR_AddImm8, /*InsnID*/0, /*Imm*/0, diff --git a/llvm/test/TableGen/GlobalISelEmitter/gisel-physreg-input.td b/llvm/test/TableGen/GlobalISelEmitter/gisel-physreg-input.td index 366d7c25a01e..8fa004373ef6 100644 --- a/llvm/test/TableGen/GlobalISelEmitter/gisel-physreg-input.td +++ b/llvm/test/TableGen/GlobalISelEmitter/gisel-physreg-input.td @@ -46,10 +46,10 @@ class I Pat> // GISEL-NEXT: GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(MyTarget::Special32RegClassID), // GISEL-NEXT: GIM_CheckIsSafeToFold, /*NumInsns*/1, // GISEL-NEXT: // (st GPR32:{ *:[i32] }:$src0, (mul:{ *:[i32] } GPR32:{ *:[i32] }:$src1, SPECIAL:{ *:[i32] })) => (MULM_PHYS GPR32:{ *:[i32] }:$src0, GPR32:{ *:[i32] }:$src1) -// GISEL-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode4(TargetOpcode::COPY), +// GISEL-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), // GISEL-NEXT: GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(MyTarget::SPECIAL), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast(RegState::Define)), // GISEL-NEXT: GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // SPECIAL -// GISEL-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode4(MyTarget::MULM_PHYS), +// GISEL-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::MULM_PHYS), // GISEL-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // src0 // GISEL-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 // GISEL-NEXT: GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, @@ -85,13 +85,13 @@ def MULM_PHYS : I<(outs), (ins GPR32:$src0, GPR32:$src1), // GISEL-NEXT: GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(MyTarget::Special32RegClassID), // GISEL-NEXT: GIM_CheckIsSafeToFold, /*NumInsns*/1, // GISEL-NEXT: // (st GPR32:{ *:[i32] }:$src0, (mul:{ *:[i32] } R0:{ *:[i32] }, SPECIAL:{ *:[i32] })) => (MULMR0_PHYS GPR32:{ *:[i32] }:$src0) -// GISEL-NEXT: GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode4(TargetOpcode::COPY), +// GISEL-NEXT: GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), // GISEL-NEXT: GIR_AddRegister, /*InsnID*/2, GIMT_Encode2(MyTarget::SPECIAL), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast(RegState::Define)), // GISEL-NEXT: GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // SPECIAL -// GISEL-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode4(TargetOpcode::COPY), +// GISEL-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), // GISEL-NEXT: GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(MyTarget::R0), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast(RegState::Define)), // GISEL-NEXT: GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // R0 -// GISEL-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode4(MyTarget::MULMR0_PHYS), +// GISEL-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::MULMR0_PHYS), // GISEL-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // src0 // GISEL-NEXT: GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, // GISEL-NEXT: GIR_RootConstrainSelectedInstOperands, @@ -117,10 +117,10 @@ def MULMR0_PHYS : I<(outs), (ins GPR32:$src0), // GISEL-NEXT: GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, // GISEL-NEXT: GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(MyTarget::Special32RegClassID), // GISEL-NEXT: // (add:{ *:[i32] } GPR32:{ *:[i32] }:$src0, SPECIAL:{ *:[i32] }) => (ADD_PHYS:{ *:[i32] } GPR32:{ *:[i32] }:$src0) -// GISEL-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode4(TargetOpcode::COPY), +// GISEL-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), // GISEL-NEXT: GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(MyTarget::SPECIAL), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast(RegState::Define)), // GISEL-NEXT: GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // SPECIAL -// GISEL-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode4(MyTarget::ADD_PHYS), +// GISEL-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::ADD_PHYS), // GISEL-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] // GISEL-NEXT: GIR_RootToRootCopy, /*OpIdx*/1, // src0 // GISEL-NEXT: GIR_RootConstrainSelectedInstOperands, @@ -146,10 +146,10 @@ def ADD_PHYS : I<(outs GPR32:$dst), (ins GPR32:$src0), // GISEL-NEXT: GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, // GISEL-NEXT: GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(MyTarget::Special32RegClassID), // GISEL-NEXT: // (mul:{ *:[i32] } GPR32:{ *:[i32] }:$SPECIAL, SPECIAL:{ *:[i32] }) => (MUL_PHYS:{ *:[i32] } GPR32:{ *:[i32] }:$SPECIAL) -// GISEL-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode4(TargetOpcode::COPY), +// GISEL-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), // GISEL-NEXT: GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(MyTarget::SPECIAL), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast(RegState::Define)), // GISEL-NEXT: GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // SPECIAL -// GISEL-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode4(MyTarget::MUL_PHYS), +// GISEL-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::MUL_PHYS), // GISEL-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] // GISEL-NEXT: GIR_RootToRootCopy, /*OpIdx*/1, // SPECIAL // GISEL-NEXT: GIR_RootConstrainSelectedInstOperands, diff --git a/llvm/test/TableGen/GlobalISelEmitter/immarg-predicated.td b/llvm/test/TableGen/GlobalISelEmitter/immarg-predicated.td index ddc3c839f9af..ab412fac48e1 100644 --- a/llvm/test/TableGen/GlobalISelEmitter/immarg-predicated.td +++ b/llvm/test/TableGen/GlobalISelEmitter/immarg-predicated.td @@ -14,7 +14,7 @@ def int_mytarget_sleep0 : Intrinsic<[], [llvm_i32_ty], [ImmArg>]>; // GISEL-NEXT: GIM_CheckIsImm, /*MI*/0, /*Op*/1, // GISEL-NEXT: GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tuimm9), // GISEL-NEXT: // (intrinsic_void {{[0-9]+}}:{ *:[iPTR] }, (timm:{ *:[i32] })<>:$src) => (SLEEP0 (timm:{ *:[i32] }):$src) -// GISEL-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode4(MyTarget::SLEEP0), +// GISEL-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::SLEEP0), // GISEL-NEXT: GIR_RootToRootCopy, /*OpIdx*/1, // src def tuimm9 : TImmLeaf(Imm); }]>; def SLEEP0 : I<(outs), (ins i32imm:$src), diff --git a/llvm/test/TableGen/GlobalISelEmitter/immarg.td b/llvm/test/TableGen/GlobalISelEmitter/immarg.td index 7ab2ae540664..eae04094a689 100644 --- a/llvm/test/TableGen/GlobalISelEmitter/immarg.td +++ b/llvm/test/TableGen/GlobalISelEmitter/immarg.td @@ -14,7 +14,7 @@ def int_mytarget_sleep1 : Intrinsic<[], [llvm_i32_ty], [ImmArg>]>; // GISEL-NEXT: // MIs[0] src // GISEL-NEXT: GIM_CheckIsImm, /*MI*/0, /*Op*/1, // GISEL-NEXT: // (intrinsic_void {{[0-9]+}}:{ *:[iPTR] }, (timm:{ *:[i32] }):$src) => (SLEEP0 (timm:{ *:[i32] }):$src) -// GISEL-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode4(MyTarget::SLEEP0), +// GISEL-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::SLEEP0), // GISEL-NEXT: GIR_RootToRootCopy, /*OpIdx*/1, // src def SLEEP0 : I<(outs), (ins i32imm:$src), [(int_mytarget_sleep0 timm:$src)] diff --git a/llvm/test/TableGen/GlobalISelEmitter/input-discard.td b/llvm/test/TableGen/GlobalISelEmitter/input-discard.td index 77205ba272a8..b18d905b0bbf 100644 --- a/llvm/test/TableGen/GlobalISelEmitter/input-discard.td +++ b/llvm/test/TableGen/GlobalISelEmitter/input-discard.td @@ -17,10 +17,10 @@ def FOO : I<(outs GPR32:$dst), (ins GPR32Op:$src0, GPR32Op:$src1), []>; // GISEL-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // GISEL-NEXT: // (intrinsic_w_chain:{ *:[i32] } {{[0-9]+}}:{ *:[iPTR] }, srcvalue:{ *:[i32] }, i32:{ *:[i32] }:$src1) => (FOO:{ *:[i32] } (IMPLICIT_DEF:{ *:[i32] }), GPR32:{ *:[i32] }:$src1) // GISEL-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, -// GISEL-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode4(TargetOpcode::IMPLICIT_DEF), +// GISEL-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), // GISEL-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast(RegState::Define)), // GISEL-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/1, -// GISEL-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode4(MyTarget::FOO), +// GISEL-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::FOO), // GISEL-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] // GISEL-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, // GISEL-NEXT: GIR_RootToRootCopy, /*OpIdx*/3, // src1 diff --git a/llvm/test/TableGen/GlobalISelEmitter/int64min.td b/llvm/test/TableGen/GlobalISelEmitter/int64min.td index fdf40dbc1f33..ccdb749f2c14 100644 --- a/llvm/test/TableGen/GlobalISelEmitter/int64min.td +++ b/llvm/test/TableGen/GlobalISelEmitter/int64min.td @@ -6,7 +6,7 @@ include "GlobalISelEmitterCommon.td" def GPR : RegisterClass<"MyTarget", [i64], 64, (add R0)>; def ANDI : I<(outs GPR:$dst), (ins GPR:$src1, i64imm:$src2), []>; -// CHECK-LABEL: GIM_Try, /*On fail goto*//*Label 0*/ GIMT_Encode4(61), // Rule ID 0 // +// CHECK-LABEL: GIM_Try, /*On fail goto*//*Label 0*/ GIMT_Encode4(59), // Rule ID 0 // // CHECK-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/3, // CHECK-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_AND), // CHECK-NEXT: // MIs[0] DstI[dst] @@ -19,7 +19,7 @@ def ANDI : I<(outs GPR:$dst), (ins GPR:$src1, i64imm:$src2), []>; // CHECK-NEXT: GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, // CHECK-NEXT: GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(9223372036854775808u), // CHECK-NEXT: // (and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, -9223372036854775808:{ *:[i64] }) => (ANDI:{ *:[i64] } GPR:{ *:[i64] }:$rs1, -9223372036854775808:{ *:[i64] }) -// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode4(MyTarget::ANDI), +// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::ANDI), // CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] // CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/1, // rs1 // CHECK-NEXT: GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(9223372036854775808u), diff --git a/llvm/test/TableGen/GlobalISelEmitter/multiple-output-discard.td b/llvm/test/TableGen/GlobalISelEmitter/multiple-output-discard.td index 3b25b77d0914..54b0f4412da6 100644 --- a/llvm/test/TableGen/GlobalISelEmitter/multiple-output-discard.td +++ b/llvm/test/TableGen/GlobalISelEmitter/multiple-output-discard.td @@ -33,7 +33,7 @@ def : Pat<(two_out GPR32:$val), (THREE_OUTS GPR32:$val)>; // CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // CHECK-NEXT: // (two_out:{ *:[i32] }:{ *:[i32] } GPR32:{ *:[i32] }:$val) => (THREE_OUTS:{ *:[i32] }:{ *:[i32] }:{ *:[i32] } GPR32:{ *:[i32] }:$val) // CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, -// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode4(MyTarget::THREE_OUTS), +// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::THREE_OUTS), // CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[out1] // CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/1, // DstI[out2] // CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast(RegState::Define|RegState::Dead)), diff --git a/llvm/test/TableGen/GlobalISelEmitter/multiple-output.td b/llvm/test/TableGen/GlobalISelEmitter/multiple-output.td index 270658f01fb5..17cc0695a463 100644 --- a/llvm/test/TableGen/GlobalISelEmitter/multiple-output.td +++ b/llvm/test/TableGen/GlobalISelEmitter/multiple-output.td @@ -44,7 +44,7 @@ def : Pat<(loadpost (p0 GPR32:$addr), (i32 GPR32:$off)), // CHECK-NEXT: GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, // CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // CHECK-NEXT: // (loadpost:{ *:[i32] }:{ *:[i32] } GPR32:{ *:[i32] }:$addr, GPR32:{ *:[i32] }:$off) => (LDPost:{ *:[i32] }:{ *:[i32] } GPR32:{ *:[i32] }:$addr, GPR32:{ *:[i32] }:$off) -// CHECK-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode4(MyTarget::LDPost), +// CHECK-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::LDPost), // CHECK-NEXT: GIR_RootConstrainSelectedInstOperands, //----------------------------------------------------------------------------- @@ -79,7 +79,7 @@ def : Pat<(two_in GPR32:$i1, GPR32:$i2), (TWO_INS GPR32:$i2, GPR32:$i1)>; // CHECK-NEXT: GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, // CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // CHECK-NEXT: // (two_in:{ *:[i32] }:{ *:[i32] } GPR32:{ *:[i32] }:$i1, GPR32:{ *:[i32] }:$i2) => (TWO_INS:{ *:[i32] }:{ *:[i32] } GPR32:{ *:[i32] }:$i2, GPR32:{ *:[i32] }:$i1) -// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode4(MyTarget::TWO_INS), +// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::TWO_INS), // CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[out1] // CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/1, // DstI[out2] // CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/3, // i2 @@ -108,12 +108,12 @@ def : Pat<(i32 (add i32:$src, i32:$src)), // CHECK-NEXT: GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/0, /*OtherOpIdx*/1, // CHECK-NEXT: // (add:{ *:[i32] } i32:{ *:[i32] }:$src, i32:{ *:[i32] }:$src) => (OtherInstr:{ *:[i32] } (ImplicitDefInstr:{ *:[i32] }:{ *:[i32] } GPR32:{ *:[i32] }:$src)) // CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode4(MyTarget::ImplicitDefInstr), +// CHECK-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(MyTarget::ImplicitDefInstr), // CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast(RegState::Define)), // CHECK-NEXT: GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src // CHECK-NEXT: GIR_SetImplicitDefDead, /*InsnID*/1, /*OpIdx for MyTarget::R0*/0, // CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/1, -// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode4(MyTarget::OtherInstr), +// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::OtherInstr), // CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] // CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, // CHECK-NEXT: GIR_RootConstrainSelectedInstOperands, @@ -134,12 +134,12 @@ def : Pat<(i32 (add i32:$src, i32:$src)), // CHECK-NEXT: // (add:{ *:[i32] } i32:{ *:[i32] }:$src, i32:{ *:[i32] }:$src) => (OtherInstr:{ *:[i32] } (TwoOutsInstr:{ *:[i32] }:{ *:[i32] } GPR32:{ *:[i32] }:$src)) // CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, // CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode4(MyTarget::TwoOutsInstr), +// CHECK-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(MyTarget::TwoOutsInstr), // CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast(RegState::Define)), // CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast(RegState::Define|RegState::Dead)), // CHECK-NEXT: GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src // CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/1, -// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode4(MyTarget::OtherInstr), +// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::OtherInstr), // CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] // CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, // CHECK-NEXT: GIR_RootConstrainSelectedInstOperands, diff --git a/llvm/test/TableGen/GlobalISelEmitter/nested-subregs.td b/llvm/test/TableGen/GlobalISelEmitter/nested-subregs.td index f594cf67cc41..2513161eec24 100644 --- a/llvm/test/TableGen/GlobalISelEmitter/nested-subregs.td +++ b/llvm/test/TableGen/GlobalISelEmitter/nested-subregs.td @@ -39,11 +39,11 @@ def A0 : RegisterClass<"MyTarget", [i32], 32, (add a0)>; // CHECK-NEXT: GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s8, // CHECK-NEXT: // (anyext:{ *:[i16] } i8:{ *:[i8] }:$src) => (EXTRACT_SUBREG:{ *:[i16] } (INSERT_SUBREG:{ *:[i32] } (IMPLICIT_DEF:{ *:[i32] }), A0b:{ *:[i8] }:$src, lo8:{ *:[i32] }), lo16:{ *:[i32] }) // CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode4(TargetOpcode::IMPLICIT_DEF), +// CHECK-NEXT: GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), // CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast(RegState::Define)), // CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/2, // CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode4(TargetOpcode::INSERT_SUBREG), +// CHECK-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), // CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast(RegState::Define)), // CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, // CHECK-NEXT: GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src @@ -51,7 +51,7 @@ def A0 : RegisterClass<"MyTarget", [i32], 32, (add a0)>; // CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(MyTarget::A0RegClassID), // CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(MyTarget::A0RegClassID), // CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(MyTarget::A0bRegClassID), -// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode4(TargetOpcode::COPY), +// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), // CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] // CHECK-NEXT: GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(MyTarget::lo16), // CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(MyTarget::A0wRegClassID), diff --git a/llvm/test/TableGen/GlobalISelEmitter/optional-def.td b/llvm/test/TableGen/GlobalISelEmitter/optional-def.td index 6e2e4ff57667..3fc05dc368e1 100644 --- a/llvm/test/TableGen/GlobalISelEmitter/optional-def.td +++ b/llvm/test/TableGen/GlobalISelEmitter/optional-def.td @@ -9,7 +9,7 @@ def cc_out : OptionalDefOperand; def s_cc_out : OptionalDefOperand; // CHECK-LABEL: // (add:{ *:[i32] } i32:{ *:[i32] }:$rs1, i32:{ *:[i32] }:$rs2) => (tst2:{ *:[i32] } i32:{ *:[i32] }:$rs1, i32:{ *:[i32] }:$rs2) -// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode4(MyTarget::tst2), +// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::tst2), // CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] // CHECK-NEXT: GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(MyTarget::B0), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast(RegState::Define|RegState::Dead)), // CHECK-NEXT: GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(MyTarget::F0), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast(RegState::Define|RegState::Dead)), @@ -20,7 +20,7 @@ def s_cc_out : OptionalDefOperand; // CHECK-NEXT: GIR_EraseRootFromParent_Done, // CHECK-LABEL: // (imm:{ *:[i32] }):$imm => (tst1:{ *:[i32] } (imm:{ *:[i32] }):$imm) -// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode4(MyTarget::tst1), +// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::tst1), // CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] // CHECK-NEXT: GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(MyTarget::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast(RegState::Define|RegState::Dead)), // CHECK-NEXT: GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm diff --git a/llvm/test/TableGen/GlobalISelEmitter/output-discard.td b/llvm/test/TableGen/GlobalISelEmitter/output-discard.td index 11f8ba49b065..dfb6b1f10471 100644 --- a/llvm/test/TableGen/GlobalISelEmitter/output-discard.td +++ b/llvm/test/TableGen/GlobalISelEmitter/output-discard.td @@ -14,7 +14,7 @@ def ADD_CO : I<(outs GPR32:$dst, GPR8:$flag), // GISEL-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // GISEL-NEXT: // (add:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1) => (ADD_CO:{ *:[i32] }:{ *:[i8] } GPR32:{ *:[i32] }:$src0, GPR32:{ *:[i32] }:$src1) // GISEL-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s8, -// GISEL-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode4(MyTarget::ADD_CO), +// GISEL-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::ADD_CO), // GISEL-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] // GISEL-NEXT: GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast(RegState::Define|RegState::Dead)), // GISEL-NEXT: GIR_RootToRootCopy, /*OpIdx*/1, // src0 diff --git a/llvm/test/TableGen/GlobalISelEmitter/predicated-pattern-order.td b/llvm/test/TableGen/GlobalISelEmitter/predicated-pattern-order.td index 8bb997bb8f45..ce420dbe01a2 100644 --- a/llvm/test/TableGen/GlobalISelEmitter/predicated-pattern-order.td +++ b/llvm/test/TableGen/GlobalISelEmitter/predicated-pattern-order.td @@ -26,7 +26,7 @@ def aligned_store: PatFrag<(ops node:$v, node:$a), (store $v, $a), [{ // CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // CHECK-NEXT: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_store), // CHECK-NEXT: // (st GPR32:{ *:[i32] }:$src0, GPR32:{ *:[i32] }:$src1)<><><> => (MOVALIGNED GPR32:{ *:[i32] }:$src0, GPR32:{ *:[i32] }:$src1) -// CHECK-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode4(MyTarget::MOVALIGNED), +// CHECK-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::MOVALIGNED), // CHECK-NEXT: GIR_RootConstrainSelectedInstOperands, // CHECK-NEXT: // GIR_Coverage @@ -42,7 +42,7 @@ def aligned_store: PatFrag<(ops node:$v, node:$a), (store $v, $a), [{ // CHECK-NEXT: GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, // CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // CHECK-NEXT: // (st GPR32:{ *:[i32] }:$src0, GPR32:{ *:[i32] }:$src1)<><> => (MOVUNALIGNED GPR32:{ *:[i32] }:$src0, GPR32:{ *:[i32] }:$src1) -// CHECK-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode4(MyTarget::MOVUNALIGNED), +// CHECK-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::MOVUNALIGNED), // CHECK-NEXT: GIR_RootConstrainSelectedInstOperands, // CHECK-NEXT: // GIR_Coverage @@ -59,7 +59,7 @@ def aligned_store: PatFrag<(ops node:$v, node:$a), (store $v, $a), [{ // OPT-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // OPT-NEXT: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_store), // OPT-NEXT: // (st GPR32:{ *:[i32] }:$src0, GPR32:{ *:[i32] }:$src1)<><><> => (MOVALIGNED GPR32:{ *:[i32] }:$src0, GPR32:{ *:[i32] }:$src1) -// OPT-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode4(MyTarget::MOVALIGNED), +// OPT-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::MOVALIGNED), // OPT-NEXT: GIR_RootConstrainSelectedInstOperands, // OPT-NEXT: // GIR_Coverage @@ -69,7 +69,7 @@ def aligned_store: PatFrag<(ops node:$v, node:$a), (store $v, $a), [{ // OPT-NEXT: GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, // OPT-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // OPT-NEXT: // (st GPR32:{ *:[i32] }:$src0, GPR32:{ *:[i32] }:$src1)<><> => (MOVUNALIGNED GPR32:{ *:[i32] }:$src0, GPR32:{ *:[i32] }:$src1) -// OPT-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode4(MyTarget::MOVUNALIGNED), +// OPT-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::MOVUNALIGNED), // OPT-NEXT: GIR_RootConstrainSelectedInstOperands, // OPT-NEXT: // GIR_Coverage diff --git a/llvm/test/TableGen/GlobalISelEmitter/undef-tied-input.td b/llvm/test/TableGen/GlobalISelEmitter/undef-tied-input.td index 0d03358b6652..c0a9d2391b5a 100644 --- a/llvm/test/TableGen/GlobalISelEmitter/undef-tied-input.td +++ b/llvm/test/TableGen/GlobalISelEmitter/undef-tied-input.td @@ -24,9 +24,9 @@ def I2 : I<(outs GPR32:$rd), (ins GPR32:$rs, undef_tied_2:$opt), // CHECK-LABEL: // (abs:{ *:[i32] } i32:{ *:[i32] }:$rs) => (I1:{ *:[i32] } i32:{ *:[i32] }:$rs) // CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode4(TargetOpcode::IMPLICIT_DEF), +// CHECK-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), // CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast(RegState::Define)), -// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode4(MyTarget::I1), +// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::I1), // CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] // CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/1, // rs // CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, diff --git a/llvm/test/TableGen/GlobalISelEmitter/zero-reg.td b/llvm/test/TableGen/GlobalISelEmitter/zero-reg.td index f18d19bd904f..dfbe7f902c01 100644 --- a/llvm/test/TableGen/GlobalISelEmitter/zero-reg.td +++ b/llvm/test/TableGen/GlobalISelEmitter/zero-reg.td @@ -31,7 +31,7 @@ def INST : PredI<(outs GPR32:$dst), (ins GPR32:$src), []>; // CHECK-NEXT: GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, // CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // CHECK-NEXT: // (ld:{ *:[i32] } GPR32:{ *:[i32] }:$src)<><> => (INST:{ *:[i32] } GPR32:{ *:[i32] }:$src) -// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode4(MyTarget::INST), +// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::INST), // CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] // CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/1, // src // CHECK-NEXT: GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(MyTarget::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), diff --git a/llvm/test/TableGen/HasNoUse.td b/llvm/test/TableGen/HasNoUse.td index e10df7513d3d..d51fa9ef0723 100644 --- a/llvm/test/TableGen/HasNoUse.td +++ b/llvm/test/TableGen/HasNoUse.td @@ -24,7 +24,7 @@ def NO_RET_ATOMIC_ADD : I<(outs), (ins GPR32Op:$src0, GPR32Op:$src1), []>; // GISEL-NEXT: // MIs[0] src0 // GISEL-NEXT: GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, // GISEL-NEXT: // (atomic_load_add:{ *:[i32] } iPTR:{ *:[iPTR] }:$src0, i32:{ *:[i32] }:$src1)<> => (NO_RET_ATOMIC_ADD GPR32:{ *:[i32] }:$src0, GPR32:{ *:[i32] }:$src1) -// GISEL-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode4(MyTarget::NO_RET_ATOMIC_ADD), +// GISEL-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::NO_RET_ATOMIC_ADD), // GISEL-NEXT: GIR_RootToRootCopy, /*OpIdx*/1, // src0 // GISEL-NEXT: GIR_RootToRootCopy, /*OpIdx*/2, // src1 // GISEL-NEXT: GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, diff --git a/llvm/test/TableGen/RegClassByHwMode.td b/llvm/test/TableGen/RegClassByHwMode.td index 40e7b6ad2f82..83531b9248f9 100644 --- a/llvm/test/TableGen/RegClassByHwMode.td +++ b/llvm/test/TableGen/RegClassByHwMode.td @@ -211,7 +211,7 @@ include "Common/RegClassByHwModeCommon.td" // ISEL-SDAG-NEXT: OPC_CheckPredicate0, // Predicate_unindexedstore // ISEL-SDAG-NEXT: OPC_CheckPredicate1, // Predicate_store // ISEL-SDAG-NEXT: OPC_EmitMergeInputChains1_0, -// ISEL-SDAG-NEXT: OPC_MorphNodeTo0, TARGET_OUTPUT_VAL(MyTarget::MY_STORE), 0|OPFL_Chain|OPFL_MemRefs, +// ISEL-SDAG-NEXT: OPC_MorphNodeTo0, TARGET_VAL(MyTarget::MY_STORE), 0|OPFL_Chain|OPFL_MemRefs, // ISEL-SDAG-NEXT: 2/*#Ops*/, /*OperandList*/1, // Ops = #1 #2 // ISEL-SDAG: /*SwitchOpcode*/ {{[0-9]+}}, TARGET_VAL(ISD::LOAD), @@ -223,7 +223,7 @@ include "Common/RegClassByHwModeCommon.td" // ISEL-SDAG-NEXT: OPC_CheckPredicate3, // Predicate_load // ISEL-SDAG-NEXT: OPC_CheckTypeI64, // ISEL-SDAG-NEXT: OPC_EmitMergeInputChains1_0, -// ISEL-SDAG-NEXT: OPC_MorphNodeToByHwMode, TARGET_OUTPUT_VAL(MyTarget::MY_LOAD), 0|OPFL_Chain|OPFL_MemRefs, +// ISEL-SDAG-NEXT: OPC_MorphNodeToByHwMode, TARGET_VAL(MyTarget::MY_LOAD), 0|OPFL_Chain|OPFL_MemRefs, // ISEL-SDAG-NEXT: 1/*#VTs*/, /*{(*:i64),(m1:i64),(m2:i64)}*/0, 1/*#Ops*/, /*OperandList*/0, // Ops = #1 // ISEL-SDAG: static const uint8_t OperandLists[] = { @@ -235,115 +235,115 @@ include "Common/RegClassByHwModeCommon.td" -// ISEL-GISEL: GIM_Try, /*On fail goto*//*Label 3*/ GIMT_Encode4(156), +// ISEL-GISEL: GIM_Try, /*On fail goto*//*Label 3*/ GIMT_Encode4(148), // ISEL-GISEL-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, // ISEL-GISEL-NEXT: GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, // ISEL-GISEL-NEXT: GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, // ISEL-GISEL-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::XRegsRegClassID), -// ISEL-GISEL-NEXT: GIM_Try, /*On fail goto*//*Label 4*/ GIMT_Encode4(105), +// ISEL-GISEL-NEXT: GIM_Try, /*On fail goto*//*Label 4*/ GIMT_Encode4(101), // ISEL-GISEL-NEXT: GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, // FIXME: This should be a direct check for regbank, not have an incorrect class // ISEL-GISEL-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::PtrRegs32RegClassID), -// ISEL-GISEL-NEXT: GIM_Try, /*On fail goto*//*Label 5*/ GIMT_Encode4(87), // Rule ID 4 // +// ISEL-GISEL-NEXT: GIM_Try, /*On fail goto*//*Label 5*/ GIMT_Encode4(85), // Rule ID 4 // // ISEL-GISEL-NEXT: GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0), // ISEL-GISEL-NEXT: // (ld:{ *:[i64] } PtrRegOperand:{ *:[i32] }:$src)<><> => (MY_LOAD:{ *:[i64] } ?:{ *:[i32] }:$src) -// ISEL-GISEL-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode4(MyTarget::MY_LOAD), +// ISEL-GISEL-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::MY_LOAD), // ISEL-GISEL-NEXT: GIR_RootConstrainSelectedInstOperands, // ISEL-GISEL-NEXT: // GIR_Coverage, 4, // ISEL-GISEL-NEXT: GIR_Done, -// ISEL-GISEL-NEXT: // Label 5: @87 -// ISEL-GISEL-NEXT: GIM_Try, /*On fail goto*//*Label 6*/ GIMT_Encode4(104), // Rule ID 5 // +// ISEL-GISEL-NEXT: // Label 5: @85 +// ISEL-GISEL-NEXT: GIM_Try, /*On fail goto*//*Label 6*/ GIMT_Encode4(100), // Rule ID 5 // // ISEL-GISEL-NEXT: GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1), // ISEL-GISEL-NEXT: // (ld:{ *:[i64] } PtrRegOperand:{ *:[i32] }:$src)<><> => (MY_LOAD:{ *:[i64] } ?:{ *:[i32] }:$src) -// ISEL-GISEL-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode4(MyTarget::MY_LOAD), +// ISEL-GISEL-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::MY_LOAD), // ISEL-GISEL-NEXT: GIR_RootConstrainSelectedInstOperands, // ISEL-GISEL-NEXT: // GIR_Coverage, 5, // ISEL-GISEL-NEXT: GIR_Done, -// ISEL-GISEL-NEXT: // Label 6: @104 +// ISEL-GISEL-NEXT: // Label 6: @100 // ISEL-GISEL-NEXT: GIM_Reject, -// ISEL-GISEL-NEXT: // Label 4: @105 -// ISEL-GISEL-NEXT: GIM_Try, /*On fail goto*//*Label 7*/ GIMT_Encode4(130), // Rule ID 6 // +// ISEL-GISEL-NEXT: // Label 4: @101 +// ISEL-GISEL-NEXT: GIM_Try, /*On fail goto*//*Label 7*/ GIMT_Encode4(124), // Rule ID 6 // // ISEL-GISEL-NEXT: GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2), // ISEL-GISEL-NEXT: // MIs[0] src // ISEL-GISEL-NEXT: GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, // ISEL-GISEL-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::PtrRegs32RegClassID), // ISEL-GISEL-NEXT: // (ld:{ *:[i64] } PtrRegOperand:{ *:[i64] }:$src)<><> => (MY_LOAD:{ *:[i64] } ?:{ *:[i64] }:$src) -// ISEL-GISEL-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode4(MyTarget::MY_LOAD), +// ISEL-GISEL-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::MY_LOAD), // ISEL-GISEL-NEXT: GIR_RootConstrainSelectedInstOperands, // ISEL-GISEL-NEXT: // GIR_Coverage, 6, // ISEL-GISEL-NEXT: GIR_Done, -// ISEL-GISEL-NEXT: // Label 7: @130 -// ISEL-GISEL-NEXT: GIM_Try, /*On fail goto*//*Label 8*/ GIMT_Encode4(155), // Rule ID 7 // +// ISEL-GISEL-NEXT: // Label 7: @124 +// ISEL-GISEL-NEXT: GIM_Try, /*On fail goto*//*Label 8*/ GIMT_Encode4(147), // Rule ID 7 // // ISEL-GISEL-NEXT: GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3), // ISEL-GISEL-NEXT: // MIs[0] src // ISEL-GISEL-NEXT: GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, // ISEL-GISEL-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::PtrRegs32RegClassID), // ISEL-GISEL-NEXT: // (ld:{ *:[i64] } PtrRegOperand:{ *:[i32] }:$src)<><> => (MY_LOAD:{ *:[i64] } ?:{ *:[i32] }:$src) -// ISEL-GISEL-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode4(MyTarget::MY_LOAD), +// ISEL-GISEL-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::MY_LOAD), // ISEL-GISEL-NEXT: GIR_RootConstrainSelectedInstOperands, // ISEL-GISEL-NEXT: // GIR_Coverage, 7, // ISEL-GISEL-NEXT: GIR_Done, -// ISEL-GISEL-NEXT: // Label 8: @155 +// ISEL-GISEL-NEXT: // Label 8: @147 // ISEL-GISEL-NEXT: GIM_Reject, -// ISEL-GISEL-NEXT: // Label 3: @156 +// ISEL-GISEL-NEXT: // Label 3: @148 // ISEL-GISEL-NEXT: GIM_Reject, -// ISEL-GISEL-NEXT: // Label 1: @157 -// ISEL-GISEL-NEXT: GIM_Try, /*On fail goto*//*Label 9*/ GIMT_Encode4(275), +// ISEL-GISEL-NEXT: // Label 1: @149 +// ISEL-GISEL-NEXT: GIM_Try, /*On fail goto*//*Label 9*/ GIMT_Encode4(259), // ISEL-GISEL-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, // ISEL-GISEL-NEXT: GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, // ISEL-GISEL-NEXT: GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, // ISEL-GISEL-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::XRegsRegClassID), -// ISEL-GISEL-NEXT: GIM_Try, /*On fail goto*//*Label 10*/ GIMT_Encode4(224), +// ISEL-GISEL-NEXT: GIM_Try, /*On fail goto*//*Label 10*/ GIMT_Encode4(212), // ISEL-GISEL-NEXT: GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, // ISEL-GISEL-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::PtrRegs32RegClassID), -// ISEL-GISEL-NEXT: GIM_Try, /*On fail goto*//*Label 11*/ GIMT_Encode4(206), // Rule ID 0 // +// ISEL-GISEL-NEXT: GIM_Try, /*On fail goto*//*Label 11*/ GIMT_Encode4(196), // Rule ID 0 // // ISEL-GISEL-NEXT: GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0), // ISEL-GISEL-NEXT: // (st XRegs_EvenIfRequired:{ *:[i64] }:$val, MyPtrRC:{ *:[i32] }:$src)<><> => (MY_STORE XRegs_EvenIfRequired:{ *:[i64] }:$val, ?:{ *:[i32] }:$src) -// ISEL-GISEL-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode4(MyTarget::MY_STORE), +// ISEL-GISEL-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::MY_STORE), // ISEL-GISEL-NEXT: GIR_RootConstrainSelectedInstOperands, // ISEL-GISEL-NEXT: // GIR_Coverage, 0, // ISEL-GISEL-NEXT: GIR_Done, -// ISEL-GISEL-NEXT: // Label 11: @206 -// ISEL-GISEL-NEXT: GIM_Try, /*On fail goto*//*Label 12*/ GIMT_Encode4(223), // Rule ID 1 // +// ISEL-GISEL-NEXT: // Label 11: @196 +// ISEL-GISEL-NEXT: GIM_Try, /*On fail goto*//*Label 12*/ GIMT_Encode4(211), // Rule ID 1 // // ISEL-GISEL-NEXT: GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1), // ISEL-GISEL-NEXT: // (st XRegs_EvenIfRequired:{ *:[i64] }:$val, MyPtrRC:{ *:[i32] }:$src)<><> => (MY_STORE XRegs_EvenIfRequired:{ *:[i64] }:$val, ?:{ *:[i32] }:$src) -// ISEL-GISEL-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode4(MyTarget::MY_STORE), +// ISEL-GISEL-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::MY_STORE), // ISEL-GISEL-NEXT: GIR_RootConstrainSelectedInstOperands, // ISEL-GISEL-NEXT: // GIR_Coverage, 1, // ISEL-GISEL-NEXT: GIR_Done, -// ISEL-GISEL-NEXT: // Label 12: @223 +// ISEL-GISEL-NEXT: // Label 12: @211 // ISEL-GISEL-NEXT: GIM_Reject, -// ISEL-GISEL-NEXT: // Label 10: @224 -// ISEL-GISEL-NEXT: GIM_Try, /*On fail goto*//*Label 13*/ GIMT_Encode4(249), // Rule ID 2 // +// ISEL-GISEL-NEXT: // Label 10: @212 +// ISEL-GISEL-NEXT: GIM_Try, /*On fail goto*//*Label 13*/ GIMT_Encode4(235), // Rule ID 2 // // ISEL-GISEL-NEXT: GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2), // ISEL-GISEL-NEXT: // MIs[0] src // ISEL-GISEL-NEXT: GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, // ISEL-GISEL-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::PtrRegs32RegClassID), // ISEL-GISEL-NEXT: // (st XRegs_EvenIfRequired:{ *:[i64] }:$val, MyPtrRC:{ *:[i64] }:$src)<><> => (MY_STORE XRegs_EvenIfRequired:{ *:[i64] }:$val, ?:{ *:[i64] }:$src) -// ISEL-GISEL-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode4(MyTarget::MY_STORE), +// ISEL-GISEL-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::MY_STORE), // ISEL-GISEL-NEXT: GIR_RootConstrainSelectedInstOperands, // ISEL-GISEL-NEXT: // GIR_Coverage, 2, // ISEL-GISEL-NEXT: GIR_Done, -// ISEL-GISEL-NEXT: // Label 13: @249 -// ISEL-GISEL-NEXT: GIM_Try, /*On fail goto*//*Label 14*/ GIMT_Encode4(274), // Rule ID 3 // +// ISEL-GISEL-NEXT: // Label 13: @235 +// ISEL-GISEL-NEXT: GIM_Try, /*On fail goto*//*Label 14*/ GIMT_Encode4(258), // Rule ID 3 // // ISEL-GISEL-NEXT: GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3), // ISEL-GISEL-NEXT: // MIs[0] src // ISEL-GISEL-NEXT: GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, // ISEL-GISEL-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::PtrRegs32RegClassID), // ISEL-GISEL-NEXT: // (st XRegs_EvenIfRequired:{ *:[i64] }:$val, MyPtrRC:{ *:[i32] }:$src)<><> => (MY_STORE XRegs_EvenIfRequired:{ *:[i64] }:$val, ?:{ *:[i32] }:$src) -// ISEL-GISEL-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode4(MyTarget::MY_STORE) +// ISEL-GISEL-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::MY_STORE) // ISEL-GISEL-NEXT: GIR_RootConstrainSelectedInstOperands, // ISEL-GISEL-NEXT: // GIR_Coverage, 3, // ISEL-GISEL-NEXT: GIR_Done, -// ISEL-GISEL-NEXT: // Label 14: @274 +// ISEL-GISEL-NEXT: // Label 14: @258 // ISEL-GISEL-NEXT: GIM_Reject, -// ISEL-GISEL-NEXT: // Label 9: @275 +// ISEL-GISEL-NEXT: // Label 9: @259 // ISEL-GISEL-NEXT: GIM_Reject, -// ISEL-GISEL-NEXT: // Label 2: @276 +// ISEL-GISEL-NEXT: // Label 2: @260 // ISEL-GISEL-NEXT: GIM_Reject, -// ISEL-GISEL-NEXT: }; // Size: 277 bytes +// ISEL-GISEL-NEXT: }; // Size: 261 bytes def HasAlignedRegisters : Predicate<"Subtarget->hasAlignedRegisters()">; def HasUnalignedRegisters : Predicate<"Subtarget->hasUnalignedRegisters()">; diff --git a/llvm/test/TableGen/dag-isel-instrument.td b/llvm/test/TableGen/dag-isel-instrument.td index 1c565f7d6ba7..2862af03cf16 100644 --- a/llvm/test/TableGen/dag-isel-instrument.td +++ b/llvm/test/TableGen/dag-isel-instrument.td @@ -12,7 +12,7 @@ def REG : Register<"REG">; def GPR : RegisterClass<"TestTarget", [i32], 32, (add REG)>; // CHECK-LABEL: OPC_CheckOpcode, TARGET_VAL(ISD::UDIVREM) -// CHECK: OPC_EmitNode2None, TARGET_OUTPUT_VAL(::INSTR) +// CHECK: OPC_EmitNode2None, TARGET_VAL(::INSTR) // CHECK-NEXT: Results = #2 #3 // CHECK-NEXT: OPC_Coverage, COVERAGE_IDX_VAL(0), // CHECK-NEXT: OPC_CompleteMatch, 2, 3, 2 diff --git a/llvm/test/TableGen/dag-isel-regclass-emit-enum.td b/llvm/test/TableGen/dag-isel-regclass-emit-enum.td index 01bf67f27510..5a3b4a47953c 100644 --- a/llvm/test/TableGen/dag-isel-regclass-emit-enum.td +++ b/llvm/test/TableGen/dag-isel-regclass-emit-enum.td @@ -23,17 +23,17 @@ def GPRAbove127 : RegisterClass<"TestTarget", [i32], 32, // CHECK: OPC_CheckOpcode, TARGET_VAL(ISD::ADD), // CHECK-NEXT: OPC_RecordChild0, // #0 = $src -// CHECK-NEXT: OPC_Scope /*2 children */, 13, // ->19 +// CHECK-NEXT: OPC_Scope /*2 children */, 11, // ->17 // CHECK-NEXT: OPC_CheckChild1Integer, 0, // CHECK-NEXT: OPC_EmitIntegerI32, 0|128,1/*128*/, // #1 = TestNamespace::GPRAbove127RegClassID -// CHECK-NEXT: OPC_MorphNodeTo1None, TARGET_OUTPUT_VAL(TargetOpcode::COPY_TO_REGCLASS), +// CHECK-NEXT: OPC_MorphNodeTo1None, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), // CHECK-NEXT: MVT::i32, 2/*#Ops*/, /*OperandList*/0, // Ops = #1 #0 def : Pat<(i32 (add i32:$src, (i32 0))), (COPY_TO_REGCLASS GPRAbove127, GPR0:$src)>; // CHECK: OPC_CheckChild1Integer, 1, // CHECK-NEXT: OPC_EmitIntegerI32, TestNamespace::GPR127RegClassID, -// CHECK-NEXT: OPC_MorphNodeTo1None, TARGET_OUTPUT_VAL(TargetOpcode::COPY_TO_REGCLASS), +// CHECK-NEXT: OPC_MorphNodeTo1None, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), // CHECK-NEXT: MVT::i32, 2/*#Ops*/, /*OperandList*/0, // Ops = #1 #0 def : Pat<(i32 (add i32:$src, (i32 1))), (COPY_TO_REGCLASS GPR127, GPR0:$src)>; diff --git a/llvm/test/TableGen/dag-isel-res-order.td b/llvm/test/TableGen/dag-isel-res-order.td index 37874d1a44e9..6937dd8c6b80 100644 --- a/llvm/test/TableGen/dag-isel-res-order.td +++ b/llvm/test/TableGen/dag-isel-res-order.td @@ -12,7 +12,7 @@ def REG : Register<"REG">; def GPR : RegisterClass<"TestTarget", [i32], 32, (add REG)>; // CHECK-LABEL: OPC_CheckOpcode, TARGET_VAL(ISD::UDIVREM) -// CHECK: OPC_EmitNode2None, TARGET_OUTPUT_VAL(::INSTR) +// CHECK: OPC_EmitNode2None, TARGET_VAL(::INSTR) // CHECK: Results = #2 #3 // CHECK: OPC_CompleteMatch, 2, 3, 2 def INSTR : Instruction { diff --git a/llvm/test/TableGen/get-named-operand-idx.td b/llvm/test/TableGen/get-named-operand-idx.td index 5e6a9859f360..7982822c0a89 100644 --- a/llvm/test/TableGen/get-named-operand-idx.td +++ b/llvm/test/TableGen/get-named-operand-idx.td @@ -64,8 +64,8 @@ defm : RemapAllTargetPseudoPointerOperands; // CHECK-NEXT: NUM_OPERAND_NAMES = 5, // CHECK-NEXT: }; // enum class OpName // CHECK-EMPTY: -// CHECK-NEXT: LLVM_READONLY int16_t getNamedOperandIdx(uint32_t Opcode, OpName Name); -// CHECK-NEXT: LLVM_READONLY OpName getOperandIdxName(uint32_t Opcode, int16_t Idx); +// CHECK-NEXT: LLVM_READONLY int16_t getNamedOperandIdx(uint16_t Opcode, OpName Name); +// CHECK-NEXT: LLVM_READONLY OpName getOperandIdxName(uint16_t Opcode, int16_t Idx); // CHECK-EMPTY: // CHECK-NEXT: } // namespace llvm::MyNamespace // CHECK-EMPTY: @@ -76,7 +76,7 @@ defm : RemapAllTargetPseudoPointerOperands; // CHECK-EMPTY: // CHECK-NEXT: namespace llvm::MyNamespace { // CHECK-EMPTY: -// CHECK-NEXT: LLVM_READONLY static uint8_t getInstructionIndexForOpLookup(uint32_t Opcode) { +// CHECK-NEXT: LLVM_READONLY static uint8_t getInstructionIndexForOpLookup(uint16_t Opcode) { // CHECK-NEXT: static constexpr uint8_t InstructionIndex[] = { // CHECK-NEXT: 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // CHECK-NEXT: 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -102,7 +102,7 @@ defm : RemapAllTargetPseudoPointerOperands; // CHECK-NEXT: }; // CHECK-NEXT: return InstructionIndex[Opcode]; // CHECK-NEXT: } -// CHECK-NEXT: LLVM_READONLY int16_t getNamedOperandIdx(uint32_t Opcode, OpName Name) { +// CHECK-NEXT: LLVM_READONLY int16_t getNamedOperandIdx(uint16_t Opcode, OpName Name) { // CHECK-NEXT: assert(Name != OpName::NUM_OPERAND_NAMES); // CHECK-NEXT: static constexpr int8_t OperandMap[][5] = { // CHECK-NEXT: {-1, -1, -1, -1, -1, }, @@ -112,7 +112,7 @@ defm : RemapAllTargetPseudoPointerOperands; // CHECK-NEXT: unsigned InstrIdx = getInstructionIndexForOpLookup(Opcode); // CHECK-NEXT: return OperandMap[InstrIdx][(unsigned)Name]; // CHECK-NEXT: } -// CHECK-NEXT: LLVM_READONLY OpName getOperandIdxName(uint32_t Opcode, int16_t Idx) { +// CHECK-NEXT: LLVM_READONLY OpName getOperandIdxName(uint16_t Opcode, int16_t Idx) { // CHECK-NEXT: assert(Idx >= 0 && Idx < 3); // CHECK-NEXT: static constexpr OpName OperandMap[][3] = { // CHECK-NEXT: {OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, }, diff --git a/llvm/test/TableGen/multiple-type-casts-patfrags.td b/llvm/test/TableGen/multiple-type-casts-patfrags.td index a1d74b2528a1..39a5b042eaa6 100644 --- a/llvm/test/TableGen/multiple-type-casts-patfrags.td +++ b/llvm/test/TableGen/multiple-type-casts-patfrags.td @@ -18,20 +18,20 @@ def INSTR_FOO_I32_I16 : Instruction { let InOperandList = (ins); } -// SDAG: 7*/ OPC_SwitchType {{.*}}, 12, MVT::i16 +// SDAG: 7*/ OPC_SwitchType {{.*}}, 10, MVT::i16 // SDAG: OPC_CheckTypeRes, 1, MVT::i32 -// SDAG: OPC_MorphNodeTo2Chain, TARGET_OUTPUT_VAL(::INSTR_FOO_I16_I32) +// SDAG: OPC_MorphNodeTo2Chain, TARGET_VAL(::INSTR_FOO_I16_I32) // GISEL: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16 // GISEL: GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32 -// GISEL: GIR_BuildRootMI, /*Opcode*/GIMT_Encode4(::INSTR_FOO_I16_I32) +// GISEL: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(::INSTR_FOO_I16_I32) def : Pat<([i16, i32] (int_foo)), ([i16, i32] (INSTR_FOO_I16_I32))>; -// SDAG: 22*/ /*SwitchType*/ {{.*}} MVT::i32 +// SDAG: 20*/ /*SwitchType*/ {{.*}} MVT::i32 // SDAG: OPC_CheckTypeRes, 1, MVT::i16 -// SDAG: OPC_MorphNodeTo2Chain, TARGET_OUTPUT_VAL(::INSTR_FOO_I32_I16) +// SDAG: OPC_MorphNodeTo2Chain, TARGET_VAL(::INSTR_FOO_I32_I16) // GISEL: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32 // GISEL: GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16 -// GISEL: GIR_BuildRootMI, /*Opcode*/GIMT_Encode4(::INSTR_FOO_I32_I16) +// GISEL: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(::INSTR_FOO_I32_I16) def : Pat<([i32, i16] (int_foo)), ([i32, i16] (INSTR_FOO_I32_I16))>; diff --git a/llvm/utils/TableGen/AsmMatcherEmitter.cpp b/llvm/utils/TableGen/AsmMatcherEmitter.cpp index 00f5c033cf52..5610123f3323 100644 --- a/llvm/utils/TableGen/AsmMatcherEmitter.cpp +++ b/llvm/utils/TableGen/AsmMatcherEmitter.cpp @@ -3609,7 +3609,7 @@ void AsmMatcherEmitter::run(raw_ostream &OS) { OS << "namespace {\n"; OS << " struct MatchEntry {\n"; OS << " " << getMinimalTypeForRange(MaxMnemonicIndex) << " Mnemonic;\n"; - OS << " uint32_t Opcode;\n"; + OS << " uint16_t Opcode;\n"; OS << " " << getMinimalTypeForRange(NumConverters) << " ConvertFn;\n"; OS << " " << getMinimalTypeForRange(FeatureBitsets.size()) << " RequiredFeaturesIdx;\n"; diff --git a/llvm/utils/TableGen/CodeGenMapTable.cpp b/llvm/utils/TableGen/CodeGenMapTable.cpp index 9724493642d7..35ec495b93ba 100644 --- a/llvm/utils/TableGen/CodeGenMapTable.cpp +++ b/llvm/utils/TableGen/CodeGenMapTable.cpp @@ -25,7 +25,7 @@ // CodeGenMapTable parses this map and generates a table in XXXGenInstrInfo.inc // file that contains the instructions modeling this relationship. This table // is defined in the function -// "int getPredOpcode(uint32_t Opcode, enum PredSense inPredSense)" +// "int getPredOpcode(uint16_t Opcode, enum PredSense inPredSense)" // that can be used to retrieve the predicated form of the instruction by // passing its opcode value and the predicate sense (true/false) of the desired // instruction as arguments. @@ -381,13 +381,13 @@ unsigned MapTableEmitter::emitBinSearchTable(raw_ostream &OS) { OutStr += ", "; OutStr += ColInstr->getName(); } else { - OutStr += ", (uint32_t)-1U"; + OutStr += ", (uint16_t)-1U"; } } if (RelExists) { if (TableSize == 0) - OS << " static constexpr uint32_t Table[][" << NumCol + 1 << "] = {\n"; + OS << " static constexpr uint16_t Table[][" << NumCol + 1 << "] = {\n"; OS << " { " << CurInstr->getName() << OutStr << " },\n"; ++TableSize; } @@ -455,7 +455,7 @@ void MapTableEmitter::emitMapFuncBody(raw_ostream &OS, unsigned TableSize) { OS << ")\n"; OS << " return Table[mid][" << I + 1 << "];\n"; } - OS << " return (uint32_t)-1U;"; + OS << " return -1;"; } else { OS << " return Table[mid][1];\n"; } @@ -474,7 +474,7 @@ void MapTableEmitter::emitTablesWithFunc(raw_ostream &OS) { const ListInit *ColFields = InstrMapDesc.getColFields(); ArrayRef ValueCols = InstrMapDesc.getValueCols(); OS << "// " << InstrMapDesc.getName() << "\nLLVM_READONLY\n"; - OS << "int64_t " << InstrMapDesc.getName() << "(uint32_t Opcode"; + OS << "int " << InstrMapDesc.getName() << "(uint16_t Opcode"; if (ValueCols.size() > 1) { for (const Init *CF : ColFields->getElements()) { std::string ColName = CF->getAsUnquotedString(); diff --git a/llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.cpp b/llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.cpp index 1d9035ac12c6..bd1c3a4b9e82 100644 --- a/llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.cpp +++ b/llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.cpp @@ -2289,7 +2289,7 @@ void BuildMIAction::emitActionOpcodes(MatchTable &Table, << MatchTable::Comment("RecycleInsnID") << MatchTable::ULEB128Value(RecycleInsnID) << MatchTable::Comment("Opcode") - << MatchTable::NamedValue(4, I->Namespace, I->getName()) + << MatchTable::NamedValue(2, I->Namespace, I->getName()) << MatchTable::LineBreak; if (!I->ImplicitDefs.empty() || !I->ImplicitUses.empty()) { @@ -2337,7 +2337,7 @@ void BuildMIAction::emitActionOpcodes(MatchTable &Table, } Table << MatchTable::Comment("Opcode") - << MatchTable::NamedValue(4, I->Namespace, I->getName()) + << MatchTable::NamedValue(2, I->Namespace, I->getName()) << MatchTable::LineBreak; for (const auto &Renderer : OperandRenderers) diff --git a/llvm/utils/TableGen/DAGISelMatcherEmitter.cpp b/llvm/utils/TableGen/DAGISelMatcherEmitter.cpp index fb5cefc0dfd0..1058e7567805 100644 --- a/llvm/utils/TableGen/DAGISelMatcherEmitter.cpp +++ b/llvm/utils/TableGen/DAGISelMatcherEmitter.cpp @@ -1094,7 +1094,7 @@ unsigned MatcherTableEmitter::EmitMatcher(const Matcher *N, OS << "ByHwMode"; const CodeGenInstruction &CGI = EN->getInstruction(); - OS << ", TARGET_OUTPUT_VAL(" << CGI.Namespace << "::" << CGI.TheDef->getName() + OS << ", TARGET_VAL(" << CGI.Namespace << "::" << CGI.TheDef->getName() << ")"; if (!CompressNodeInfo) { @@ -1188,7 +1188,7 @@ unsigned MatcherTableEmitter::EmitMatcher(const Matcher *N, OS << '\n'; } - return 6 + SupportsDeactivationSymbol + !CompressVTs + !CompressNodeInfo + + return 4 + SupportsDeactivationSymbol + !CompressVTs + !CompressNodeInfo + NumTypeBytes + NumOperandBytes + NumCoveredBytes; } case Matcher::CompleteMatch: { @@ -1579,13 +1579,11 @@ void llvm::EmitMatcherTable(Matcher *TheMatcher, const CodeGenDAGPatterns &CGP, // final stream. OS << "{\n"; OS << " // Some target values are emitted as 2 bytes, TARGET_VAL handles\n"; - OS << " // this. Output opcodes are emitted as 4 bytes. TARGET_OUTPUT_VAL\n"; - OS << " // handles that. Coverage indexes are emitted as 4 bytes,\n"; + OS << " // this. Coverage indexes are emitted as 4 bytes,\n"; OS << " // COVERAGE_IDX_VAL handles this.\n"; OS << " #define TARGET_VAL(X) X & 255, unsigned(X) >> 8\n"; - OS << " #define TARGET_OUTPUT_VAL(X) X & 255, (unsigned(X) >> 8) & 255, "; + OS << " #define COVERAGE_IDX_VAL(X) X & 255, (unsigned(X) >> 8) & 255, "; OS << "(unsigned(X) >> 16) & 255, (unsigned(X) >> 24) & 255\n"; - OS << " #define COVERAGE_IDX_VAL(X) TARGET_OUTPUT_VAL(X)\n"; OS << " static const uint8_t MatcherTable[] = {\n"; TotalSize = MatcherEmitter.EmitMatcherList(TheMatcher, 1, 0, OS); OS << " }; // Total Array size is " << TotalSize << " bytes\n\n"; @@ -1597,7 +1595,6 @@ void llvm::EmitMatcherTable(Matcher *TheMatcher, const CodeGenDAGPatterns &CGP, OS << " };\n\n"; OS << " #undef COVERAGE_IDX_VAL\n"; - OS << " #undef TARGET_OUTPUT_VAL\n"; OS << " #undef TARGET_VAL\n"; OS << " SelectCodeCommon(N, MatcherTable, sizeof(MatcherTable),\n"; OS << " OperandLists);\n"; diff --git a/llvm/utils/TableGen/InstrInfoEmitter.cpp b/llvm/utils/TableGen/InstrInfoEmitter.cpp index 08526cc2a72b..8442ad0dc0ed 100644 --- a/llvm/utils/TableGen/InstrInfoEmitter.cpp +++ b/llvm/utils/TableGen/InstrInfoEmitter.cpp @@ -261,7 +261,7 @@ static void emitGetInstructionIndexForOpLookup( ArrayRef InstructionIndex) { StringRef Type = OperandMap.size() <= UINT8_MAX + 1 ? "uint8_t" : "uint16_t"; OS << "LLVM_READONLY static " << Type - << " getInstructionIndexForOpLookup(uint32_t Opcode) {\n" + << " getInstructionIndexForOpLookup(uint16_t Opcode) {\n" " static constexpr " << Type << " InstructionIndex[] = {"; for (auto [TableIndex, Entry] : enumerate(InstructionIndex)) @@ -275,7 +275,7 @@ static void emitGetNamedOperandIdx(raw_ostream &OS, const MapVector, unsigned> &OperandMap, unsigned MaxOperandNo, unsigned NumOperandNames) { - OS << "LLVM_READONLY int16_t getNamedOperandIdx(uint32_t Opcode, OpName " + OS << "LLVM_READONLY int16_t getNamedOperandIdx(uint16_t Opcode, OpName " "Name) {\n"; OS << " assert(Name != OpName::NUM_OPERAND_NAMES);\n"; if (!NumOperandNames) { @@ -307,7 +307,7 @@ emitGetOperandIdxName(raw_ostream &OS, const MapVector &OperandNameToID, const MapVector, unsigned> &OperandMap, unsigned MaxNumOperands, unsigned NumOperandNames) { - OS << "LLVM_READONLY OpName getOperandIdxName(uint32_t Opcode, int16_t Idx) " + OS << "LLVM_READONLY OpName getOperandIdxName(uint16_t Opcode, int16_t Idx) " "{\n"; OS << " assert(Idx >= 0 && Idx < " << MaxNumOperands << ");\n"; if (!MaxNumOperands) { @@ -347,11 +347,11 @@ emitGetOperandIdxName(raw_ostream &OS, /// - An enum in the llvm::TargetNamespace::OpName namespace, with one entry /// for each operand name. /// - A 2-dimensional table for mapping OpName enum values to operand indices. -/// - A function called getNamedOperandIdx(uint32_t Opcode, OpName Name) +/// - A function called getNamedOperandIdx(uint16_t Opcode, OpName Name) /// for looking up the operand index for an instruction, given a value from /// OpName enum /// - A 2-dimensional table for mapping operand indices to OpName enum values. -/// - A function called getOperandIdxName(uint32_t Opcode, int16_t Idx) +/// - A function called getOperandIdxName(uint16_t Opcode, int16_t Idx) /// for looking up the OpName enum for an instruction, given the operand /// index. This is the inverse of getNamedOperandIdx(). /// @@ -414,9 +414,9 @@ void InstrInfoEmitter::emitOperandNameMappings( OS << " NUM_OPERAND_NAMES = " << NumOperandNames << ",\n"; OS << "}; // enum class OpName\n\n"; - OS << "LLVM_READONLY int16_t getNamedOperandIdx(uint32_t Opcode, OpName " + OS << "LLVM_READONLY int16_t getNamedOperandIdx(uint16_t Opcode, OpName " "Name);\n"; - OS << "LLVM_READONLY OpName getOperandIdxName(uint32_t Opcode, int16_t " + OS << "LLVM_READONLY OpName getOperandIdxName(uint16_t Opcode, int16_t " "Idx);\n"; } @@ -476,7 +476,7 @@ void InstrInfoEmitter::emitOperandTypeMappings( IfDefEmitter IfDef(OS, "GET_INSTRINFO_OPERAND_TYPE"); NamespaceEmitter NS(OS, ("llvm::" + Namespace).str()); OS << "LLVM_READONLY\n"; - OS << "static int getOperandType(uint32_t Opcode, uint16_t OpIdx) {\n"; + OS << "static int getOperandType(uint16_t Opcode, uint16_t OpIdx) {\n"; auto getInstrName = [&](int I) -> StringRef { return NumberedInstructions[I]->getName(); }; @@ -604,7 +604,7 @@ void InstrInfoEmitter::emitLogicalOperandSizeMappings( IfDefEmitter IfDef(OS, "GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP"); NamespaceEmitter NS(OS, ("llvm::" + Namespace).str()); OS << "LLVM_READONLY static unsigned\n"; - OS << "getLogicalOperandSize(uint32_t Opcode, uint16_t LogicalOpIdx) {\n"; + OS << "getLogicalOperandSize(uint16_t Opcode, uint16_t LogicalOpIdx) {\n"; if (!InstMap.empty()) { std::vector *> LogicalOpSizeList( LogicalOpSizeMap.size()); @@ -644,7 +644,7 @@ void InstrInfoEmitter::emitLogicalOperandSizeMappings( OS << "}\n"; OS << "LLVM_READONLY static inline unsigned\n"; - OS << "getLogicalOperandIdx(uint32_t Opcode, uint16_t LogicalOpIdx) {\n"; + OS << "getLogicalOperandIdx(uint16_t Opcode, uint16_t LogicalOpIdx) {\n"; OS << " auto S = 0U;\n"; OS << " for (auto i = 0U; i < LogicalOpIdx; ++i)\n"; OS << " S += getLogicalOperandSize(Opcode, i);\n";