[AMDGPU] Do not fold COPY with implicit operands (#136003)
Folding may remove COPY from inside of the divergent loop.
This commit is contained in:
Mariusz Sikora
GitHub
parent
d7d1706564
commit
1a48e1df45
@ -1091,7 +1091,8 @@ void SIFoldOperandsImpl::foldOperand(
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} else {
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if (UseMI->isCopy() && OpToFold.isReg() &&
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UseMI->getOperand(0).getReg().isVirtual() &&
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!UseMI->getOperand(1).getSubReg()) {
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!UseMI->getOperand(1).getSubReg() &&
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OpToFold.getParent()->implicit_operands().empty()) {
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LLVM_DEBUG(dbgs() << "Folding " << OpToFold << "\n into " << *UseMI);
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unsigned Size = TII->getOpSize(*UseMI, 1);
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Register UseReg = OpToFold.getReg();
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56
llvm/test/CodeGen/AMDGPU/do-not-fold-copy.mir
Normal file
56
llvm/test/CodeGen/AMDGPU/do-not-fold-copy.mir
Normal file
@ -0,0 +1,56 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
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# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -run-pass=si-fold-operands -o - %s | FileCheck %s
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---
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liveins:
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name: do_not_fold_copy_with_implicit_exec
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tracksRegLiveness: true
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body: |
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; CHECK-LABEL: name: do_not_fold_copy_with_implicit_exec
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; CHECK: bb.0:
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; CHECK-NEXT: successors: %bb.1(0x80000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 0
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; CHECK-NEXT: [[S_MOV_B64_1:%[0-9]+]]:sreg_64 = S_MOV_B64 0
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; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0, implicit $exec
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; CHECK-NEXT: S_BRANCH %bb.1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.1:
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; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[PHI:%[0-9]+]]:sreg_64 = PHI [[S_MOV_B64_1]], %bb.0, %4, %bb.1
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; CHECK-NEXT: [[PHI1:%[0-9]+]]:sreg_32 = PHI [[S_MOV_B32_]], %bb.0, %6, %bb.1
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; CHECK-NEXT: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[PHI1]], 1, implicit-def dead $scc
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; CHECK-NEXT: [[SI_IF_BREAK:%[0-9]+]]:sreg_64 = SI_IF_BREAK [[S_MOV_B64_]], [[PHI]], implicit-def dead $scc
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; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[S_ADD_I32_]], implicit $exec
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; CHECK-NEXT: SI_LOOP [[SI_IF_BREAK]], %bb.1, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
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; CHECK-NEXT: S_BRANCH %bb.2
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.2:
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; CHECK-NEXT: SI_END_CF [[SI_IF_BREAK]], implicit-def dead $exec, implicit-def dead $scc, implicit $exec
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; CHECK-NEXT: [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
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; CHECK-NEXT: [[V_SET_INACTIVE_B32_:%[0-9]+]]:vgpr_32 = V_SET_INACTIVE_B32 0, [[COPY]], 0, 0, killed [[DEF]], implicit $exec
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; CHECK-NEXT: S_ENDPGM 0
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bb.0:
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%0:sreg_64 = S_MOV_B64 0
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%1:sreg_64 = S_MOV_B64 0
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%2:sreg_32 = S_MOV_B32 0, implicit $exec
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S_BRANCH %bb.1
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bb.1:
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%3:sreg_64 = PHI %1, %bb.0, %4, %bb.1
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%5:sreg_32 = PHI %2, %bb.0, %6, %bb.1
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%6:sreg_32 = S_ADD_I32 %5, 1, implicit-def dead $scc
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%4:sreg_64 = SI_IF_BREAK %0, %3, implicit-def dead $scc
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%7:vgpr_32 = COPY %6, implicit $exec
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SI_LOOP %4, %bb.1, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
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S_BRANCH %bb.2
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bb.2:
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SI_END_CF %4, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
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%9:vgpr_32 = COPY %7
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%10:sreg_64_xexec = IMPLICIT_DEF
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%11:vgpr_32 = V_SET_INACTIVE_B32 0, %9, 0, 0, killed %10, implicit $exec
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S_ENDPGM 0
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...
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@ -429,13 +429,14 @@ define amdgpu_cs_chain void @control_flow(<3 x i32> inreg %sgpr, ptr inreg %call
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; DAGISEL12-NEXT: v_cmp_ne_u32_e64 s9, 0, v0
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; DAGISEL12-NEXT: s_mov_b32 exec_lo, s8
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; DAGISEL12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v13, v1
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; DAGISEL12-NEXT: v_mov_b32_e32 v11, s9
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; DAGISEL12-NEXT: s_or_b32 s4, vcc_lo, s4
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; DAGISEL12-NEXT: s_wait_alu 0xfffe
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; DAGISEL12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s4
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; DAGISEL12-NEXT: s_cbranch_execnz .LBB3_2
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; DAGISEL12-NEXT: ; %bb.3: ; %tail.loopexit
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; DAGISEL12-NEXT: s_or_b32 exec_lo, exec_lo, s4
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; DAGISEL12-NEXT: v_dual_mov_b32 v11, s9 :: v_dual_add_nc_u32 v10, 42, v1
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; DAGISEL12-NEXT: v_add_nc_u32_e32 v10, 42, v1
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; DAGISEL12-NEXT: .LBB3_4: ; %Flow1
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; DAGISEL12-NEXT: s_wait_alu 0xfffe
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; DAGISEL12-NEXT: s_or_b32 exec_lo, exec_lo, s3
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@ -526,13 +527,13 @@ define amdgpu_cs_chain void @control_flow(<3 x i32> inreg %sgpr, ptr inreg %call
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; DAGISEL10-NEXT: v_cmp_ne_u32_e64 s9, 0, v0
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; DAGISEL10-NEXT: s_mov_b32 exec_lo, s8
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; DAGISEL10-NEXT: v_cmp_eq_u32_e32 vcc_lo, v13, v1
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; DAGISEL10-NEXT: v_mov_b32_e32 v11, s9
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; DAGISEL10-NEXT: s_or_b32 s4, vcc_lo, s4
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; DAGISEL10-NEXT: s_andn2_b32 exec_lo, exec_lo, s4
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; DAGISEL10-NEXT: s_cbranch_execnz .LBB3_2
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; DAGISEL10-NEXT: ; %bb.3: ; %tail.loopexit
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; DAGISEL10-NEXT: s_or_b32 exec_lo, exec_lo, s4
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; DAGISEL10-NEXT: v_add_nc_u32_e32 v10, 42, v1
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; DAGISEL10-NEXT: v_mov_b32_e32 v11, s9
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; DAGISEL10-NEXT: .LBB3_4: ; %Flow1
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; DAGISEL10-NEXT: s_or_b32 exec_lo, exec_lo, s3
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; DAGISEL10-NEXT: s_mov_b32 s3, exec_lo
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@ -1425,41 +1425,42 @@ define amdgpu_kernel void @test_mfma_loop_sgpr_init(ptr addrspace(1) %arg, float
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; GFX90A: ; %bb.0: ; %entry
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; GFX90A-NEXT: s_load_dword s1, s[4:5], 0x2c
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; GFX90A-NEXT: s_mov_b32 s0, 16
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; GFX90A-NEXT: v_mov_b32_e32 v0, 2.0
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; GFX90A-NEXT: v_mov_b32_e32 v1, 1.0
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; GFX90A-NEXT: s_waitcnt lgkmcnt(0)
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; GFX90A-NEXT: v_accvgpr_write_b32 a31, s1
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; GFX90A-NEXT: v_accvgpr_write_b32 a30, s1
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; GFX90A-NEXT: v_accvgpr_write_b32 a29, s1
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; GFX90A-NEXT: v_accvgpr_write_b32 a28, s1
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; GFX90A-NEXT: v_accvgpr_write_b32 a27, s1
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; GFX90A-NEXT: v_accvgpr_write_b32 a26, s1
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; GFX90A-NEXT: v_accvgpr_write_b32 a25, s1
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; GFX90A-NEXT: v_accvgpr_write_b32 a24, s1
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; GFX90A-NEXT: v_accvgpr_write_b32 a23, s1
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; GFX90A-NEXT: v_accvgpr_write_b32 a22, s1
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; GFX90A-NEXT: v_accvgpr_write_b32 a21, s1
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; GFX90A-NEXT: v_accvgpr_write_b32 a20, s1
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; GFX90A-NEXT: v_accvgpr_write_b32 a19, s1
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; GFX90A-NEXT: v_accvgpr_write_b32 a18, s1
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; GFX90A-NEXT: v_accvgpr_write_b32 a17, s1
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; GFX90A-NEXT: v_accvgpr_write_b32 a16, s1
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; GFX90A-NEXT: v_accvgpr_write_b32 a15, s1
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; GFX90A-NEXT: v_accvgpr_write_b32 a14, s1
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; GFX90A-NEXT: v_accvgpr_write_b32 a13, s1
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; GFX90A-NEXT: v_accvgpr_write_b32 a12, s1
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; GFX90A-NEXT: v_accvgpr_write_b32 a11, s1
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; GFX90A-NEXT: v_accvgpr_write_b32 a10, s1
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; GFX90A-NEXT: v_accvgpr_write_b32 a9, s1
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; GFX90A-NEXT: v_accvgpr_write_b32 a8, s1
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; GFX90A-NEXT: v_accvgpr_write_b32 a7, s1
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; GFX90A-NEXT: v_accvgpr_write_b32 a6, s1
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; GFX90A-NEXT: v_accvgpr_write_b32 a5, s1
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; GFX90A-NEXT: v_accvgpr_write_b32 a4, s1
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; GFX90A-NEXT: v_accvgpr_write_b32 a3, s1
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; GFX90A-NEXT: v_accvgpr_write_b32 a2, s1
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; GFX90A-NEXT: v_accvgpr_write_b32 a1, s1
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; GFX90A-NEXT: v_accvgpr_write_b32 a0, s1
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; GFX90A-NEXT: v_mov_b32_e32 v0, s1
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; GFX90A-NEXT: v_accvgpr_write_b32 a31, v0
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; GFX90A-NEXT: v_accvgpr_write_b32 a30, v0
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; GFX90A-NEXT: v_accvgpr_write_b32 a29, v0
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; GFX90A-NEXT: v_accvgpr_write_b32 a28, v0
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; GFX90A-NEXT: v_accvgpr_write_b32 a27, v0
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; GFX90A-NEXT: v_accvgpr_write_b32 a26, v0
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; GFX90A-NEXT: v_accvgpr_write_b32 a25, v0
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; GFX90A-NEXT: v_accvgpr_write_b32 a24, v0
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; GFX90A-NEXT: v_accvgpr_write_b32 a23, v0
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; GFX90A-NEXT: v_accvgpr_write_b32 a22, v0
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; GFX90A-NEXT: v_accvgpr_write_b32 a21, v0
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; GFX90A-NEXT: v_accvgpr_write_b32 a20, v0
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; GFX90A-NEXT: v_accvgpr_write_b32 a19, v0
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; GFX90A-NEXT: v_accvgpr_write_b32 a18, v0
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; GFX90A-NEXT: v_accvgpr_write_b32 a17, v0
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; GFX90A-NEXT: v_accvgpr_write_b32 a16, v0
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; GFX90A-NEXT: v_accvgpr_write_b32 a15, v0
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; GFX90A-NEXT: v_accvgpr_write_b32 a14, v0
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; GFX90A-NEXT: v_accvgpr_write_b32 a13, v0
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; GFX90A-NEXT: v_accvgpr_write_b32 a12, v0
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; GFX90A-NEXT: v_accvgpr_write_b32 a11, v0
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; GFX90A-NEXT: v_accvgpr_write_b32 a10, v0
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; GFX90A-NEXT: v_accvgpr_write_b32 a9, v0
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; GFX90A-NEXT: v_accvgpr_write_b32 a8, v0
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; GFX90A-NEXT: v_accvgpr_write_b32 a7, v0
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; GFX90A-NEXT: v_accvgpr_write_b32 a6, v0
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; GFX90A-NEXT: v_accvgpr_write_b32 a5, v0
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; GFX90A-NEXT: v_accvgpr_write_b32 a4, v0
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; GFX90A-NEXT: v_accvgpr_write_b32 a3, v0
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; GFX90A-NEXT: v_accvgpr_write_b32 a2, v0
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; GFX90A-NEXT: v_accvgpr_write_b32 a1, v0
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; GFX90A-NEXT: v_accvgpr_write_b32 a0, v0
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; GFX90A-NEXT: v_mov_b32_e32 v0, 2.0
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; GFX90A-NEXT: .LBB5_1: ; %for.cond.preheader
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; GFX90A-NEXT: ; =>This Inner Loop Header: Depth=1
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; GFX90A-NEXT: s_nop 1
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@ -1487,41 +1488,42 @@ define amdgpu_kernel void @test_mfma_loop_sgpr_init(ptr addrspace(1) %arg, float
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; GFX942: ; %bb.0: ; %entry
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; GFX942-NEXT: s_load_dword s1, s[4:5], 0x2c
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; GFX942-NEXT: s_mov_b32 s0, 16
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; GFX942-NEXT: v_mov_b32_e32 v0, 2.0
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; GFX942-NEXT: v_mov_b32_e32 v1, 1.0
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; GFX942-NEXT: s_waitcnt lgkmcnt(0)
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; GFX942-NEXT: v_accvgpr_write_b32 a31, s1
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; GFX942-NEXT: v_accvgpr_write_b32 a30, s1
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; GFX942-NEXT: v_accvgpr_write_b32 a29, s1
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; GFX942-NEXT: v_accvgpr_write_b32 a28, s1
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; GFX942-NEXT: v_accvgpr_write_b32 a27, s1
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; GFX942-NEXT: v_accvgpr_write_b32 a26, s1
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; GFX942-NEXT: v_accvgpr_write_b32 a25, s1
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; GFX942-NEXT: v_accvgpr_write_b32 a24, s1
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; GFX942-NEXT: v_accvgpr_write_b32 a23, s1
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; GFX942-NEXT: v_accvgpr_write_b32 a22, s1
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; GFX942-NEXT: v_accvgpr_write_b32 a21, s1
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; GFX942-NEXT: v_accvgpr_write_b32 a20, s1
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; GFX942-NEXT: v_accvgpr_write_b32 a19, s1
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; GFX942-NEXT: v_accvgpr_write_b32 a18, s1
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; GFX942-NEXT: v_accvgpr_write_b32 a17, s1
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; GFX942-NEXT: v_accvgpr_write_b32 a16, s1
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; GFX942-NEXT: v_accvgpr_write_b32 a15, s1
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; GFX942-NEXT: v_accvgpr_write_b32 a14, s1
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; GFX942-NEXT: v_accvgpr_write_b32 a13, s1
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; GFX942-NEXT: v_accvgpr_write_b32 a12, s1
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; GFX942-NEXT: v_accvgpr_write_b32 a11, s1
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; GFX942-NEXT: v_accvgpr_write_b32 a10, s1
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; GFX942-NEXT: v_accvgpr_write_b32 a9, s1
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; GFX942-NEXT: v_accvgpr_write_b32 a8, s1
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; GFX942-NEXT: v_accvgpr_write_b32 a7, s1
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; GFX942-NEXT: v_accvgpr_write_b32 a6, s1
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; GFX942-NEXT: v_accvgpr_write_b32 a5, s1
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; GFX942-NEXT: v_accvgpr_write_b32 a4, s1
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; GFX942-NEXT: v_accvgpr_write_b32 a3, s1
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; GFX942-NEXT: v_accvgpr_write_b32 a2, s1
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; GFX942-NEXT: v_accvgpr_write_b32 a1, s1
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; GFX942-NEXT: v_accvgpr_write_b32 a0, s1
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; GFX942-NEXT: v_mov_b32_e32 v0, s1
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; GFX942-NEXT: v_accvgpr_write_b32 a31, v0
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; GFX942-NEXT: v_accvgpr_write_b32 a30, v0
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; GFX942-NEXT: v_accvgpr_write_b32 a29, v0
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; GFX942-NEXT: v_accvgpr_write_b32 a28, v0
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; GFX942-NEXT: v_accvgpr_write_b32 a27, v0
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; GFX942-NEXT: v_accvgpr_write_b32 a26, v0
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; GFX942-NEXT: v_accvgpr_write_b32 a25, v0
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; GFX942-NEXT: v_accvgpr_write_b32 a24, v0
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; GFX942-NEXT: v_accvgpr_write_b32 a23, v0
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; GFX942-NEXT: v_accvgpr_write_b32 a22, v0
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; GFX942-NEXT: v_accvgpr_write_b32 a21, v0
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; GFX942-NEXT: v_accvgpr_write_b32 a20, v0
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; GFX942-NEXT: v_accvgpr_write_b32 a19, v0
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; GFX942-NEXT: v_accvgpr_write_b32 a18, v0
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; GFX942-NEXT: v_accvgpr_write_b32 a17, v0
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; GFX942-NEXT: v_accvgpr_write_b32 a16, v0
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; GFX942-NEXT: v_accvgpr_write_b32 a15, v0
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; GFX942-NEXT: v_accvgpr_write_b32 a14, v0
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; GFX942-NEXT: v_accvgpr_write_b32 a13, v0
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; GFX942-NEXT: v_accvgpr_write_b32 a12, v0
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; GFX942-NEXT: v_accvgpr_write_b32 a11, v0
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; GFX942-NEXT: v_accvgpr_write_b32 a10, v0
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; GFX942-NEXT: v_accvgpr_write_b32 a9, v0
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; GFX942-NEXT: v_accvgpr_write_b32 a8, v0
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; GFX942-NEXT: v_accvgpr_write_b32 a7, v0
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; GFX942-NEXT: v_accvgpr_write_b32 a6, v0
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; GFX942-NEXT: v_accvgpr_write_b32 a5, v0
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; GFX942-NEXT: v_accvgpr_write_b32 a4, v0
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; GFX942-NEXT: v_accvgpr_write_b32 a3, v0
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; GFX942-NEXT: v_accvgpr_write_b32 a2, v0
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; GFX942-NEXT: v_accvgpr_write_b32 a1, v0
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; GFX942-NEXT: v_accvgpr_write_b32 a0, v0
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; GFX942-NEXT: v_mov_b32_e32 v0, 2.0
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; GFX942-NEXT: .LBB5_1: ; %for.cond.preheader
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; GFX942-NEXT: ; =>This Inner Loop Header: Depth=1
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; GFX942-NEXT: s_nop 1
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@ -1696,6 +1698,8 @@ define amdgpu_kernel void @test_mfma_loop_mixed_init(ptr addrspace(1) %arg, floa
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; GFX90A-NEXT: v_accvgpr_write_b32 a0, v0
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; GFX90A-NEXT: v_accvgpr_write_b32 a31, 0
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; GFX90A-NEXT: v_accvgpr_write_b32 a30, 0
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; GFX90A-NEXT: s_waitcnt lgkmcnt(0)
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; GFX90A-NEXT: v_mov_b32_e32 v0, s1
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; GFX90A-NEXT: v_accvgpr_write_b32 a29, 0
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; GFX90A-NEXT: v_accvgpr_write_b32 a28, 0
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; GFX90A-NEXT: v_accvgpr_write_b32 a27, 0
|
||||
@ -1725,8 +1729,7 @@ define amdgpu_kernel void @test_mfma_loop_mixed_init(ptr addrspace(1) %arg, floa
|
||||
; GFX90A-NEXT: v_accvgpr_write_b32 a3, 0
|
||||
; GFX90A-NEXT: v_accvgpr_write_b32 a2, 0
|
||||
; GFX90A-NEXT: s_mov_b32 s0, 16
|
||||
; GFX90A-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX90A-NEXT: v_accvgpr_write_b32 a1, s1
|
||||
; GFX90A-NEXT: v_accvgpr_write_b32 a1, v0
|
||||
; GFX90A-NEXT: v_mov_b32_e32 v0, 2.0
|
||||
; GFX90A-NEXT: v_mov_b32_e32 v1, 1.0
|
||||
; GFX90A-NEXT: .LBB6_1: ; %for.cond.preheader
|
||||
@ -1759,6 +1762,8 @@ define amdgpu_kernel void @test_mfma_loop_mixed_init(ptr addrspace(1) %arg, floa
|
||||
; GFX942-NEXT: v_accvgpr_write_b32 a0, v0
|
||||
; GFX942-NEXT: v_accvgpr_write_b32 a31, 0
|
||||
; GFX942-NEXT: v_accvgpr_write_b32 a30, 0
|
||||
; GFX942-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX942-NEXT: v_mov_b32_e32 v0, s1
|
||||
; GFX942-NEXT: v_accvgpr_write_b32 a29, 0
|
||||
; GFX942-NEXT: v_accvgpr_write_b32 a28, 0
|
||||
; GFX942-NEXT: v_accvgpr_write_b32 a27, 0
|
||||
@ -1788,8 +1793,7 @@ define amdgpu_kernel void @test_mfma_loop_mixed_init(ptr addrspace(1) %arg, floa
|
||||
; GFX942-NEXT: v_accvgpr_write_b32 a3, 0
|
||||
; GFX942-NEXT: v_accvgpr_write_b32 a2, 0
|
||||
; GFX942-NEXT: s_mov_b32 s0, 16
|
||||
; GFX942-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX942-NEXT: v_accvgpr_write_b32 a1, s1
|
||||
; GFX942-NEXT: v_accvgpr_write_b32 a1, v0
|
||||
; GFX942-NEXT: v_mov_b32_e32 v0, 2.0
|
||||
; GFX942-NEXT: v_mov_b32_e32 v1, 1.0
|
||||
; GFX942-NEXT: .LBB6_1: ; %for.cond.preheader
|
||||
@ -2050,66 +2054,38 @@ define amdgpu_kernel void @test_mfma_loop_agpr_init(ptr addrspace(1) %arg) #0 {
|
||||
; GFX908-NEXT: s_nop 7
|
||||
; GFX908-NEXT: s_nop 1
|
||||
; GFX908-NEXT: v_accvgpr_read_b32 v2, a0
|
||||
; GFX908-NEXT: v_accvgpr_read_b32 v3, a0
|
||||
; GFX908-NEXT: v_accvgpr_read_b32 v33, a0
|
||||
; GFX908-NEXT: s_nop 1
|
||||
; GFX908-NEXT: v_accvgpr_write_b32 a0, v2
|
||||
; GFX908-NEXT: v_accvgpr_write_b32 a1, v2
|
||||
; GFX908-NEXT: v_accvgpr_read_b32 v2, a0
|
||||
; GFX908-NEXT: v_accvgpr_write_b32 a2, v3
|
||||
; GFX908-NEXT: v_accvgpr_write_b32 a3, v33
|
||||
; GFX908-NEXT: v_accvgpr_write_b32 a2, v2
|
||||
; GFX908-NEXT: v_accvgpr_write_b32 a3, v2
|
||||
; GFX908-NEXT: v_accvgpr_write_b32 a4, v2
|
||||
; GFX908-NEXT: v_accvgpr_read_b32 v3, a0
|
||||
; GFX908-NEXT: v_accvgpr_read_b32 v33, a0
|
||||
; GFX908-NEXT: v_accvgpr_read_b32 v2, a0
|
||||
; GFX908-NEXT: v_accvgpr_write_b32 a5, v3
|
||||
; GFX908-NEXT: v_accvgpr_write_b32 a6, v33
|
||||
; GFX908-NEXT: v_accvgpr_write_b32 a5, v2
|
||||
; GFX908-NEXT: v_accvgpr_write_b32 a6, v2
|
||||
; GFX908-NEXT: v_accvgpr_write_b32 a7, v2
|
||||
; GFX908-NEXT: v_accvgpr_read_b32 v3, a0
|
||||
; GFX908-NEXT: v_accvgpr_read_b32 v33, a0
|
||||
; GFX908-NEXT: v_accvgpr_read_b32 v2, a0
|
||||
; GFX908-NEXT: v_accvgpr_write_b32 a8, v3
|
||||
; GFX908-NEXT: v_accvgpr_write_b32 a9, v33
|
||||
; GFX908-NEXT: v_accvgpr_write_b32 a8, v2
|
||||
; GFX908-NEXT: v_accvgpr_write_b32 a9, v2
|
||||
; GFX908-NEXT: v_accvgpr_write_b32 a10, v2
|
||||
; GFX908-NEXT: v_accvgpr_read_b32 v3, a0
|
||||
; GFX908-NEXT: v_accvgpr_read_b32 v33, a0
|
||||
; GFX908-NEXT: v_accvgpr_read_b32 v2, a0
|
||||
; GFX908-NEXT: v_accvgpr_write_b32 a11, v3
|
||||
; GFX908-NEXT: v_accvgpr_write_b32 a12, v33
|
||||
; GFX908-NEXT: v_accvgpr_write_b32 a11, v2
|
||||
; GFX908-NEXT: v_accvgpr_write_b32 a12, v2
|
||||
; GFX908-NEXT: v_accvgpr_write_b32 a13, v2
|
||||
; GFX908-NEXT: v_accvgpr_read_b32 v3, a0
|
||||
; GFX908-NEXT: v_accvgpr_read_b32 v33, a0
|
||||
; GFX908-NEXT: v_accvgpr_read_b32 v2, a0
|
||||
; GFX908-NEXT: v_accvgpr_write_b32 a14, v3
|
||||
; GFX908-NEXT: v_accvgpr_write_b32 a15, v33
|
||||
; GFX908-NEXT: v_accvgpr_write_b32 a14, v2
|
||||
; GFX908-NEXT: v_accvgpr_write_b32 a15, v2
|
||||
; GFX908-NEXT: v_accvgpr_write_b32 a16, v2
|
||||
; GFX908-NEXT: v_accvgpr_read_b32 v3, a0
|
||||
; GFX908-NEXT: v_accvgpr_read_b32 v33, a0
|
||||
; GFX908-NEXT: v_accvgpr_read_b32 v2, a0
|
||||
; GFX908-NEXT: v_accvgpr_write_b32 a17, v3
|
||||
; GFX908-NEXT: v_accvgpr_write_b32 a18, v33
|
||||
; GFX908-NEXT: v_accvgpr_write_b32 a17, v2
|
||||
; GFX908-NEXT: v_accvgpr_write_b32 a18, v2
|
||||
; GFX908-NEXT: v_accvgpr_write_b32 a19, v2
|
||||
; GFX908-NEXT: v_accvgpr_read_b32 v3, a0
|
||||
; GFX908-NEXT: v_accvgpr_read_b32 v33, a0
|
||||
; GFX908-NEXT: v_accvgpr_read_b32 v2, a0
|
||||
; GFX908-NEXT: v_accvgpr_write_b32 a20, v3
|
||||
; GFX908-NEXT: v_accvgpr_write_b32 a21, v33
|
||||
; GFX908-NEXT: v_accvgpr_write_b32 a20, v2
|
||||
; GFX908-NEXT: v_accvgpr_write_b32 a21, v2
|
||||
; GFX908-NEXT: v_accvgpr_write_b32 a22, v2
|
||||
; GFX908-NEXT: v_accvgpr_read_b32 v3, a0
|
||||
; GFX908-NEXT: v_accvgpr_read_b32 v33, a0
|
||||
; GFX908-NEXT: v_accvgpr_read_b32 v2, a0
|
||||
; GFX908-NEXT: v_accvgpr_write_b32 a23, v3
|
||||
; GFX908-NEXT: v_accvgpr_write_b32 a24, v33
|
||||
; GFX908-NEXT: v_accvgpr_write_b32 a23, v2
|
||||
; GFX908-NEXT: v_accvgpr_write_b32 a24, v2
|
||||
; GFX908-NEXT: v_accvgpr_write_b32 a25, v2
|
||||
; GFX908-NEXT: v_accvgpr_read_b32 v3, a0
|
||||
; GFX908-NEXT: v_accvgpr_read_b32 v33, a0
|
||||
; GFX908-NEXT: v_accvgpr_read_b32 v2, a0
|
||||
; GFX908-NEXT: v_accvgpr_write_b32 a26, v3
|
||||
; GFX908-NEXT: v_accvgpr_write_b32 a27, v33
|
||||
; GFX908-NEXT: v_accvgpr_write_b32 a26, v2
|
||||
; GFX908-NEXT: v_accvgpr_write_b32 a27, v2
|
||||
; GFX908-NEXT: v_accvgpr_write_b32 a28, v2
|
||||
; GFX908-NEXT: v_accvgpr_read_b32 v3, a0
|
||||
; GFX908-NEXT: v_accvgpr_read_b32 v33, a0
|
||||
; GFX908-NEXT: v_accvgpr_read_b32 v2, a0
|
||||
; GFX908-NEXT: v_accvgpr_write_b32 a29, v3
|
||||
; GFX908-NEXT: v_accvgpr_write_b32 a30, v33
|
||||
; GFX908-NEXT: v_accvgpr_write_b32 a29, v2
|
||||
; GFX908-NEXT: v_accvgpr_write_b32 a30, v2
|
||||
; GFX908-NEXT: v_accvgpr_write_b32 a31, v2
|
||||
; GFX908-NEXT: .LBB8_1: ; %for.cond.preheader
|
||||
; GFX908-NEXT: ; =>This Inner Loop Header: Depth=1
|
||||
|
||||
@ -2619,13 +2619,13 @@ define amdgpu_kernel void @s_mul_i128(ptr addrspace(1) %out, [8 x i32], i128 %a,
|
||||
; SI-NEXT: v_add_i32_e32 v0, vcc, s4, v0
|
||||
; SI-NEXT: v_add_i32_e32 v0, vcc, s5, v0
|
||||
; SI-NEXT: s_mul_i32 s5, s14, s9
|
||||
; SI-NEXT: s_mul_i32 s4, s12, s10
|
||||
; SI-NEXT: v_add_i32_e32 v1, vcc, s5, v1
|
||||
; SI-NEXT: s_mul_i32 s5, s15, s8
|
||||
; SI-NEXT: v_add_i32_e32 v1, vcc, s5, v1
|
||||
; SI-NEXT: s_mul_i32 s5, s14, s8
|
||||
; SI-NEXT: v_mov_b32_e32 v2, s4
|
||||
; SI-NEXT: v_add_i32_e32 v2, vcc, s5, v2
|
||||
; SI-NEXT: s_mul_i32 s4, s12, s10
|
||||
; SI-NEXT: v_mov_b32_e32 v2, s5
|
||||
; SI-NEXT: v_add_i32_e32 v2, vcc, s4, v2
|
||||
; SI-NEXT: v_addc_u32_e32 v0, vcc, v1, v0, vcc
|
||||
; SI-NEXT: v_mov_b32_e32 v1, s12
|
||||
; SI-NEXT: v_mul_hi_u32 v5, s8, v1
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user