diff --git a/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp b/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp index 64dfb1e39485..206e410047db 100644 --- a/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp @@ -3902,7 +3902,7 @@ void AArch64FrameLowering::determineCalleeSaves(MachineFunction &MF, const TargetRegisterClass &RC = AArch64::GPR64RegClass; unsigned Size = TRI->getSpillSize(RC); Align Alignment = TRI->getSpillAlign(RC); - int FI = MFI.CreateStackObject(Size, Alignment, false); + int FI = MFI.CreateSpillStackObject(Size, Alignment); RS->addScavengingFrameIndex(FI); LLVM_DEBUG(dbgs() << "No available CS registers, allocated fi#" << FI << " as the emergency spill slot.\n"); diff --git a/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp b/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp index dcd4f0f65e8e..2e2523312840 100644 --- a/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp +++ b/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp @@ -1438,7 +1438,7 @@ void SIFrameLowering::processFunctionBeforeFrameFinalized( // second VGPR emergency frame index. if (HaveSGPRToVMemSpill && allocateScavengingFrameIndexesNearIncomingSP(MF)) { - RS->addScavengingFrameIndex(MFI.CreateStackObject(4, Align(4), false)); + RS->addScavengingFrameIndex(MFI.CreateSpillStackObject(4, Align(4))); } } } diff --git a/llvm/lib/Target/ARC/ARCFrameLowering.cpp b/llvm/lib/Target/ARC/ARCFrameLowering.cpp index 472f1c13f362..95054eac8c4f 100644 --- a/llvm/lib/Target/ARC/ARCFrameLowering.cpp +++ b/llvm/lib/Target/ARC/ARCFrameLowering.cpp @@ -438,8 +438,8 @@ void ARCFrameLowering::processFunctionBeforeFrameFinalized( LLVM_DEBUG(dbgs() << "Current stack size: " << MFI.getStackSize() << "\n"); const TargetRegisterClass *RC = &ARC::GPR32RegClass; if (MFI.hasStackObjects()) { - int RegScavFI = MFI.CreateStackObject(RegInfo->getSpillSize(*RC), - RegInfo->getSpillAlign(*RC), false); + int RegScavFI = MFI.CreateSpillStackObject(RegInfo->getSpillSize(*RC), + RegInfo->getSpillAlign(*RC)); RS->addScavengingFrameIndex(RegScavFI); LLVM_DEBUG(dbgs() << "Created scavenging index RegScavFI=" << RegScavFI << "\n"); diff --git a/llvm/lib/Target/ARM/ARMFrameLowering.cpp b/llvm/lib/Target/ARM/ARMFrameLowering.cpp index f495aa701e87..8b94bfac9b0c 100644 --- a/llvm/lib/Target/ARM/ARMFrameLowering.cpp +++ b/llvm/lib/Target/ARM/ARMFrameLowering.cpp @@ -2925,7 +2925,7 @@ void ARMFrameLowering::determineCalleeSaves(MachineFunction &MF, unsigned Size = TRI->getSpillSize(RC); Align Alignment = TRI->getSpillAlign(RC); RS->addScavengingFrameIndex( - MFI.CreateStackObject(Size, Alignment, false)); + MFI.CreateSpillStackObject(Size, Alignment)); --RegsNeeded; } } diff --git a/llvm/lib/Target/CSKY/CSKYFrameLowering.cpp b/llvm/lib/Target/CSKY/CSKYFrameLowering.cpp index c023b5a0de5a..f29caafe3952 100644 --- a/llvm/lib/Target/CSKY/CSKYFrameLowering.cpp +++ b/llvm/lib/Target/CSKY/CSKYFrameLowering.cpp @@ -441,7 +441,7 @@ void CSKYFrameLowering::determineCalleeSaves(MachineFunction &MF, unsigned size = TRI->getSpillSize(*RC); Align align = TRI->getSpillAlign(*RC); - RS->addScavengingFrameIndex(MFI.CreateStackObject(size, align, false)); + RS->addScavengingFrameIndex(MFI.CreateSpillStackObject(size, align)); } unsigned FnSize = EstimateFunctionSizeInBytes(MF, *TII); diff --git a/llvm/lib/Target/LoongArch/LoongArchFrameLowering.cpp b/llvm/lib/Target/LoongArch/LoongArchFrameLowering.cpp index 1a787c63c624..4b7b5483f5b8 100644 --- a/llvm/lib/Target/LoongArch/LoongArchFrameLowering.cpp +++ b/llvm/lib/Target/LoongArch/LoongArchFrameLowering.cpp @@ -167,8 +167,8 @@ void LoongArchFrameLowering::processFunctionBeforeFrameFinalized( // Create emergency spill slots. for (unsigned i = 0; i < ScavSlotsNum; ++i) { - int FI = MFI.CreateStackObject(RI->getSpillSize(RC), RI->getSpillAlign(RC), - false); + int FI = + MFI.CreateSpillStackObject(RI->getSpillSize(RC), RI->getSpillAlign(RC)); RS->addScavengingFrameIndex(FI); if (IsLargeFunction && LAFI->getBranchRelaxationSpillFrameIndex() == -1) LAFI->setBranchRelaxationSpillFrameIndex(FI); diff --git a/llvm/lib/Target/Mips/MipsSEFrameLowering.cpp b/llvm/lib/Target/Mips/MipsSEFrameLowering.cpp index 165e38915811..04f3a974f540 100644 --- a/llvm/lib/Target/Mips/MipsSEFrameLowering.cpp +++ b/llvm/lib/Target/Mips/MipsSEFrameLowering.cpp @@ -892,8 +892,8 @@ void MipsSEFrameLowering::determineCalleeSaves(MachineFunction &MF, // it should be 32-bit. const TargetRegisterClass &RC = STI.isGP64bit() ? Mips::GPR64RegClass : Mips::GPR32RegClass; - int FI = MF.getFrameInfo().CreateStackObject(TRI->getSpillSize(RC), - TRI->getSpillAlign(RC), false); + int FI = MF.getFrameInfo().CreateSpillStackObject(TRI->getSpillSize(RC), + TRI->getSpillAlign(RC)); RS->addScavengingFrameIndex(FI); } @@ -908,8 +908,8 @@ void MipsSEFrameLowering::determineCalleeSaves(MachineFunction &MF, const TargetRegisterClass &RC = ABI.ArePtrs64bit() ? Mips::GPR64RegClass : Mips::GPR32RegClass; - int FI = MF.getFrameInfo().CreateStackObject(TRI->getSpillSize(RC), - TRI->getSpillAlign(RC), false); + int FI = MF.getFrameInfo().CreateSpillStackObject(TRI->getSpillSize(RC), + TRI->getSpillAlign(RC)); RS->addScavengingFrameIndex(FI); } diff --git a/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp b/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp index b118976b4731..39ebd7f8d0df 100644 --- a/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp @@ -2307,7 +2307,7 @@ PPCFrameLowering::addScavengingSpillSlot(MachineFunction &MF, const TargetRegisterInfo &TRI = *Subtarget.getRegisterInfo(); unsigned Size = TRI.getSpillSize(RC); Align Alignment = TRI.getSpillAlign(RC); - RS->addScavengingFrameIndex(MFI.CreateStackObject(Size, Alignment, false)); + RS->addScavengingFrameIndex(MFI.CreateSpillStackObject(Size, Alignment)); // Might we have over-aligned allocas? bool HasAlVars = @@ -2315,8 +2315,7 @@ PPCFrameLowering::addScavengingSpillSlot(MachineFunction &MF, // These kinds of spills might need two registers. if (spillsCR(MF) || HasAlVars) - RS->addScavengingFrameIndex( - MFI.CreateStackObject(Size, Alignment, false)); + RS->addScavengingFrameIndex(MFI.CreateSpillStackObject(Size, Alignment)); } } diff --git a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp index ed3ec3102806..911cea27a48a 100644 --- a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp @@ -1595,8 +1595,8 @@ void RISCVFrameLowering::processFunctionBeforeFrameFinalized( ScavSlotsNum = std::max(ScavSlotsNum, getScavSlotsNumForRVV(MF)); for (unsigned I = 0; I < ScavSlotsNum; I++) { - int FI = MFI.CreateStackObject(RegInfo->getSpillSize(*RC), - RegInfo->getSpillAlign(*RC), false); + int FI = MFI.CreateSpillStackObject(RegInfo->getSpillSize(*RC), + RegInfo->getSpillAlign(*RC)); RS->addScavengingFrameIndex(FI); if (IsLargeFunction && RVFI->getBranchRelaxationScratchFrameIndex() == -1) diff --git a/llvm/lib/Target/SystemZ/SystemZFrameLowering.cpp b/llvm/lib/Target/SystemZ/SystemZFrameLowering.cpp index ec3ebcbd86d7..54a950ee213f 100644 --- a/llvm/lib/Target/SystemZ/SystemZFrameLowering.cpp +++ b/llvm/lib/Target/SystemZ/SystemZFrameLowering.cpp @@ -457,9 +457,9 @@ void SystemZELFFrameLowering::processFunctionBeforeFrameFinalized( // Create 2 for the case where both addresses in an MVC are // out of range. RS->addScavengingFrameIndex( - MFFrame.CreateStackObject(getPointerSize(), Align(8), false)); + MFFrame.CreateSpillStackObject(getPointerSize(), Align(8))); RS->addScavengingFrameIndex( - MFFrame.CreateStackObject(getPointerSize(), Align(8), false)); + MFFrame.CreateSpillStackObject(getPointerSize(), Align(8))); } // If R6 is used as an argument register it is still callee saved. If it in @@ -1491,8 +1491,8 @@ void SystemZXPLINKFrameLowering::processFunctionBeforeFrameFinalized( if (!isUInt<12>(MaxReach)) { // We may need register scavenging slots if some parts of the frame // are outside the reach of an unsigned 12-bit displacement. - RS->addScavengingFrameIndex(MFFrame.CreateStackObject(8, Align(8), false)); - RS->addScavengingFrameIndex(MFFrame.CreateStackObject(8, Align(8), false)); + RS->addScavengingFrameIndex(MFFrame.CreateSpillStackObject(8, Align(8))); + RS->addScavengingFrameIndex(MFFrame.CreateSpillStackObject(8, Align(8))); } } diff --git a/llvm/lib/Target/XCore/XCoreFrameLowering.cpp b/llvm/lib/Target/XCore/XCoreFrameLowering.cpp index 2bf91dc37999..01896bf98cc1 100644 --- a/llvm/lib/Target/XCore/XCoreFrameLowering.cpp +++ b/llvm/lib/Target/XCore/XCoreFrameLowering.cpp @@ -576,7 +576,7 @@ processFunctionBeforeFrameFinalized(MachineFunction &MF, unsigned Size = TRI.getSpillSize(RC); Align Alignment = TRI.getSpillAlign(RC); if (XFI->isLargeFrame(MF) || hasFP(MF)) - RS->addScavengingFrameIndex(MFI.CreateStackObject(Size, Alignment, false)); + RS->addScavengingFrameIndex(MFI.CreateSpillStackObject(Size, Alignment)); if (XFI->isLargeFrame(MF) && !hasFP(MF)) - RS->addScavengingFrameIndex(MFI.CreateStackObject(Size, Alignment, false)); + RS->addScavengingFrameIndex(MFI.CreateSpillStackObject(Size, Alignment)); } diff --git a/llvm/lib/Target/Xtensa/XtensaFrameLowering.cpp b/llvm/lib/Target/Xtensa/XtensaFrameLowering.cpp index 005ba10b8131..f8ed5dd5e757 100644 --- a/llvm/lib/Target/Xtensa/XtensaFrameLowering.cpp +++ b/llvm/lib/Target/Xtensa/XtensaFrameLowering.cpp @@ -276,7 +276,7 @@ void XtensaFrameLowering::processFunctionBeforeFrameFinalized( unsigned Size = TRI->getSpillSize(RC); Align Alignment = TRI->getSpillAlign(RC); for (unsigned I = 0; I < ScavSlotsNum; I++) { - int FI = MFI.CreateStackObject(Size, Alignment, false); + int FI = MFI.CreateSpillStackObject(Size, Alignment); RS->addScavengingFrameIndex(FI); if (IsLargeFunction && diff --git a/llvm/test/CodeGen/PowerPC/alloca-crspill.ll b/llvm/test/CodeGen/PowerPC/alloca-crspill.ll index da6a206ff940..cbcfd9a6a0da 100644 --- a/llvm/test/CodeGen/PowerPC/alloca-crspill.ll +++ b/llvm/test/CodeGen/PowerPC/alloca-crspill.ll @@ -53,7 +53,7 @@ declare signext i32 @do_something(ptr) ; CHECK64-NEXT: stack-id: default, callee-saved-register: '', callee-saved-restored: true, ; CHECK64-NEXT: local-offset: 0, debug-info-variable: '', debug-info-expression: '', ; CHECK64-NEXT: debug-info-location: '' } -; CHECK64-NEXT: - { id: 1, name: '', type: default, offset: -16, size: 8, alignment: 8, +; CHECK64-NEXT: - { id: 1, name: '', type: spill-slot, offset: -16, size: 8, alignment: 8, ; CHECK64-NEXT: stack-id: default, callee-saved-register: '', callee-saved-restored: true, ; CHECK64-NEXT: debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } @@ -72,7 +72,7 @@ declare signext i32 @do_something(ptr) ; CHECK32-NEXT: stack-id: default, callee-saved-register: '', callee-saved-restored: true, ; CHECK32-NEXT: local-offset: 0, debug-info-variable: '', debug-info-expression: '', ; CHECK32-NEXT: debug-info-location: '' } -; CHECK32-NEXT: - { id: 1, name: '', type: default, offset: -8, size: 4, alignment: 4, +; CHECK32-NEXT: - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, ; CHECK32-NEXT: stack-id: default, callee-saved-register: '', callee-saved-restored: true, ; CHECK32-NEXT: debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } diff --git a/llvm/test/CodeGen/RISCV/rvv/addi-rvv-stack-object.mir b/llvm/test/CodeGen/RISCV/rvv/addi-rvv-stack-object.mir index 080a89e41f0d..812a29b9f0f4 100644 --- a/llvm/test/CodeGen/RISCV/rvv/addi-rvv-stack-object.mir +++ b/llvm/test/CodeGen/RISCV/rvv/addi-rvv-stack-object.mir @@ -40,7 +40,7 @@ stack: - { id: 0, name: local0, type: default, offset: 0, size: 16, alignment: 16, stack-id: scalable-vector, callee-saved-register: '', callee-saved-restored: true, debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } -# CHECK: - { id: 2, name: '', type: default, offset: -16, size: 8, alignment: 8, +# CHECK: - { id: 2, name: '', type: spill-slot, offset: -16, size: 8, alignment: 8, # CHECK: stack-id: default, callee-saved-register: '', callee-saved-restored: true, # CHECK: debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } callSites: []