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[AMDGPU][GFX1030][DOC][NFC] Update assembler syntax description

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Summary of changes:
- Update MUBUF lds syntax (see https://reviews.llvm.org/D124485).
- Add v_cvt_pkrtz_f16_f32_dpp, v_cvt_pkrtz_f16_f32_sdwa.
- Update SMEM syntax (see https://reviews.llvm.org/D127314).
- Enable op_sel for v_add_nc_u16, v_sub_nc_u16 (see https://reviews.llvm.org/D123594).
- Minor bug fixing and improvements.
This commit is contained in:
Dmitry Preobrazhensky 2022-06-27 19:55:07 +03:00
parent beec3e8cb1
commit 2044e4c53e
18 changed files with 303 additions and 284 deletions
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432
llvm/docs/AMDGPU/AMDGPUAsmGFX1030.rst
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@ -68,6 +68,7 @@ DPP16
v_cvt_norm_i16_f16_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx1030_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
v_cvt_norm_u16_f16_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx1030_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
v_cvt_off_f32_i4_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx1030_vsrc_6802ce>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
v_cvt_pkrtz_f16_f32_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx1030_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`::ref:`f32<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`::ref:`f32<amdgpu_synid_gfx1030_type_deviation>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
v_cvt_rpi_i32_f32_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx1030_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
v_cvt_u16_f16_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx1030_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
v_cvt_u32_f32_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx1030_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
@ -175,6 +176,7 @@ DPP8
v_cvt_norm_i16_f16_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx1030_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
v_cvt_norm_u16_f16_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx1030_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
v_cvt_off_f32_i4_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx1030_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
v_cvt_pkrtz_f16_f32_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx1030_vsrc_6802ce>`::ref:`f32<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`::ref:`f32<amdgpu_synid_gfx1030_type_deviation>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
v_cvt_rpi_i32_f32_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx1030_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
v_cvt_u16_f16_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx1030_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
v_cvt_u32_f32_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx1030_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
@ -394,38 +396,38 @@ FLAT
**INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **MODIFIERS**
\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
flat_atomic_add :ref:`vdst<amdgpu_synid_gfx1030_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx1030_opt>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
flat_atomic_add_x2 :ref:`vdst<amdgpu_synid_gfx1030_vdst_463513>`::ref:`opt<amdgpu_synid_gfx1030_opt>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_fd235e>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
flat_atomic_and :ref:`vdst<amdgpu_synid_gfx1030_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx1030_opt>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
flat_atomic_and_x2 :ref:`vdst<amdgpu_synid_gfx1030_vdst_463513>`::ref:`opt<amdgpu_synid_gfx1030_opt>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_fd235e>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
flat_atomic_cmpswap :ref:`vdst<amdgpu_synid_gfx1030_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx1030_opt>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_fd235e>`::ref:`b32x2<amdgpu_synid_gfx1030_type_deviation>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
flat_atomic_cmpswap_x2 :ref:`vdst<amdgpu_synid_gfx1030_vdst_463513>`::ref:`opt<amdgpu_synid_gfx1030_opt>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_e016a1>`::ref:`b64x2<amdgpu_synid_gfx1030_type_deviation>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
flat_atomic_dec :ref:`vdst<amdgpu_synid_gfx1030_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx1030_opt>`::ref:`u32<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>`::ref:`u32<amdgpu_synid_gfx1030_type_deviation>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
flat_atomic_dec_x2 :ref:`vdst<amdgpu_synid_gfx1030_vdst_463513>`::ref:`opt<amdgpu_synid_gfx1030_opt>`::ref:`u64<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_fd235e>`::ref:`u64<amdgpu_synid_gfx1030_type_deviation>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
flat_atomic_fcmpswap :ref:`vdst<amdgpu_synid_gfx1030_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx1030_opt>`::ref:`f32<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_fd235e>`::ref:`f32x2<amdgpu_synid_gfx1030_type_deviation>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
flat_atomic_fcmpswap_x2 :ref:`vdst<amdgpu_synid_gfx1030_vdst_463513>`::ref:`opt<amdgpu_synid_gfx1030_opt>`::ref:`f64<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_e016a1>`::ref:`f64x2<amdgpu_synid_gfx1030_type_deviation>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
flat_atomic_fmax :ref:`vdst<amdgpu_synid_gfx1030_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx1030_opt>`::ref:`f32<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>`::ref:`f32<amdgpu_synid_gfx1030_type_deviation>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
flat_atomic_fmax_x2 :ref:`vdst<amdgpu_synid_gfx1030_vdst_463513>`::ref:`opt<amdgpu_synid_gfx1030_opt>`::ref:`f64<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_fd235e>`::ref:`f64<amdgpu_synid_gfx1030_type_deviation>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
flat_atomic_fmin :ref:`vdst<amdgpu_synid_gfx1030_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx1030_opt>`::ref:`f32<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>`::ref:`f32<amdgpu_synid_gfx1030_type_deviation>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
flat_atomic_fmin_x2 :ref:`vdst<amdgpu_synid_gfx1030_vdst_463513>`::ref:`opt<amdgpu_synid_gfx1030_opt>`::ref:`f64<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_fd235e>`::ref:`f64<amdgpu_synid_gfx1030_type_deviation>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
flat_atomic_inc :ref:`vdst<amdgpu_synid_gfx1030_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx1030_opt>`::ref:`u32<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>`::ref:`u32<amdgpu_synid_gfx1030_type_deviation>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
flat_atomic_inc_x2 :ref:`vdst<amdgpu_synid_gfx1030_vdst_463513>`::ref:`opt<amdgpu_synid_gfx1030_opt>`::ref:`u64<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_fd235e>`::ref:`u64<amdgpu_synid_gfx1030_type_deviation>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
flat_atomic_or :ref:`vdst<amdgpu_synid_gfx1030_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx1030_opt>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
flat_atomic_or_x2 :ref:`vdst<amdgpu_synid_gfx1030_vdst_463513>`::ref:`opt<amdgpu_synid_gfx1030_opt>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_fd235e>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
flat_atomic_smax :ref:`vdst<amdgpu_synid_gfx1030_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx1030_opt>`::ref:`i32<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>`::ref:`i32<amdgpu_synid_gfx1030_type_deviation>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
flat_atomic_smax_x2 :ref:`vdst<amdgpu_synid_gfx1030_vdst_463513>`::ref:`opt<amdgpu_synid_gfx1030_opt>`::ref:`i64<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_fd235e>`::ref:`i64<amdgpu_synid_gfx1030_type_deviation>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
flat_atomic_smin :ref:`vdst<amdgpu_synid_gfx1030_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx1030_opt>`::ref:`i32<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>`::ref:`i32<amdgpu_synid_gfx1030_type_deviation>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
flat_atomic_smin_x2 :ref:`vdst<amdgpu_synid_gfx1030_vdst_463513>`::ref:`opt<amdgpu_synid_gfx1030_opt>`::ref:`i64<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_fd235e>`::ref:`i64<amdgpu_synid_gfx1030_type_deviation>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
flat_atomic_sub :ref:`vdst<amdgpu_synid_gfx1030_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx1030_opt>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
flat_atomic_sub_x2 :ref:`vdst<amdgpu_synid_gfx1030_vdst_463513>`::ref:`opt<amdgpu_synid_gfx1030_opt>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_fd235e>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
flat_atomic_swap :ref:`vdst<amdgpu_synid_gfx1030_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx1030_opt>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
flat_atomic_swap_x2 :ref:`vdst<amdgpu_synid_gfx1030_vdst_463513>`::ref:`opt<amdgpu_synid_gfx1030_opt>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_fd235e>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
flat_atomic_umax :ref:`vdst<amdgpu_synid_gfx1030_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx1030_opt>`::ref:`u32<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>`::ref:`u32<amdgpu_synid_gfx1030_type_deviation>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
flat_atomic_umax_x2 :ref:`vdst<amdgpu_synid_gfx1030_vdst_463513>`::ref:`opt<amdgpu_synid_gfx1030_opt>`::ref:`u64<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_fd235e>`::ref:`u64<amdgpu_synid_gfx1030_type_deviation>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
flat_atomic_umin :ref:`vdst<amdgpu_synid_gfx1030_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx1030_opt>`::ref:`u32<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>`::ref:`u32<amdgpu_synid_gfx1030_type_deviation>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
flat_atomic_umin_x2 :ref:`vdst<amdgpu_synid_gfx1030_vdst_463513>`::ref:`opt<amdgpu_synid_gfx1030_opt>`::ref:`u64<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_fd235e>`::ref:`u64<amdgpu_synid_gfx1030_type_deviation>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
flat_atomic_xor :ref:`vdst<amdgpu_synid_gfx1030_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx1030_opt>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
flat_atomic_xor_x2 :ref:`vdst<amdgpu_synid_gfx1030_vdst_463513>`::ref:`opt<amdgpu_synid_gfx1030_opt>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_fd235e>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
flat_atomic_add :ref:`vdst<amdgpu_synid_gfx1030_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx1030_opt_847aed>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
flat_atomic_add_x2 :ref:`vdst<amdgpu_synid_gfx1030_vdst_463513>`::ref:`opt<amdgpu_synid_gfx1030_opt_847aed>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_fd235e>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
flat_atomic_and :ref:`vdst<amdgpu_synid_gfx1030_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx1030_opt_847aed>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
flat_atomic_and_x2 :ref:`vdst<amdgpu_synid_gfx1030_vdst_463513>`::ref:`opt<amdgpu_synid_gfx1030_opt_847aed>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_fd235e>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
flat_atomic_cmpswap :ref:`vdst<amdgpu_synid_gfx1030_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx1030_opt_847aed>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_fd235e>`::ref:`b32x2<amdgpu_synid_gfx1030_type_deviation>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
flat_atomic_cmpswap_x2 :ref:`vdst<amdgpu_synid_gfx1030_vdst_463513>`::ref:`opt<amdgpu_synid_gfx1030_opt_847aed>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_e016a1>`::ref:`b64x2<amdgpu_synid_gfx1030_type_deviation>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
flat_atomic_dec :ref:`vdst<amdgpu_synid_gfx1030_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx1030_opt_847aed>`::ref:`u32<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>`::ref:`u32<amdgpu_synid_gfx1030_type_deviation>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
flat_atomic_dec_x2 :ref:`vdst<amdgpu_synid_gfx1030_vdst_463513>`::ref:`opt<amdgpu_synid_gfx1030_opt_847aed>`::ref:`u64<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_fd235e>`::ref:`u64<amdgpu_synid_gfx1030_type_deviation>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
flat_atomic_fcmpswap :ref:`vdst<amdgpu_synid_gfx1030_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx1030_opt_847aed>`::ref:`f32<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_fd235e>`::ref:`f32x2<amdgpu_synid_gfx1030_type_deviation>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
flat_atomic_fcmpswap_x2 :ref:`vdst<amdgpu_synid_gfx1030_vdst_463513>`::ref:`opt<amdgpu_synid_gfx1030_opt_847aed>`::ref:`f64<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_e016a1>`::ref:`f64x2<amdgpu_synid_gfx1030_type_deviation>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
flat_atomic_fmax :ref:`vdst<amdgpu_synid_gfx1030_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx1030_opt_847aed>`::ref:`f32<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>`::ref:`f32<amdgpu_synid_gfx1030_type_deviation>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
flat_atomic_fmax_x2 :ref:`vdst<amdgpu_synid_gfx1030_vdst_463513>`::ref:`opt<amdgpu_synid_gfx1030_opt_847aed>`::ref:`f64<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_fd235e>`::ref:`f64<amdgpu_synid_gfx1030_type_deviation>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
flat_atomic_fmin :ref:`vdst<amdgpu_synid_gfx1030_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx1030_opt_847aed>`::ref:`f32<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>`::ref:`f32<amdgpu_synid_gfx1030_type_deviation>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
flat_atomic_fmin_x2 :ref:`vdst<amdgpu_synid_gfx1030_vdst_463513>`::ref:`opt<amdgpu_synid_gfx1030_opt_847aed>`::ref:`f64<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_fd235e>`::ref:`f64<amdgpu_synid_gfx1030_type_deviation>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
flat_atomic_inc :ref:`vdst<amdgpu_synid_gfx1030_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx1030_opt_847aed>`::ref:`u32<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>`::ref:`u32<amdgpu_synid_gfx1030_type_deviation>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
flat_atomic_inc_x2 :ref:`vdst<amdgpu_synid_gfx1030_vdst_463513>`::ref:`opt<amdgpu_synid_gfx1030_opt_847aed>`::ref:`u64<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_fd235e>`::ref:`u64<amdgpu_synid_gfx1030_type_deviation>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
flat_atomic_or :ref:`vdst<amdgpu_synid_gfx1030_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx1030_opt_847aed>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
flat_atomic_or_x2 :ref:`vdst<amdgpu_synid_gfx1030_vdst_463513>`::ref:`opt<amdgpu_synid_gfx1030_opt_847aed>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_fd235e>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
flat_atomic_smax :ref:`vdst<amdgpu_synid_gfx1030_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx1030_opt_847aed>`::ref:`i32<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>`::ref:`i32<amdgpu_synid_gfx1030_type_deviation>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
flat_atomic_smax_x2 :ref:`vdst<amdgpu_synid_gfx1030_vdst_463513>`::ref:`opt<amdgpu_synid_gfx1030_opt_847aed>`::ref:`i64<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_fd235e>`::ref:`i64<amdgpu_synid_gfx1030_type_deviation>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
flat_atomic_smin :ref:`vdst<amdgpu_synid_gfx1030_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx1030_opt_847aed>`::ref:`i32<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>`::ref:`i32<amdgpu_synid_gfx1030_type_deviation>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
flat_atomic_smin_x2 :ref:`vdst<amdgpu_synid_gfx1030_vdst_463513>`::ref:`opt<amdgpu_synid_gfx1030_opt_847aed>`::ref:`i64<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_fd235e>`::ref:`i64<amdgpu_synid_gfx1030_type_deviation>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
flat_atomic_sub :ref:`vdst<amdgpu_synid_gfx1030_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx1030_opt_847aed>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
flat_atomic_sub_x2 :ref:`vdst<amdgpu_synid_gfx1030_vdst_463513>`::ref:`opt<amdgpu_synid_gfx1030_opt_847aed>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_fd235e>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
flat_atomic_swap :ref:`vdst<amdgpu_synid_gfx1030_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx1030_opt_847aed>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
flat_atomic_swap_x2 :ref:`vdst<amdgpu_synid_gfx1030_vdst_463513>`::ref:`opt<amdgpu_synid_gfx1030_opt_847aed>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_fd235e>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
flat_atomic_umax :ref:`vdst<amdgpu_synid_gfx1030_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx1030_opt_847aed>`::ref:`u32<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>`::ref:`u32<amdgpu_synid_gfx1030_type_deviation>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
flat_atomic_umax_x2 :ref:`vdst<amdgpu_synid_gfx1030_vdst_463513>`::ref:`opt<amdgpu_synid_gfx1030_opt_847aed>`::ref:`u64<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_fd235e>`::ref:`u64<amdgpu_synid_gfx1030_type_deviation>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
flat_atomic_umin :ref:`vdst<amdgpu_synid_gfx1030_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx1030_opt_847aed>`::ref:`u32<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>`::ref:`u32<amdgpu_synid_gfx1030_type_deviation>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
flat_atomic_umin_x2 :ref:`vdst<amdgpu_synid_gfx1030_vdst_463513>`::ref:`opt<amdgpu_synid_gfx1030_opt_847aed>`::ref:`u64<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_fd235e>`::ref:`u64<amdgpu_synid_gfx1030_type_deviation>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
flat_atomic_xor :ref:`vdst<amdgpu_synid_gfx1030_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx1030_opt_847aed>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
flat_atomic_xor_x2 :ref:`vdst<amdgpu_synid_gfx1030_vdst_463513>`::ref:`opt<amdgpu_synid_gfx1030_opt_847aed>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_fd235e>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
flat_load_dword :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9f7133>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
flat_load_dwordx2 :ref:`vdst<amdgpu_synid_gfx1030_vdst_bdb32f>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9f7133>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
flat_load_dwordx3 :ref:`vdst<amdgpu_synid_gfx1030_vdst_48e42f>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9f7133>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
@ -448,39 +450,39 @@ FLAT
flat_store_dwordx4 :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_e016a1>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
flat_store_short :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
flat_store_short_d16_hi :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
global_atomic_add :ref:`vdst<amdgpu_synid_gfx1030_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx1030_opt>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>`, :ref:`saddr<amdgpu_synid_gfx1030_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
global_atomic_add_x2 :ref:`vdst<amdgpu_synid_gfx1030_vdst_463513>`::ref:`opt<amdgpu_synid_gfx1030_opt>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_fd235e>`, :ref:`saddr<amdgpu_synid_gfx1030_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
global_atomic_and :ref:`vdst<amdgpu_synid_gfx1030_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx1030_opt>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>`, :ref:`saddr<amdgpu_synid_gfx1030_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
global_atomic_and_x2 :ref:`vdst<amdgpu_synid_gfx1030_vdst_463513>`::ref:`opt<amdgpu_synid_gfx1030_opt>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_fd235e>`, :ref:`saddr<amdgpu_synid_gfx1030_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
global_atomic_cmpswap :ref:`vdst<amdgpu_synid_gfx1030_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx1030_opt>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_fd235e>`::ref:`b32x2<amdgpu_synid_gfx1030_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx1030_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
global_atomic_cmpswap_x2 :ref:`vdst<amdgpu_synid_gfx1030_vdst_463513>`::ref:`opt<amdgpu_synid_gfx1030_opt>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_e016a1>`::ref:`b64x2<amdgpu_synid_gfx1030_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx1030_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
global_atomic_csub :ref:`vdst<amdgpu_synid_gfx1030_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx1030_opt>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>`, :ref:`saddr<amdgpu_synid_gfx1030_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
global_atomic_dec :ref:`vdst<amdgpu_synid_gfx1030_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx1030_opt>`::ref:`u32<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>`::ref:`u32<amdgpu_synid_gfx1030_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx1030_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
global_atomic_dec_x2 :ref:`vdst<amdgpu_synid_gfx1030_vdst_463513>`::ref:`opt<amdgpu_synid_gfx1030_opt>`::ref:`u64<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_fd235e>`::ref:`u64<amdgpu_synid_gfx1030_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx1030_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
global_atomic_fcmpswap :ref:`vdst<amdgpu_synid_gfx1030_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx1030_opt>`::ref:`f32<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_fd235e>`::ref:`f32x2<amdgpu_synid_gfx1030_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx1030_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
global_atomic_fcmpswap_x2 :ref:`vdst<amdgpu_synid_gfx1030_vdst_463513>`::ref:`opt<amdgpu_synid_gfx1030_opt>`::ref:`f64<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_e016a1>`::ref:`f64x2<amdgpu_synid_gfx1030_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx1030_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
global_atomic_fmax :ref:`vdst<amdgpu_synid_gfx1030_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx1030_opt>`::ref:`f32<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>`::ref:`f32<amdgpu_synid_gfx1030_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx1030_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
global_atomic_fmax_x2 :ref:`vdst<amdgpu_synid_gfx1030_vdst_463513>`::ref:`opt<amdgpu_synid_gfx1030_opt>`::ref:`f64<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_fd235e>`::ref:`f64<amdgpu_synid_gfx1030_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx1030_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
global_atomic_fmin :ref:`vdst<amdgpu_synid_gfx1030_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx1030_opt>`::ref:`f32<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>`::ref:`f32<amdgpu_synid_gfx1030_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx1030_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
global_atomic_fmin_x2 :ref:`vdst<amdgpu_synid_gfx1030_vdst_463513>`::ref:`opt<amdgpu_synid_gfx1030_opt>`::ref:`f64<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_fd235e>`::ref:`f64<amdgpu_synid_gfx1030_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx1030_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
global_atomic_inc :ref:`vdst<amdgpu_synid_gfx1030_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx1030_opt>`::ref:`u32<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>`::ref:`u32<amdgpu_synid_gfx1030_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx1030_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
global_atomic_inc_x2 :ref:`vdst<amdgpu_synid_gfx1030_vdst_463513>`::ref:`opt<amdgpu_synid_gfx1030_opt>`::ref:`u64<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_fd235e>`::ref:`u64<amdgpu_synid_gfx1030_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx1030_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
global_atomic_or :ref:`vdst<amdgpu_synid_gfx1030_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx1030_opt>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>`, :ref:`saddr<amdgpu_synid_gfx1030_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
global_atomic_or_x2 :ref:`vdst<amdgpu_synid_gfx1030_vdst_463513>`::ref:`opt<amdgpu_synid_gfx1030_opt>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_fd235e>`, :ref:`saddr<amdgpu_synid_gfx1030_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
global_atomic_smax :ref:`vdst<amdgpu_synid_gfx1030_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx1030_opt>`::ref:`i32<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>`::ref:`i32<amdgpu_synid_gfx1030_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx1030_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
global_atomic_smax_x2 :ref:`vdst<amdgpu_synid_gfx1030_vdst_463513>`::ref:`opt<amdgpu_synid_gfx1030_opt>`::ref:`i64<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_fd235e>`::ref:`i64<amdgpu_synid_gfx1030_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx1030_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
global_atomic_smin :ref:`vdst<amdgpu_synid_gfx1030_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx1030_opt>`::ref:`i32<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>`::ref:`i32<amdgpu_synid_gfx1030_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx1030_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
global_atomic_smin_x2 :ref:`vdst<amdgpu_synid_gfx1030_vdst_463513>`::ref:`opt<amdgpu_synid_gfx1030_opt>`::ref:`i64<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_fd235e>`::ref:`i64<amdgpu_synid_gfx1030_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx1030_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
global_atomic_sub :ref:`vdst<amdgpu_synid_gfx1030_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx1030_opt>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>`, :ref:`saddr<amdgpu_synid_gfx1030_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
global_atomic_sub_x2 :ref:`vdst<amdgpu_synid_gfx1030_vdst_463513>`::ref:`opt<amdgpu_synid_gfx1030_opt>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_fd235e>`, :ref:`saddr<amdgpu_synid_gfx1030_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
global_atomic_swap :ref:`vdst<amdgpu_synid_gfx1030_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx1030_opt>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>`, :ref:`saddr<amdgpu_synid_gfx1030_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
global_atomic_swap_x2 :ref:`vdst<amdgpu_synid_gfx1030_vdst_463513>`::ref:`opt<amdgpu_synid_gfx1030_opt>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_fd235e>`, :ref:`saddr<amdgpu_synid_gfx1030_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
global_atomic_umax :ref:`vdst<amdgpu_synid_gfx1030_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx1030_opt>`::ref:`u32<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>`::ref:`u32<amdgpu_synid_gfx1030_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx1030_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
global_atomic_umax_x2 :ref:`vdst<amdgpu_synid_gfx1030_vdst_463513>`::ref:`opt<amdgpu_synid_gfx1030_opt>`::ref:`u64<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_fd235e>`::ref:`u64<amdgpu_synid_gfx1030_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx1030_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
global_atomic_umin :ref:`vdst<amdgpu_synid_gfx1030_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx1030_opt>`::ref:`u32<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>`::ref:`u32<amdgpu_synid_gfx1030_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx1030_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
global_atomic_umin_x2 :ref:`vdst<amdgpu_synid_gfx1030_vdst_463513>`::ref:`opt<amdgpu_synid_gfx1030_opt>`::ref:`u64<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_fd235e>`::ref:`u64<amdgpu_synid_gfx1030_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx1030_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
global_atomic_xor :ref:`vdst<amdgpu_synid_gfx1030_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx1030_opt>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>`, :ref:`saddr<amdgpu_synid_gfx1030_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
global_atomic_xor_x2 :ref:`vdst<amdgpu_synid_gfx1030_vdst_463513>`::ref:`opt<amdgpu_synid_gfx1030_opt>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_fd235e>`, :ref:`saddr<amdgpu_synid_gfx1030_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
global_atomic_add :ref:`vdst<amdgpu_synid_gfx1030_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx1030_opt_847aed>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>`, :ref:`saddr<amdgpu_synid_gfx1030_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
global_atomic_add_x2 :ref:`vdst<amdgpu_synid_gfx1030_vdst_463513>`::ref:`opt<amdgpu_synid_gfx1030_opt_847aed>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_fd235e>`, :ref:`saddr<amdgpu_synid_gfx1030_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
global_atomic_and :ref:`vdst<amdgpu_synid_gfx1030_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx1030_opt_847aed>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>`, :ref:`saddr<amdgpu_synid_gfx1030_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
global_atomic_and_x2 :ref:`vdst<amdgpu_synid_gfx1030_vdst_463513>`::ref:`opt<amdgpu_synid_gfx1030_opt_847aed>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_fd235e>`, :ref:`saddr<amdgpu_synid_gfx1030_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
global_atomic_cmpswap :ref:`vdst<amdgpu_synid_gfx1030_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx1030_opt_847aed>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_fd235e>`::ref:`b32x2<amdgpu_synid_gfx1030_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx1030_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
global_atomic_cmpswap_x2 :ref:`vdst<amdgpu_synid_gfx1030_vdst_463513>`::ref:`opt<amdgpu_synid_gfx1030_opt_847aed>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_e016a1>`::ref:`b64x2<amdgpu_synid_gfx1030_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx1030_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
global_atomic_csub :ref:`vdst<amdgpu_synid_gfx1030_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx1030_opt_847aed>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>`, :ref:`saddr<amdgpu_synid_gfx1030_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
global_atomic_dec :ref:`vdst<amdgpu_synid_gfx1030_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx1030_opt_847aed>`::ref:`u32<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>`::ref:`u32<amdgpu_synid_gfx1030_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx1030_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
global_atomic_dec_x2 :ref:`vdst<amdgpu_synid_gfx1030_vdst_463513>`::ref:`opt<amdgpu_synid_gfx1030_opt_847aed>`::ref:`u64<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_fd235e>`::ref:`u64<amdgpu_synid_gfx1030_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx1030_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
global_atomic_fcmpswap :ref:`vdst<amdgpu_synid_gfx1030_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx1030_opt_847aed>`::ref:`f32<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_fd235e>`::ref:`f32x2<amdgpu_synid_gfx1030_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx1030_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
global_atomic_fcmpswap_x2 :ref:`vdst<amdgpu_synid_gfx1030_vdst_463513>`::ref:`opt<amdgpu_synid_gfx1030_opt_847aed>`::ref:`f64<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_e016a1>`::ref:`f64x2<amdgpu_synid_gfx1030_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx1030_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
global_atomic_fmax :ref:`vdst<amdgpu_synid_gfx1030_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx1030_opt_847aed>`::ref:`f32<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>`::ref:`f32<amdgpu_synid_gfx1030_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx1030_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
global_atomic_fmax_x2 :ref:`vdst<amdgpu_synid_gfx1030_vdst_463513>`::ref:`opt<amdgpu_synid_gfx1030_opt_847aed>`::ref:`f64<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_fd235e>`::ref:`f64<amdgpu_synid_gfx1030_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx1030_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
global_atomic_fmin :ref:`vdst<amdgpu_synid_gfx1030_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx1030_opt_847aed>`::ref:`f32<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>`::ref:`f32<amdgpu_synid_gfx1030_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx1030_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
global_atomic_fmin_x2 :ref:`vdst<amdgpu_synid_gfx1030_vdst_463513>`::ref:`opt<amdgpu_synid_gfx1030_opt_847aed>`::ref:`f64<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_fd235e>`::ref:`f64<amdgpu_synid_gfx1030_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx1030_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
global_atomic_inc :ref:`vdst<amdgpu_synid_gfx1030_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx1030_opt_847aed>`::ref:`u32<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>`::ref:`u32<amdgpu_synid_gfx1030_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx1030_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
global_atomic_inc_x2 :ref:`vdst<amdgpu_synid_gfx1030_vdst_463513>`::ref:`opt<amdgpu_synid_gfx1030_opt_847aed>`::ref:`u64<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_fd235e>`::ref:`u64<amdgpu_synid_gfx1030_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx1030_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
global_atomic_or :ref:`vdst<amdgpu_synid_gfx1030_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx1030_opt_847aed>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>`, :ref:`saddr<amdgpu_synid_gfx1030_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
global_atomic_or_x2 :ref:`vdst<amdgpu_synid_gfx1030_vdst_463513>`::ref:`opt<amdgpu_synid_gfx1030_opt_847aed>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_fd235e>`, :ref:`saddr<amdgpu_synid_gfx1030_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
global_atomic_smax :ref:`vdst<amdgpu_synid_gfx1030_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx1030_opt_847aed>`::ref:`i32<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>`::ref:`i32<amdgpu_synid_gfx1030_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx1030_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
global_atomic_smax_x2 :ref:`vdst<amdgpu_synid_gfx1030_vdst_463513>`::ref:`opt<amdgpu_synid_gfx1030_opt_847aed>`::ref:`i64<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_fd235e>`::ref:`i64<amdgpu_synid_gfx1030_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx1030_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
global_atomic_smin :ref:`vdst<amdgpu_synid_gfx1030_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx1030_opt_847aed>`::ref:`i32<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>`::ref:`i32<amdgpu_synid_gfx1030_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx1030_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
global_atomic_smin_x2 :ref:`vdst<amdgpu_synid_gfx1030_vdst_463513>`::ref:`opt<amdgpu_synid_gfx1030_opt_847aed>`::ref:`i64<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_fd235e>`::ref:`i64<amdgpu_synid_gfx1030_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx1030_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
global_atomic_sub :ref:`vdst<amdgpu_synid_gfx1030_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx1030_opt_847aed>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>`, :ref:`saddr<amdgpu_synid_gfx1030_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
global_atomic_sub_x2 :ref:`vdst<amdgpu_synid_gfx1030_vdst_463513>`::ref:`opt<amdgpu_synid_gfx1030_opt_847aed>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_fd235e>`, :ref:`saddr<amdgpu_synid_gfx1030_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
global_atomic_swap :ref:`vdst<amdgpu_synid_gfx1030_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx1030_opt_847aed>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>`, :ref:`saddr<amdgpu_synid_gfx1030_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
global_atomic_swap_x2 :ref:`vdst<amdgpu_synid_gfx1030_vdst_463513>`::ref:`opt<amdgpu_synid_gfx1030_opt_847aed>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_fd235e>`, :ref:`saddr<amdgpu_synid_gfx1030_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
global_atomic_umax :ref:`vdst<amdgpu_synid_gfx1030_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx1030_opt_847aed>`::ref:`u32<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>`::ref:`u32<amdgpu_synid_gfx1030_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx1030_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
global_atomic_umax_x2 :ref:`vdst<amdgpu_synid_gfx1030_vdst_463513>`::ref:`opt<amdgpu_synid_gfx1030_opt_847aed>`::ref:`u64<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_fd235e>`::ref:`u64<amdgpu_synid_gfx1030_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx1030_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
global_atomic_umin :ref:`vdst<amdgpu_synid_gfx1030_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx1030_opt_847aed>`::ref:`u32<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>`::ref:`u32<amdgpu_synid_gfx1030_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx1030_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
global_atomic_umin_x2 :ref:`vdst<amdgpu_synid_gfx1030_vdst_463513>`::ref:`opt<amdgpu_synid_gfx1030_opt_847aed>`::ref:`u64<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_fd235e>`::ref:`u64<amdgpu_synid_gfx1030_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx1030_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
global_atomic_xor :ref:`vdst<amdgpu_synid_gfx1030_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx1030_opt_847aed>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>`, :ref:`saddr<amdgpu_synid_gfx1030_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
global_atomic_xor_x2 :ref:`vdst<amdgpu_synid_gfx1030_vdst_463513>`::ref:`opt<amdgpu_synid_gfx1030_opt_847aed>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_fd235e>`, :ref:`saddr<amdgpu_synid_gfx1030_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
global_load_dword :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9aeece>`, :ref:`saddr<amdgpu_synid_gfx1030_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
global_load_dword_addtid :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`saddr<amdgpu_synid_gfx1030_saddr_9cd3cf>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
global_load_dwordx2 :ref:`vdst<amdgpu_synid_gfx1030_vdst_bdb32f>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9aeece>`, :ref:`saddr<amdgpu_synid_gfx1030_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
@ -535,48 +537,48 @@ MIMG
**INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **MODIFIERS**
\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
image_atomic_add :ref:`vdata<amdgpu_synid_gfx1030_vdata_325b78>`::ref:`dst<amdgpu_synid_gfx1030_dst>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>`
image_atomic_and :ref:`vdata<amdgpu_synid_gfx1030_vdata_325b78>`::ref:`dst<amdgpu_synid_gfx1030_dst>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>`
image_atomic_cmpswap :ref:`vdata<amdgpu_synid_gfx1030_vdata_4d8ecf>`::ref:`dst<amdgpu_synid_gfx1030_dst>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>`
image_atomic_dec :ref:`vdata<amdgpu_synid_gfx1030_vdata_325b78>`::ref:`dst<amdgpu_synid_gfx1030_dst>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>`
image_atomic_fcmpswap :ref:`vdata<amdgpu_synid_gfx1030_vdata_4d8ecf>`::ref:`dst<amdgpu_synid_gfx1030_dst>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>`
image_atomic_fmax :ref:`vdata<amdgpu_synid_gfx1030_vdata_325b78>`::ref:`dst<amdgpu_synid_gfx1030_dst>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>`
image_atomic_fmin :ref:`vdata<amdgpu_synid_gfx1030_vdata_325b78>`::ref:`dst<amdgpu_synid_gfx1030_dst>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>`
image_atomic_inc :ref:`vdata<amdgpu_synid_gfx1030_vdata_325b78>`::ref:`dst<amdgpu_synid_gfx1030_dst>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>`
image_atomic_or :ref:`vdata<amdgpu_synid_gfx1030_vdata_325b78>`::ref:`dst<amdgpu_synid_gfx1030_dst>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>`
image_atomic_smax :ref:`vdata<amdgpu_synid_gfx1030_vdata_325b78>`::ref:`dst<amdgpu_synid_gfx1030_dst>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>`
image_atomic_smin :ref:`vdata<amdgpu_synid_gfx1030_vdata_325b78>`::ref:`dst<amdgpu_synid_gfx1030_dst>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>`
image_atomic_sub :ref:`vdata<amdgpu_synid_gfx1030_vdata_325b78>`::ref:`dst<amdgpu_synid_gfx1030_dst>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>`
image_atomic_swap :ref:`vdata<amdgpu_synid_gfx1030_vdata_325b78>`::ref:`dst<amdgpu_synid_gfx1030_dst>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>`
image_atomic_umax :ref:`vdata<amdgpu_synid_gfx1030_vdata_325b78>`::ref:`dst<amdgpu_synid_gfx1030_dst>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>`
image_atomic_umin :ref:`vdata<amdgpu_synid_gfx1030_vdata_325b78>`::ref:`dst<amdgpu_synid_gfx1030_dst>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>`
image_atomic_xor :ref:`vdata<amdgpu_synid_gfx1030_vdata_325b78>`::ref:`dst<amdgpu_synid_gfx1030_dst>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>`
image_atomic_add :ref:`vdata<amdgpu_synid_gfx1030_vdata_35851e>`::ref:`dst<amdgpu_synid_gfx1030_dst>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>`
image_atomic_and :ref:`vdata<amdgpu_synid_gfx1030_vdata_35851e>`::ref:`dst<amdgpu_synid_gfx1030_dst>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>`
image_atomic_cmpswap :ref:`vdata<amdgpu_synid_gfx1030_vdata_a9ff5a>`::ref:`dst<amdgpu_synid_gfx1030_dst>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>`
image_atomic_dec :ref:`vdata<amdgpu_synid_gfx1030_vdata_35851e>`::ref:`dst<amdgpu_synid_gfx1030_dst>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>`
image_atomic_fcmpswap :ref:`vdata<amdgpu_synid_gfx1030_vdata_a9ff5a>`::ref:`dst<amdgpu_synid_gfx1030_dst>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>`
image_atomic_fmax :ref:`vdata<amdgpu_synid_gfx1030_vdata_35851e>`::ref:`dst<amdgpu_synid_gfx1030_dst>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>`
image_atomic_fmin :ref:`vdata<amdgpu_synid_gfx1030_vdata_35851e>`::ref:`dst<amdgpu_synid_gfx1030_dst>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>`
image_atomic_inc :ref:`vdata<amdgpu_synid_gfx1030_vdata_35851e>`::ref:`dst<amdgpu_synid_gfx1030_dst>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>`
image_atomic_or :ref:`vdata<amdgpu_synid_gfx1030_vdata_35851e>`::ref:`dst<amdgpu_synid_gfx1030_dst>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>`
image_atomic_smax :ref:`vdata<amdgpu_synid_gfx1030_vdata_35851e>`::ref:`dst<amdgpu_synid_gfx1030_dst>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>`
image_atomic_smin :ref:`vdata<amdgpu_synid_gfx1030_vdata_35851e>`::ref:`dst<amdgpu_synid_gfx1030_dst>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>`
image_atomic_sub :ref:`vdata<amdgpu_synid_gfx1030_vdata_35851e>`::ref:`dst<amdgpu_synid_gfx1030_dst>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>`
image_atomic_swap :ref:`vdata<amdgpu_synid_gfx1030_vdata_35851e>`::ref:`dst<amdgpu_synid_gfx1030_dst>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>`
image_atomic_umax :ref:`vdata<amdgpu_synid_gfx1030_vdata_35851e>`::ref:`dst<amdgpu_synid_gfx1030_dst>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>`
image_atomic_umin :ref:`vdata<amdgpu_synid_gfx1030_vdata_35851e>`::ref:`dst<amdgpu_synid_gfx1030_dst>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>`
image_atomic_xor :ref:`vdata<amdgpu_synid_gfx1030_vdata_35851e>`::ref:`dst<amdgpu_synid_gfx1030_dst>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>`
image_bvh64_intersect_ray :ref:`vdst<amdgpu_synid_gfx1030_vdst_f8490d>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_49d53a>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_5dafbc>` :ref:`a16<amdgpu_synid_a16>`
image_bvh_intersect_ray :ref:`vdst<amdgpu_synid_gfx1030_vdst_f8490d>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_49d53a>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_5dafbc>` :ref:`a16<amdgpu_synid_a16>`
image_gather4 :ref:`vdst<amdgpu_synid_gfx1030_vdst_48d3a8>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx1030_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
image_gather4_b :ref:`vdst<amdgpu_synid_gfx1030_vdst_48d3a8>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx1030_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
image_gather4_b_cl :ref:`vdst<amdgpu_synid_gfx1030_vdst_48d3a8>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx1030_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
image_gather4_b_cl_o :ref:`vdst<amdgpu_synid_gfx1030_vdst_48d3a8>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx1030_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
image_gather4_b_o :ref:`vdst<amdgpu_synid_gfx1030_vdst_48d3a8>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx1030_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
image_gather4_c :ref:`vdst<amdgpu_synid_gfx1030_vdst_48d3a8>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx1030_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
image_gather4_c_b :ref:`vdst<amdgpu_synid_gfx1030_vdst_48d3a8>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx1030_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
image_gather4_c_b_cl :ref:`vdst<amdgpu_synid_gfx1030_vdst_48d3a8>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx1030_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
image_gather4_c_b_cl_o :ref:`vdst<amdgpu_synid_gfx1030_vdst_48d3a8>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx1030_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
image_gather4_c_b_o :ref:`vdst<amdgpu_synid_gfx1030_vdst_48d3a8>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx1030_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
image_gather4_c_cl :ref:`vdst<amdgpu_synid_gfx1030_vdst_48d3a8>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx1030_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
image_gather4_c_cl_o :ref:`vdst<amdgpu_synid_gfx1030_vdst_48d3a8>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx1030_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
image_gather4_c_l :ref:`vdst<amdgpu_synid_gfx1030_vdst_48d3a8>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx1030_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
image_gather4_c_l_o :ref:`vdst<amdgpu_synid_gfx1030_vdst_48d3a8>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx1030_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
image_gather4_c_lz :ref:`vdst<amdgpu_synid_gfx1030_vdst_48d3a8>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx1030_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
image_gather4_c_lz_o :ref:`vdst<amdgpu_synid_gfx1030_vdst_48d3a8>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx1030_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
image_gather4_c_o :ref:`vdst<amdgpu_synid_gfx1030_vdst_48d3a8>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx1030_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
image_gather4_cl :ref:`vdst<amdgpu_synid_gfx1030_vdst_48d3a8>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx1030_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
image_gather4_cl_o :ref:`vdst<amdgpu_synid_gfx1030_vdst_48d3a8>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx1030_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
image_gather4_l :ref:`vdst<amdgpu_synid_gfx1030_vdst_48d3a8>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx1030_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
image_gather4_l_o :ref:`vdst<amdgpu_synid_gfx1030_vdst_48d3a8>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx1030_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
image_gather4_lz :ref:`vdst<amdgpu_synid_gfx1030_vdst_48d3a8>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx1030_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
image_gather4_lz_o :ref:`vdst<amdgpu_synid_gfx1030_vdst_48d3a8>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx1030_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
image_gather4_o :ref:`vdst<amdgpu_synid_gfx1030_vdst_48d3a8>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx1030_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
image_gather4 :ref:`vdst<amdgpu_synid_gfx1030_vdst_2ea017>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx1030_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
image_gather4_b :ref:`vdst<amdgpu_synid_gfx1030_vdst_2ea017>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx1030_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
image_gather4_b_cl :ref:`vdst<amdgpu_synid_gfx1030_vdst_2ea017>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx1030_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
image_gather4_b_cl_o :ref:`vdst<amdgpu_synid_gfx1030_vdst_2ea017>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx1030_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
image_gather4_b_o :ref:`vdst<amdgpu_synid_gfx1030_vdst_2ea017>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx1030_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
image_gather4_c :ref:`vdst<amdgpu_synid_gfx1030_vdst_2ea017>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx1030_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
image_gather4_c_b :ref:`vdst<amdgpu_synid_gfx1030_vdst_2ea017>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx1030_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
image_gather4_c_b_cl :ref:`vdst<amdgpu_synid_gfx1030_vdst_2ea017>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx1030_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
image_gather4_c_b_cl_o :ref:`vdst<amdgpu_synid_gfx1030_vdst_2ea017>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx1030_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
image_gather4_c_b_o :ref:`vdst<amdgpu_synid_gfx1030_vdst_2ea017>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx1030_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
image_gather4_c_cl :ref:`vdst<amdgpu_synid_gfx1030_vdst_2ea017>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx1030_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
image_gather4_c_cl_o :ref:`vdst<amdgpu_synid_gfx1030_vdst_2ea017>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx1030_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
image_gather4_c_l :ref:`vdst<amdgpu_synid_gfx1030_vdst_2ea017>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx1030_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
image_gather4_c_l_o :ref:`vdst<amdgpu_synid_gfx1030_vdst_2ea017>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx1030_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
image_gather4_c_lz :ref:`vdst<amdgpu_synid_gfx1030_vdst_2ea017>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx1030_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
image_gather4_c_lz_o :ref:`vdst<amdgpu_synid_gfx1030_vdst_2ea017>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx1030_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
image_gather4_c_o :ref:`vdst<amdgpu_synid_gfx1030_vdst_2ea017>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx1030_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
image_gather4_cl :ref:`vdst<amdgpu_synid_gfx1030_vdst_2ea017>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx1030_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
image_gather4_cl_o :ref:`vdst<amdgpu_synid_gfx1030_vdst_2ea017>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx1030_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
image_gather4_l :ref:`vdst<amdgpu_synid_gfx1030_vdst_2ea017>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx1030_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
image_gather4_l_o :ref:`vdst<amdgpu_synid_gfx1030_vdst_2ea017>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx1030_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
image_gather4_lz :ref:`vdst<amdgpu_synid_gfx1030_vdst_2ea017>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx1030_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
image_gather4_lz_o :ref:`vdst<amdgpu_synid_gfx1030_vdst_2ea017>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx1030_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
image_gather4_o :ref:`vdst<amdgpu_synid_gfx1030_vdst_2ea017>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx1030_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
image_get_lod :ref:`vdst<amdgpu_synid_gfx1030_vdst_3d7dcf>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx1030_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>`
image_get_resinfo :ref:`vdst<amdgpu_synid_gfx1030_vdst_3d7dcf>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>`
image_load :ref:`vdst<amdgpu_synid_gfx1030_vdst_473a69>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
@ -654,14 +656,14 @@ MTBUF
**INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **SRC3** **MODIFIERS**
\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
tbuffer_load_format_d16_x :ref:`vdst<amdgpu_synid_gfx1030_vdst_5d50a1>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`ufmt<amdgpu_synid_ufmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
tbuffer_load_format_d16_xy :ref:`vdst<amdgpu_synid_gfx1030_vdst_5d50a1>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`ufmt<amdgpu_synid_ufmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
tbuffer_load_format_d16_xyz :ref:`vdst<amdgpu_synid_gfx1030_vdst_d7c57e>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`ufmt<amdgpu_synid_ufmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
tbuffer_load_format_d16_xyzw :ref:`vdst<amdgpu_synid_gfx1030_vdst_d7c57e>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`ufmt<amdgpu_synid_ufmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
tbuffer_load_format_x :ref:`vdst<amdgpu_synid_gfx1030_vdst_5d50a1>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`ufmt<amdgpu_synid_ufmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
tbuffer_load_format_xy :ref:`vdst<amdgpu_synid_gfx1030_vdst_d7c57e>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`ufmt<amdgpu_synid_ufmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
tbuffer_load_format_xyz :ref:`vdst<amdgpu_synid_gfx1030_vdst_a49b76>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`ufmt<amdgpu_synid_ufmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
tbuffer_load_format_xyzw :ref:`vdst<amdgpu_synid_gfx1030_vdst_f47754>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`ufmt<amdgpu_synid_ufmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
tbuffer_load_format_d16_x :ref:`vdst<amdgpu_synid_gfx1030_vdst_709347>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`ufmt<amdgpu_synid_ufmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
tbuffer_load_format_d16_xy :ref:`vdst<amdgpu_synid_gfx1030_vdst_709347>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`ufmt<amdgpu_synid_ufmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
tbuffer_load_format_d16_xyz :ref:`vdst<amdgpu_synid_gfx1030_vdst_d71f1c>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`ufmt<amdgpu_synid_ufmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
tbuffer_load_format_d16_xyzw :ref:`vdst<amdgpu_synid_gfx1030_vdst_d71f1c>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`ufmt<amdgpu_synid_ufmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
tbuffer_load_format_x :ref:`vdst<amdgpu_synid_gfx1030_vdst_709347>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`ufmt<amdgpu_synid_ufmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
tbuffer_load_format_xy :ref:`vdst<amdgpu_synid_gfx1030_vdst_d71f1c>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`ufmt<amdgpu_synid_ufmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
tbuffer_load_format_xyz :ref:`vdst<amdgpu_synid_gfx1030_vdst_81a6ed>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`ufmt<amdgpu_synid_ufmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
tbuffer_load_format_xyzw :ref:`vdst<amdgpu_synid_gfx1030_vdst_dd8a32>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`ufmt<amdgpu_synid_ufmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
tbuffer_store_format_d16_x :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`ufmt<amdgpu_synid_ufmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
tbuffer_store_format_d16_xy :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`ufmt<amdgpu_synid_ufmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
tbuffer_store_format_d16_xyz :ref:`vdata<amdgpu_synid_gfx1030_vdata_fd235e>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`ufmt<amdgpu_synid_ufmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
@ -676,81 +678,81 @@ MUBUF
.. parsed-literal::
**INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **SRC3** **MODIFIERS**
\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
buffer_atomic_add :ref:`vdata<amdgpu_synid_gfx1030_vdata_c61803>`::ref:`dst<amdgpu_synid_gfx1030_dst>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_atomic_add_x2 :ref:`vdata<amdgpu_synid_gfx1030_vdata_b2a787>`::ref:`dst<amdgpu_synid_gfx1030_dst>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_atomic_and :ref:`vdata<amdgpu_synid_gfx1030_vdata_c61803>`::ref:`dst<amdgpu_synid_gfx1030_dst>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_atomic_and_x2 :ref:`vdata<amdgpu_synid_gfx1030_vdata_b2a787>`::ref:`dst<amdgpu_synid_gfx1030_dst>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_atomic_cmpswap :ref:`vdata<amdgpu_synid_gfx1030_vdata_b2a787>`::ref:`dst<amdgpu_synid_gfx1030_dst>`::ref:`b32x2<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_atomic_cmpswap_x2 :ref:`vdata<amdgpu_synid_gfx1030_vdata_87fb90>`::ref:`dst<amdgpu_synid_gfx1030_dst>`::ref:`b64x2<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_atomic_csub :ref:`vdata<amdgpu_synid_gfx1030_vdata_c61803>`::ref:`dst<amdgpu_synid_gfx1030_dst>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_atomic_dec :ref:`vdata<amdgpu_synid_gfx1030_vdata_c61803>`::ref:`dst<amdgpu_synid_gfx1030_dst>`::ref:`u32<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_atomic_dec_x2 :ref:`vdata<amdgpu_synid_gfx1030_vdata_b2a787>`::ref:`dst<amdgpu_synid_gfx1030_dst>`::ref:`u64<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_atomic_fcmpswap :ref:`vdata<amdgpu_synid_gfx1030_vdata_b2a787>`::ref:`dst<amdgpu_synid_gfx1030_dst>`::ref:`f32x2<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_atomic_fcmpswap_x2 :ref:`vdata<amdgpu_synid_gfx1030_vdata_87fb90>`::ref:`dst<amdgpu_synid_gfx1030_dst>`::ref:`f64x2<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_atomic_fmax :ref:`vdata<amdgpu_synid_gfx1030_vdata_c61803>`::ref:`dst<amdgpu_synid_gfx1030_dst>`::ref:`f32<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_atomic_fmax_x2 :ref:`vdata<amdgpu_synid_gfx1030_vdata_b2a787>`::ref:`dst<amdgpu_synid_gfx1030_dst>`::ref:`f64<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_atomic_fmin :ref:`vdata<amdgpu_synid_gfx1030_vdata_c61803>`::ref:`dst<amdgpu_synid_gfx1030_dst>`::ref:`f32<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_atomic_fmin_x2 :ref:`vdata<amdgpu_synid_gfx1030_vdata_b2a787>`::ref:`dst<amdgpu_synid_gfx1030_dst>`::ref:`f64<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_atomic_inc :ref:`vdata<amdgpu_synid_gfx1030_vdata_c61803>`::ref:`dst<amdgpu_synid_gfx1030_dst>`::ref:`u32<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_atomic_inc_x2 :ref:`vdata<amdgpu_synid_gfx1030_vdata_b2a787>`::ref:`dst<amdgpu_synid_gfx1030_dst>`::ref:`u64<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_atomic_or :ref:`vdata<amdgpu_synid_gfx1030_vdata_c61803>`::ref:`dst<amdgpu_synid_gfx1030_dst>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_atomic_or_x2 :ref:`vdata<amdgpu_synid_gfx1030_vdata_b2a787>`::ref:`dst<amdgpu_synid_gfx1030_dst>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_atomic_smax :ref:`vdata<amdgpu_synid_gfx1030_vdata_c61803>`::ref:`dst<amdgpu_synid_gfx1030_dst>`::ref:`i32<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_atomic_smax_x2 :ref:`vdata<amdgpu_synid_gfx1030_vdata_b2a787>`::ref:`dst<amdgpu_synid_gfx1030_dst>`::ref:`i64<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_atomic_smin :ref:`vdata<amdgpu_synid_gfx1030_vdata_c61803>`::ref:`dst<amdgpu_synid_gfx1030_dst>`::ref:`i32<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_atomic_smin_x2 :ref:`vdata<amdgpu_synid_gfx1030_vdata_b2a787>`::ref:`dst<amdgpu_synid_gfx1030_dst>`::ref:`i64<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_atomic_sub :ref:`vdata<amdgpu_synid_gfx1030_vdata_c61803>`::ref:`dst<amdgpu_synid_gfx1030_dst>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_atomic_sub_x2 :ref:`vdata<amdgpu_synid_gfx1030_vdata_b2a787>`::ref:`dst<amdgpu_synid_gfx1030_dst>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_atomic_swap :ref:`vdata<amdgpu_synid_gfx1030_vdata_c61803>`::ref:`dst<amdgpu_synid_gfx1030_dst>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_atomic_swap_x2 :ref:`vdata<amdgpu_synid_gfx1030_vdata_b2a787>`::ref:`dst<amdgpu_synid_gfx1030_dst>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_atomic_umax :ref:`vdata<amdgpu_synid_gfx1030_vdata_c61803>`::ref:`dst<amdgpu_synid_gfx1030_dst>`::ref:`u32<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_atomic_umax_x2 :ref:`vdata<amdgpu_synid_gfx1030_vdata_b2a787>`::ref:`dst<amdgpu_synid_gfx1030_dst>`::ref:`u64<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_atomic_umin :ref:`vdata<amdgpu_synid_gfx1030_vdata_c61803>`::ref:`dst<amdgpu_synid_gfx1030_dst>`::ref:`u32<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_atomic_umin_x2 :ref:`vdata<amdgpu_synid_gfx1030_vdata_b2a787>`::ref:`dst<amdgpu_synid_gfx1030_dst>`::ref:`u64<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_atomic_xor :ref:`vdata<amdgpu_synid_gfx1030_vdata_c61803>`::ref:`dst<amdgpu_synid_gfx1030_dst>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_atomic_xor_x2 :ref:`vdata<amdgpu_synid_gfx1030_vdata_b2a787>`::ref:`dst<amdgpu_synid_gfx1030_dst>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
**INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **SRC3** **MODIFIERS**
\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
buffer_atomic_add :ref:`vdata<amdgpu_synid_gfx1030_vdata_0aba12>`::ref:`dst<amdgpu_synid_gfx1030_dst>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_atomic_add_x2 :ref:`vdata<amdgpu_synid_gfx1030_vdata_16d321>`::ref:`dst<amdgpu_synid_gfx1030_dst>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_atomic_and :ref:`vdata<amdgpu_synid_gfx1030_vdata_0aba12>`::ref:`dst<amdgpu_synid_gfx1030_dst>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_atomic_and_x2 :ref:`vdata<amdgpu_synid_gfx1030_vdata_16d321>`::ref:`dst<amdgpu_synid_gfx1030_dst>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_atomic_cmpswap :ref:`vdata<amdgpu_synid_gfx1030_vdata_16d321>`::ref:`dst<amdgpu_synid_gfx1030_dst>`::ref:`b32x2<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_atomic_cmpswap_x2 :ref:`vdata<amdgpu_synid_gfx1030_vdata_890652>`::ref:`dst<amdgpu_synid_gfx1030_dst>`::ref:`b64x2<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_atomic_csub :ref:`vdata<amdgpu_synid_gfx1030_vdata_0aba12>`::ref:`dst<amdgpu_synid_gfx1030_dst>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_atomic_dec :ref:`vdata<amdgpu_synid_gfx1030_vdata_0aba12>`::ref:`dst<amdgpu_synid_gfx1030_dst>`::ref:`u32<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_atomic_dec_x2 :ref:`vdata<amdgpu_synid_gfx1030_vdata_16d321>`::ref:`dst<amdgpu_synid_gfx1030_dst>`::ref:`u64<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_atomic_fcmpswap :ref:`vdata<amdgpu_synid_gfx1030_vdata_16d321>`::ref:`dst<amdgpu_synid_gfx1030_dst>`::ref:`f32x2<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_atomic_fcmpswap_x2 :ref:`vdata<amdgpu_synid_gfx1030_vdata_890652>`::ref:`dst<amdgpu_synid_gfx1030_dst>`::ref:`f64x2<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_atomic_fmax :ref:`vdata<amdgpu_synid_gfx1030_vdata_0aba12>`::ref:`dst<amdgpu_synid_gfx1030_dst>`::ref:`f32<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_atomic_fmax_x2 :ref:`vdata<amdgpu_synid_gfx1030_vdata_16d321>`::ref:`dst<amdgpu_synid_gfx1030_dst>`::ref:`f64<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_atomic_fmin :ref:`vdata<amdgpu_synid_gfx1030_vdata_0aba12>`::ref:`dst<amdgpu_synid_gfx1030_dst>`::ref:`f32<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_atomic_fmin_x2 :ref:`vdata<amdgpu_synid_gfx1030_vdata_16d321>`::ref:`dst<amdgpu_synid_gfx1030_dst>`::ref:`f64<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_atomic_inc :ref:`vdata<amdgpu_synid_gfx1030_vdata_0aba12>`::ref:`dst<amdgpu_synid_gfx1030_dst>`::ref:`u32<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_atomic_inc_x2 :ref:`vdata<amdgpu_synid_gfx1030_vdata_16d321>`::ref:`dst<amdgpu_synid_gfx1030_dst>`::ref:`u64<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_atomic_or :ref:`vdata<amdgpu_synid_gfx1030_vdata_0aba12>`::ref:`dst<amdgpu_synid_gfx1030_dst>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_atomic_or_x2 :ref:`vdata<amdgpu_synid_gfx1030_vdata_16d321>`::ref:`dst<amdgpu_synid_gfx1030_dst>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_atomic_smax :ref:`vdata<amdgpu_synid_gfx1030_vdata_0aba12>`::ref:`dst<amdgpu_synid_gfx1030_dst>`::ref:`i32<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_atomic_smax_x2 :ref:`vdata<amdgpu_synid_gfx1030_vdata_16d321>`::ref:`dst<amdgpu_synid_gfx1030_dst>`::ref:`i64<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_atomic_smin :ref:`vdata<amdgpu_synid_gfx1030_vdata_0aba12>`::ref:`dst<amdgpu_synid_gfx1030_dst>`::ref:`i32<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_atomic_smin_x2 :ref:`vdata<amdgpu_synid_gfx1030_vdata_16d321>`::ref:`dst<amdgpu_synid_gfx1030_dst>`::ref:`i64<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_atomic_sub :ref:`vdata<amdgpu_synid_gfx1030_vdata_0aba12>`::ref:`dst<amdgpu_synid_gfx1030_dst>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_atomic_sub_x2 :ref:`vdata<amdgpu_synid_gfx1030_vdata_16d321>`::ref:`dst<amdgpu_synid_gfx1030_dst>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_atomic_swap :ref:`vdata<amdgpu_synid_gfx1030_vdata_0aba12>`::ref:`dst<amdgpu_synid_gfx1030_dst>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_atomic_swap_x2 :ref:`vdata<amdgpu_synid_gfx1030_vdata_16d321>`::ref:`dst<amdgpu_synid_gfx1030_dst>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_atomic_umax :ref:`vdata<amdgpu_synid_gfx1030_vdata_0aba12>`::ref:`dst<amdgpu_synid_gfx1030_dst>`::ref:`u32<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_atomic_umax_x2 :ref:`vdata<amdgpu_synid_gfx1030_vdata_16d321>`::ref:`dst<amdgpu_synid_gfx1030_dst>`::ref:`u64<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_atomic_umin :ref:`vdata<amdgpu_synid_gfx1030_vdata_0aba12>`::ref:`dst<amdgpu_synid_gfx1030_dst>`::ref:`u32<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_atomic_umin_x2 :ref:`vdata<amdgpu_synid_gfx1030_vdata_16d321>`::ref:`dst<amdgpu_synid_gfx1030_dst>`::ref:`u64<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_atomic_xor :ref:`vdata<amdgpu_synid_gfx1030_vdata_0aba12>`::ref:`dst<amdgpu_synid_gfx1030_dst>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_atomic_xor_x2 :ref:`vdata<amdgpu_synid_gfx1030_vdata_16d321>`::ref:`dst<amdgpu_synid_gfx1030_dst>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_gl0_inv
buffer_gl1_inv
buffer_load_dword :ref:`vdst<amdgpu_synid_gfx1030_vdst_719833>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`lds<amdgpu_synid_lds>`
buffer_load_dwordx2 :ref:`vdst<amdgpu_synid_gfx1030_vdst_d7c57e>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
buffer_load_dwordx3 :ref:`vdst<amdgpu_synid_gfx1030_vdst_a49b76>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
buffer_load_dwordx4 :ref:`vdst<amdgpu_synid_gfx1030_vdst_f47754>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
buffer_load_format_d16_x :ref:`vdst<amdgpu_synid_gfx1030_vdst_5d50a1>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
buffer_load_format_d16_xy :ref:`vdst<amdgpu_synid_gfx1030_vdst_5d50a1>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
buffer_load_format_d16_xyz :ref:`vdst<amdgpu_synid_gfx1030_vdst_d7c57e>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
buffer_load_format_d16_xyzw :ref:`vdst<amdgpu_synid_gfx1030_vdst_d7c57e>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
buffer_load_format_x :ref:`vdst<amdgpu_synid_gfx1030_vdst_719833>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`lds<amdgpu_synid_lds>`
buffer_load_format_xy :ref:`vdst<amdgpu_synid_gfx1030_vdst_d7c57e>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
buffer_load_format_xyz :ref:`vdst<amdgpu_synid_gfx1030_vdst_a49b76>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
buffer_load_format_xyzw :ref:`vdst<amdgpu_synid_gfx1030_vdst_f47754>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
buffer_load_sbyte :ref:`vdst<amdgpu_synid_gfx1030_vdst_719833>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`lds<amdgpu_synid_lds>`
buffer_load_sbyte_d16 :ref:`vdst<amdgpu_synid_gfx1030_vdst_5d50a1>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
buffer_load_sbyte_d16_hi :ref:`vdst<amdgpu_synid_gfx1030_vdst_5d50a1>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
buffer_load_short_d16 :ref:`vdst<amdgpu_synid_gfx1030_vdst_5d50a1>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
buffer_load_short_d16_hi :ref:`vdst<amdgpu_synid_gfx1030_vdst_5d50a1>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
buffer_load_sshort :ref:`vdst<amdgpu_synid_gfx1030_vdst_719833>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`lds<amdgpu_synid_lds>`
buffer_load_ubyte :ref:`vdst<amdgpu_synid_gfx1030_vdst_719833>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`lds<amdgpu_synid_lds>`
buffer_load_ubyte_d16 :ref:`vdst<amdgpu_synid_gfx1030_vdst_5d50a1>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
buffer_load_ubyte_d16_hi :ref:`vdst<amdgpu_synid_gfx1030_vdst_5d50a1>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
buffer_load_ushort :ref:`vdst<amdgpu_synid_gfx1030_vdst_719833>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`lds<amdgpu_synid_lds>`
buffer_store_byte :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_store_byte_d16_hi :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_store_dword :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_store_dwordx2 :ref:`vdata<amdgpu_synid_gfx1030_vdata_fd235e>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_store_dwordx3 :ref:`vdata<amdgpu_synid_gfx1030_vdata_56f215>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_store_dwordx4 :ref:`vdata<amdgpu_synid_gfx1030_vdata_e016a1>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_store_format_d16_x :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_store_format_d16_xy :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_store_format_d16_xyz :ref:`vdata<amdgpu_synid_gfx1030_vdata_fd235e>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_store_format_d16_xyzw :ref:`vdata<amdgpu_synid_gfx1030_vdata_fd235e>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_store_format_x :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_store_format_xy :ref:`vdata<amdgpu_synid_gfx1030_vdata_fd235e>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_store_format_xyz :ref:`vdata<amdgpu_synid_gfx1030_vdata_56f215>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_store_format_xyzw :ref:`vdata<amdgpu_synid_gfx1030_vdata_e016a1>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_store_short :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_store_short_d16_hi :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_load_dword :ref:`vdst<amdgpu_synid_gfx1030_vdst_322561>`::ref:`opt<amdgpu_synid_gfx1030_opt_0d447d>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`lds<amdgpu_synid_lds>`
buffer_load_dwordx2 :ref:`vdst<amdgpu_synid_gfx1030_vdst_d71f1c>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
buffer_load_dwordx3 :ref:`vdst<amdgpu_synid_gfx1030_vdst_81a6ed>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
buffer_load_dwordx4 :ref:`vdst<amdgpu_synid_gfx1030_vdst_dd8a32>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
buffer_load_format_d16_x :ref:`vdst<amdgpu_synid_gfx1030_vdst_709347>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
buffer_load_format_d16_xy :ref:`vdst<amdgpu_synid_gfx1030_vdst_709347>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
buffer_load_format_d16_xyz :ref:`vdst<amdgpu_synid_gfx1030_vdst_d71f1c>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
buffer_load_format_d16_xyzw :ref:`vdst<amdgpu_synid_gfx1030_vdst_d71f1c>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
buffer_load_format_x :ref:`vdst<amdgpu_synid_gfx1030_vdst_322561>`::ref:`opt<amdgpu_synid_gfx1030_opt_0d447d>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`lds<amdgpu_synid_lds>`
buffer_load_format_xy :ref:`vdst<amdgpu_synid_gfx1030_vdst_d71f1c>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
buffer_load_format_xyz :ref:`vdst<amdgpu_synid_gfx1030_vdst_81a6ed>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
buffer_load_format_xyzw :ref:`vdst<amdgpu_synid_gfx1030_vdst_dd8a32>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
buffer_load_sbyte :ref:`vdst<amdgpu_synid_gfx1030_vdst_322561>`::ref:`opt<amdgpu_synid_gfx1030_opt_0d447d>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`lds<amdgpu_synid_lds>`
buffer_load_sbyte_d16 :ref:`vdst<amdgpu_synid_gfx1030_vdst_709347>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
buffer_load_sbyte_d16_hi :ref:`vdst<amdgpu_synid_gfx1030_vdst_709347>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
buffer_load_short_d16 :ref:`vdst<amdgpu_synid_gfx1030_vdst_709347>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
buffer_load_short_d16_hi :ref:`vdst<amdgpu_synid_gfx1030_vdst_709347>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
buffer_load_sshort :ref:`vdst<amdgpu_synid_gfx1030_vdst_322561>`::ref:`opt<amdgpu_synid_gfx1030_opt_0d447d>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`lds<amdgpu_synid_lds>`
buffer_load_ubyte :ref:`vdst<amdgpu_synid_gfx1030_vdst_322561>`::ref:`opt<amdgpu_synid_gfx1030_opt_0d447d>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`lds<amdgpu_synid_lds>`
buffer_load_ubyte_d16 :ref:`vdst<amdgpu_synid_gfx1030_vdst_709347>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
buffer_load_ubyte_d16_hi :ref:`vdst<amdgpu_synid_gfx1030_vdst_709347>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
buffer_load_ushort :ref:`vdst<amdgpu_synid_gfx1030_vdst_322561>`::ref:`opt<amdgpu_synid_gfx1030_opt_0d447d>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`lds<amdgpu_synid_lds>`
buffer_store_byte :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_store_byte_d16_hi :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_store_dword :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_store_dwordx2 :ref:`vdata<amdgpu_synid_gfx1030_vdata_fd235e>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_store_dwordx3 :ref:`vdata<amdgpu_synid_gfx1030_vdata_56f215>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_store_dwordx4 :ref:`vdata<amdgpu_synid_gfx1030_vdata_e016a1>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_store_format_d16_x :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_store_format_d16_xy :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_store_format_d16_xyz :ref:`vdata<amdgpu_synid_gfx1030_vdata_fd235e>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_store_format_d16_xyzw :ref:`vdata<amdgpu_synid_gfx1030_vdata_fd235e>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_store_format_x :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_store_format_xy :ref:`vdata<amdgpu_synid_gfx1030_vdata_fd235e>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_store_format_xyz :ref:`vdata<amdgpu_synid_gfx1030_vdata_56f215>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_store_format_xyzw :ref:`vdata<amdgpu_synid_gfx1030_vdata_e016a1>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_store_short :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_store_short_d16_hi :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
SDWA
----
@ -910,7 +912,8 @@ SDWA
v_cvt_i32_f32_sdwa :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_ae1543>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
v_cvt_norm_i16_f16_sdwa :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_ae1543>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
v_cvt_norm_u16_f16_sdwa :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_ae1543>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
v_cvt_off_f32_i4_sdwa :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_ae1543>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
v_cvt_off_f32_i4_sdwa :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_ae1543>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
v_cvt_pkrtz_f16_f32_sdwa :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_ae1543>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`::ref:`f32<amdgpu_synid_gfx1030_type_deviation>`, :ref:`src1<amdgpu_synid_gfx1030_src_ae1543>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`::ref:`f32<amdgpu_synid_gfx1030_type_deviation>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
v_cvt_rpi_i32_f32_sdwa :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_ae1543>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
v_cvt_u16_f16_sdwa :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_ae1543>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
v_cvt_u32_f32_sdwa :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_ae1543>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
@ -985,19 +988,19 @@ SMEM
.. parsed-literal::
**INSTRUCTION** **DST** **SRC0** **SRC1** **MODIFIERS**
\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
s_buffer_load_dword :ref:`sdst<amdgpu_synid_gfx1030_sdst_54e16e>`, :ref:`sbase<amdgpu_synid_gfx1030_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_59fade>` :ref:`glc<amdgpu_synid_glc>` :ref:`dlc<amdgpu_synid_dlc>`
s_buffer_load_dwordx16 :ref:`sdst<amdgpu_synid_gfx1030_sdst_3bc700>`, :ref:`sbase<amdgpu_synid_gfx1030_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_59fade>` :ref:`glc<amdgpu_synid_glc>` :ref:`dlc<amdgpu_synid_dlc>`
s_buffer_load_dwordx2 :ref:`sdst<amdgpu_synid_gfx1030_sdst_386c33>`, :ref:`sbase<amdgpu_synid_gfx1030_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_59fade>` :ref:`glc<amdgpu_synid_glc>` :ref:`dlc<amdgpu_synid_dlc>`
s_buffer_load_dwordx4 :ref:`sdst<amdgpu_synid_gfx1030_sdst_0804b1>`, :ref:`sbase<amdgpu_synid_gfx1030_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_59fade>` :ref:`glc<amdgpu_synid_glc>` :ref:`dlc<amdgpu_synid_dlc>`
s_buffer_load_dwordx8 :ref:`sdst<amdgpu_synid_gfx1030_sdst_362c37>`, :ref:`sbase<amdgpu_synid_gfx1030_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_59fade>` :ref:`glc<amdgpu_synid_glc>` :ref:`dlc<amdgpu_synid_dlc>`
\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
s_buffer_load_dword :ref:`sdst<amdgpu_synid_gfx1030_sdst_54e16e>`, :ref:`sbase<amdgpu_synid_gfx1030_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_d01a5c>` :ref:`offset20u<amdgpu_synid_smem_offset20u>` :ref:`glc<amdgpu_synid_glc>` :ref:`dlc<amdgpu_synid_dlc>`
s_buffer_load_dwordx16 :ref:`sdst<amdgpu_synid_gfx1030_sdst_3bc700>`, :ref:`sbase<amdgpu_synid_gfx1030_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_d01a5c>` :ref:`offset20u<amdgpu_synid_smem_offset20u>` :ref:`glc<amdgpu_synid_glc>` :ref:`dlc<amdgpu_synid_dlc>`
s_buffer_load_dwordx2 :ref:`sdst<amdgpu_synid_gfx1030_sdst_386c33>`, :ref:`sbase<amdgpu_synid_gfx1030_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_d01a5c>` :ref:`offset20u<amdgpu_synid_smem_offset20u>` :ref:`glc<amdgpu_synid_glc>` :ref:`dlc<amdgpu_synid_dlc>`
s_buffer_load_dwordx4 :ref:`sdst<amdgpu_synid_gfx1030_sdst_0804b1>`, :ref:`sbase<amdgpu_synid_gfx1030_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_d01a5c>` :ref:`offset20u<amdgpu_synid_smem_offset20u>` :ref:`glc<amdgpu_synid_glc>` :ref:`dlc<amdgpu_synid_dlc>`
s_buffer_load_dwordx8 :ref:`sdst<amdgpu_synid_gfx1030_sdst_362c37>`, :ref:`sbase<amdgpu_synid_gfx1030_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_d01a5c>` :ref:`offset20u<amdgpu_synid_smem_offset20u>` :ref:`glc<amdgpu_synid_glc>` :ref:`dlc<amdgpu_synid_dlc>`
s_dcache_inv
s_gl1_inv
s_load_dword :ref:`sdst<amdgpu_synid_gfx1030_sdst_54e16e>`, :ref:`sbase<amdgpu_synid_gfx1030_sbase_020892>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_c40a5a>` :ref:`glc<amdgpu_synid_glc>` :ref:`dlc<amdgpu_synid_dlc>`
s_load_dwordx16 :ref:`sdst<amdgpu_synid_gfx1030_sdst_3bc700>`, :ref:`sbase<amdgpu_synid_gfx1030_sbase_020892>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_c40a5a>` :ref:`glc<amdgpu_synid_glc>` :ref:`dlc<amdgpu_synid_dlc>`
s_load_dwordx2 :ref:`sdst<amdgpu_synid_gfx1030_sdst_386c33>`, :ref:`sbase<amdgpu_synid_gfx1030_sbase_020892>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_c40a5a>` :ref:`glc<amdgpu_synid_glc>` :ref:`dlc<amdgpu_synid_dlc>`
s_load_dwordx4 :ref:`sdst<amdgpu_synid_gfx1030_sdst_0804b1>`, :ref:`sbase<amdgpu_synid_gfx1030_sbase_020892>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_c40a5a>` :ref:`glc<amdgpu_synid_glc>` :ref:`dlc<amdgpu_synid_dlc>`
s_load_dwordx8 :ref:`sdst<amdgpu_synid_gfx1030_sdst_362c37>`, :ref:`sbase<amdgpu_synid_gfx1030_sbase_020892>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_c40a5a>` :ref:`glc<amdgpu_synid_glc>` :ref:`dlc<amdgpu_synid_dlc>`
s_load_dword :ref:`sdst<amdgpu_synid_gfx1030_sdst_54e16e>`, :ref:`sbase<amdgpu_synid_gfx1030_sbase_020892>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_73dae7>` :ref:`offset21s<amdgpu_synid_smem_offset21s>` :ref:`glc<amdgpu_synid_glc>` :ref:`dlc<amdgpu_synid_dlc>`
s_load_dwordx16 :ref:`sdst<amdgpu_synid_gfx1030_sdst_3bc700>`, :ref:`sbase<amdgpu_synid_gfx1030_sbase_020892>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_73dae7>` :ref:`offset21s<amdgpu_synid_smem_offset21s>` :ref:`glc<amdgpu_synid_glc>` :ref:`dlc<amdgpu_synid_dlc>`
s_load_dwordx2 :ref:`sdst<amdgpu_synid_gfx1030_sdst_386c33>`, :ref:`sbase<amdgpu_synid_gfx1030_sbase_020892>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_73dae7>` :ref:`offset21s<amdgpu_synid_smem_offset21s>` :ref:`glc<amdgpu_synid_glc>` :ref:`dlc<amdgpu_synid_dlc>`
s_load_dwordx4 :ref:`sdst<amdgpu_synid_gfx1030_sdst_0804b1>`, :ref:`sbase<amdgpu_synid_gfx1030_sbase_020892>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_73dae7>` :ref:`offset21s<amdgpu_synid_smem_offset21s>` :ref:`glc<amdgpu_synid_glc>` :ref:`dlc<amdgpu_synid_dlc>`
s_load_dwordx8 :ref:`sdst<amdgpu_synid_gfx1030_sdst_362c37>`, :ref:`sbase<amdgpu_synid_gfx1030_sbase_020892>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_73dae7>` :ref:`offset21s<amdgpu_synid_smem_offset21s>` :ref:`glc<amdgpu_synid_glc>` :ref:`dlc<amdgpu_synid_dlc>`
s_memrealtime :ref:`sdst<amdgpu_synid_gfx1030_sdst_386c33>`::ref:`b64<amdgpu_synid_gfx1030_type_deviation>`
s_memtime :ref:`sdst<amdgpu_synid_gfx1030_sdst_386c33>`::ref:`b64<amdgpu_synid_gfx1030_type_deviation>`
@ -1409,7 +1412,7 @@ VOP3
v_add_lshl_u32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_5bb6f2>`, :ref:`src1<amdgpu_synid_gfx1030_src_207976>`, :ref:`src2<amdgpu_synid_gfx1030_src_207976>`
v_add_nc_i16 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_364d7c>`, :ref:`src1<amdgpu_synid_gfx1030_src_1facfe>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
v_add_nc_i32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_5bb6f2>`, :ref:`src1<amdgpu_synid_gfx1030_src_207976>` :ref:`clamp<amdgpu_synid_clamp>`
v_add_nc_u16 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_364d7c>`, :ref:`src1<amdgpu_synid_gfx1030_src_1facfe>` :ref:`clamp<amdgpu_synid_clamp>`
v_add_nc_u16 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_364d7c>`, :ref:`src1<amdgpu_synid_gfx1030_src_1facfe>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
v_add_nc_u32_e64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_5bb6f2>`, :ref:`src1<amdgpu_synid_gfx1030_src_207976>` :ref:`clamp<amdgpu_synid_clamp>`
v_alignbit_b32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_5bb6f2>`, :ref:`src1<amdgpu_synid_gfx1030_src_207976>`, :ref:`src2<amdgpu_synid_gfx1030_src_1facfe>`::ref:`b16<amdgpu_synid_gfx1030_type_deviation>`
v_alignbyte_b32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_5bb6f2>`, :ref:`src1<amdgpu_synid_gfx1030_src_207976>`, :ref:`src2<amdgpu_synid_gfx1030_src_1facfe>`::ref:`b16<amdgpu_synid_gfx1030_type_deviation>`
@ -1809,7 +1812,7 @@ VOP3
v_sub_f32_e64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_5bb6f2>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_207976>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
v_sub_nc_i16 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_364d7c>`, :ref:`src1<amdgpu_synid_gfx1030_src_1facfe>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
v_sub_nc_i32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_5bb6f2>`, :ref:`src1<amdgpu_synid_gfx1030_src_207976>` :ref:`clamp<amdgpu_synid_clamp>`
v_sub_nc_u16 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_364d7c>`, :ref:`src1<amdgpu_synid_gfx1030_src_1facfe>` :ref:`clamp<amdgpu_synid_clamp>`
v_sub_nc_u16 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_364d7c>`, :ref:`src1<amdgpu_synid_gfx1030_src_1facfe>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
v_sub_nc_u32_e64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_5bb6f2>`, :ref:`src1<amdgpu_synid_gfx1030_src_207976>` :ref:`clamp<amdgpu_synid_clamp>`
v_subrev_co_ci_u32_e64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`sdst<amdgpu_synid_gfx1030_sdst_3cd7ad>`, :ref:`src0<amdgpu_synid_gfx1030_src_207976>`, :ref:`src1<amdgpu_synid_gfx1030_src_207976>`, :ref:`ssrc2<amdgpu_synid_gfx1030_ssrc_8dd4e0>` :ref:`clamp<amdgpu_synid_clamp>`
v_subrev_co_u32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`sdst<amdgpu_synid_gfx1030_sdst_3cd7ad>`, :ref:`src0<amdgpu_synid_gfx1030_src_207976>`, :ref:`src1<amdgpu_synid_gfx1030_src_207976>` :ref:`clamp<amdgpu_synid_clamp>`
@ -2076,7 +2079,8 @@ VOPC
gfx1030_m_254bcb
gfx1030_m_f5d306
gfx1030_msg
gfx1030_opt
gfx1030_opt_0d447d
gfx1030_opt_847aed
gfx1030_param
gfx1030_saddr_9cd3cf
gfx1030_saddr_beaa25
@ -2094,8 +2098,8 @@ VOPC
gfx1030_simm32_6f0844
gfx1030_simm32_a3e80c
gfx1030_simm32_be0c1c
gfx1030_soffset_59fade
gfx1030_soffset_c40a5a
gfx1030_soffset_73dae7
gfx1030_soffset_d01a5c
gfx1030_soffset_fef808
gfx1030_src_1facfe
gfx1030_src_207976
@ -2132,31 +2136,31 @@ VOPC
gfx1030_vdata0_fd235e
gfx1030_vdata1_6802ce
gfx1030_vdata1_fd235e
gfx1030_vdata_0aba12
gfx1030_vdata_15d255
gfx1030_vdata_325b78
gfx1030_vdata_4d8ecf
gfx1030_vdata_16d321
gfx1030_vdata_35851e
gfx1030_vdata_56f215
gfx1030_vdata_6802ce
gfx1030_vdata_87fb90
gfx1030_vdata_b2a787
gfx1030_vdata_890652
gfx1030_vdata_a9ff5a
gfx1030_vdata_c08393
gfx1030_vdata_c61803
gfx1030_vdata_e016a1
gfx1030_vdata_fd235e
gfx1030_vdst_2ea017
gfx1030_vdst_322561
gfx1030_vdst_3d7dcf
gfx1030_vdst_463513
gfx1030_vdst_473a69
gfx1030_vdst_48d3a8
gfx1030_vdst_48e42f
gfx1030_vdst_5d50a1
gfx1030_vdst_69a144
gfx1030_vdst_719833
gfx1030_vdst_709347
gfx1030_vdst_81a6ed
gfx1030_vdst_89680f
gfx1030_vdst_a49b76
gfx1030_vdst_bdb32f
gfx1030_vdst_d0dc43
gfx1030_vdst_d7c57e
gfx1030_vdst_f47754
gfx1030_vdst_d71f1c
gfx1030_vdst_dd8a32
gfx1030_vdst_f8490d
gfx1030_vsrc_533a4e
gfx1030_vsrc_6802ce

42
llvm/docs/AMDGPU/gfx1030_hwreg.rst
View File

@ -41,27 +41,27 @@ or :ref:`absolute expressions<amdgpu_synid_absolute_expression>`.
Defined register *names* include:
==================== ==========================================
Name Description
==================== ==========================================
HW_REG_MODE Shader writeable mode bits.
HW_REG_STATUS Shader read-only status.
HW_REG_TRAPSTS Trap status.
HW_REG_HW_ID1 Id of wave, simd, compute unit, etc.
HW_REG_HW_ID2 Id of queue, pipeline, etc.
HW_REG_GPR_ALLOC Per-wave SGPR and VGPR allocation.
HW_REG_LDS_ALLOC Per-wave LDS allocation.
HW_REG_IB_STS Counters of outstanding instructions.
HW_REG_SH_MEM_BASES Memory aperture.
HW_REG_TBA_LO tba_lo register.
HW_REG_TBA_HI tba_hi register.
HW_REG_TMA_LO tma_lo register.
HW_REG_TMA_HI tma_hi register.
HW_REG_FLAT_SCR_LO flat_scratch_lo register.
HW_REG_FLAT_SCR_HI flat_scratch_hi register.
HW_REG_POPS_PACKER pops_packer register.
HW_REG_SHADER_CYCLES Current graphics clock counter value.
==================== ==========================================
============================== ==========================================
Name Description
============================== ==========================================
HW_REG_MODE Shader writeable mode bits.
HW_REG_STATUS Shader read-only status.
HW_REG_TRAPSTS Trap status.
HW_REG_HW_ID1 Id of wave, simd, compute unit, etc.
HW_REG_HW_ID2 Id of queue, pipeline, etc.
HW_REG_GPR_ALLOC Per-wave SGPR and VGPR allocation.
HW_REG_LDS_ALLOC Per-wave LDS allocation.
HW_REG_IB_STS Counters of outstanding instructions.
HW_REG_SH_MEM_BASES Memory aperture.
HW_REG_TBA_LO tba_lo register.
HW_REG_TBA_HI tba_hi register.
HW_REG_TMA_LO tma_lo register.
HW_REG_TMA_HI tma_hi register.
HW_REG_FLAT_SCR_LO flat_scratch_lo register.
HW_REG_FLAT_SCR_HI flat_scratch_hi register.
HW_REG_POPS_PACKER pops_packer register.
HW_REG_SHADER_CYCLES Current graphics clock counter value.
============================== ==========================================
Examples:

13
llvm/docs/AMDGPU/gfx1030_opt_0d447d.rst Normal file
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@ -0,0 +1,13 @@
..
**************************************************
* *
* Automatically generated file, do not edit! *
* *
**************************************************
.. _amdgpu_synid_gfx1030_opt_0d447d:
opt
===
This is an optional operand. It must be used if and only if :ref:`lds<amdgpu_synid_lds>` is omitted.

2
llvm/docs/AMDGPU/gfx1030_opt.rst → llvm/docs/AMDGPU/gfx1030_opt_847aed.rst
View File

@ -5,7 +5,7 @@
* *
**************************************************
.. _amdgpu_synid_gfx1030_opt:
.. _amdgpu_synid_gfx1030_opt_847aed:
opt
===

6
llvm/docs/AMDGPU/gfx1030_soffset_c40a5a.rst → llvm/docs/AMDGPU/gfx1030_soffset_73dae7.rst
View File

@ -5,16 +5,18 @@
* *
**************************************************
.. _amdgpu_synid_gfx1030_soffset_c40a5a:
.. _amdgpu_synid_gfx1030_soffset_73dae7:
soffset
=======
An offset added to the base address to get memory address.
An offset from the base address.
* If offset is specified as a register, it supplies an unsigned byte offset.
* If offset is specified as a 21-bit immediate, it supplies a signed byte offset.
Note that an *immediate* offset may be specified using either :ref:`simm21<amdgpu_synid_simm21>` operand or :ref:`offset21s<amdgpu_synid_smem_offset21s>` modifier, but not both.
*Size:* 1 dword.
*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`null<amdgpu_synid_null>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`simm21<amdgpu_synid_simm21>`

6
llvm/docs/AMDGPU/gfx1030_soffset_59fade.rst → llvm/docs/AMDGPU/gfx1030_soffset_d01a5c.rst
View File

@ -5,12 +5,14 @@
* *
**************************************************
.. _amdgpu_synid_gfx1030_soffset_59fade:
.. _amdgpu_synid_gfx1030_soffset_d01a5c:
soffset
=======
An unsigned 20-bit offset added to the base address to get memory address.
An unsigned offset from the base address. My be specified as either a register or a 20-bit immediate.
Note that an *immediate* offset may be specified using either :ref:`uimm20<amdgpu_synid_uimm20>` operand or :ref:`offset20u<amdgpu_synid_smem_offset20u>` modifier, but not both.
*Size:* 1 dword.

4
llvm/docs/AMDGPU/gfx1030_vdata_c61803.rst → llvm/docs/AMDGPU/gfx1030_vdata_0aba12.rst
View File

@ -5,7 +5,7 @@
* *
**************************************************
.. _amdgpu_synid_gfx1030_vdata_c61803:
.. _amdgpu_synid_gfx1030_vdata_0aba12:
vdata
=====
@ -16,6 +16,6 @@ Optionally may serve as an output data:
* If :ref:`glc<amdgpu_synid_glc>` is specified, gets the memory value before the operation.
*Size:* 1 dword by default. :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
*Size:* 1 dword.
*Operands:* :ref:`v<amdgpu_synid_v>`

4
llvm/docs/AMDGPU/gfx1030_vdata_b2a787.rst → llvm/docs/AMDGPU/gfx1030_vdata_16d321.rst
View File

@ -5,7 +5,7 @@
* *
**************************************************
.. _amdgpu_synid_gfx1030_vdata_b2a787:
.. _amdgpu_synid_gfx1030_vdata_16d321:
vdata
=====
@ -16,6 +16,6 @@ Optionally may serve as an output data:
* If :ref:`glc<amdgpu_synid_glc>` is specified, gets the memory value before the operation.
*Size:* 2 dwords by default. :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
*Size:* 2 dwords.
*Operands:* :ref:`v<amdgpu_synid_v>`

6
llvm/docs/AMDGPU/gfx1030_vdata_325b78.rst → llvm/docs/AMDGPU/gfx1030_vdata_35851e.rst
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@ -5,7 +5,7 @@
* *
**************************************************
.. _amdgpu_synid_gfx1030_vdata_325b78:
.. _amdgpu_synid_gfx1030_vdata_35851e:
vdata
=====
@ -16,10 +16,10 @@ Optionally may serve as an output data:
* If :ref:`glc<amdgpu_synid_glc>` is specified, gets the memory value before the operation.
*Size:* depends on :ref:`dmask<amdgpu_synid_dmask>` and :ref:`tfe<amdgpu_synid_tfe>`:
*Size:* depends on :ref:`dmask<amdgpu_synid_dmask>`:
* :ref:`dmask<amdgpu_synid_dmask>` may specify 1 data element for 32-bit-per-pixel surfaces or 2 data elements for 64-bit-per-pixel surfaces. Each data element occupies 1 dword.
* :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
Note: the surface data format is indicated in the image resource constant but not in the instruction.

4
llvm/docs/AMDGPU/gfx1030_vdata_87fb90.rst → llvm/docs/AMDGPU/gfx1030_vdata_890652.rst
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@ -5,7 +5,7 @@
* *
**************************************************
.. _amdgpu_synid_gfx1030_vdata_87fb90:
.. _amdgpu_synid_gfx1030_vdata_890652:
vdata
=====
@ -16,6 +16,6 @@ Optionally may serve as an output data:
* If :ref:`glc<amdgpu_synid_glc>` is specified, gets the memory value before the operation.
*Size:* 4 dwords by default. :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
*Size:* 4 dwords.
*Operands:* :ref:`v<amdgpu_synid_v>`

6
llvm/docs/AMDGPU/gfx1030_vdata_4d8ecf.rst → llvm/docs/AMDGPU/gfx1030_vdata_a9ff5a.rst
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@ -5,7 +5,7 @@
* *
**************************************************
.. _amdgpu_synid_gfx1030_vdata_4d8ecf:
.. _amdgpu_synid_gfx1030_vdata_a9ff5a:
vdata
=====
@ -16,10 +16,10 @@ Optionally may serve as an output data:
* If :ref:`glc<amdgpu_synid_glc>` is specified, gets the memory value before the operation.
*Size:* depends on :ref:`dmask<amdgpu_synid_dmask>` and :ref:`tfe<amdgpu_synid_tfe>`:
*Size:* depends on :ref:`dmask<amdgpu_synid_dmask>`:
* :ref:`dmask<amdgpu_synid_dmask>` may specify 2 data elements for 32-bit-per-pixel surfaces or 4 data elements for 64-bit-per-pixel surfaces. Each data element occupies 1 dword.
* :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
Note: the surface data format is indicated in the image resource constant but not in the instruction.

6
llvm/docs/AMDGPU/gfx1030_vdst_48d3a8.rst → llvm/docs/AMDGPU/gfx1030_vdst_2ea017.rst
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@ -5,7 +5,7 @@
* *
**************************************************
.. _amdgpu_synid_gfx1030_vdst_48d3a8:
.. _amdgpu_synid_gfx1030_vdst_2ea017:
vdst
====
@ -14,9 +14,9 @@ Image data to load by an *image_gather4* instruction.
*Size:* 4 data elements by default. Each data element occupies either 32 bits or 16 bits depending on :ref:`d16<amdgpu_synid_d16>`.
:ref:`d16<amdgpu_synid_d16>` and :ref:`tfe<amdgpu_synid_tfe>` affect operand size as follows:
:ref:`d16<amdgpu_synid_d16>` affects operand size as follows:
* :ref:`d16<amdgpu_synid_d16>` specifies that data elements in registers are packed; each value occupies 16 bits.
* :ref:`tfe<amdgpu_synid_tfe>` adds one dword if specified.
*Operands:* :ref:`v<amdgpu_synid_v>`

19
llvm/docs/AMDGPU/gfx1030_vdst_322561.rst Normal file
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@ -0,0 +1,19 @@
..
**************************************************
* *
* Automatically generated file, do not edit! *
* *
**************************************************
.. _amdgpu_synid_gfx1030_vdst_322561:
vdst
====
Instruction output: data read from a memory buffer.
This is an optional operand. It must be used if and only if :ref:`lds<amdgpu_synid_lds>` is omitted.
*Size:* 1 dword.
*Operands:* :ref:`v<amdgpu_synid_v>`

4
llvm/docs/AMDGPU/gfx1030_vdst_5d50a1.rst → llvm/docs/AMDGPU/gfx1030_vdst_709347.rst
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@ -5,13 +5,13 @@
* *
**************************************************
.. _amdgpu_synid_gfx1030_vdst_5d50a1:
.. _amdgpu_synid_gfx1030_vdst_709347:
vdst
====
Instruction output: data read from a memory buffer.
*Size:* 1 dword by default. :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
*Size:* 1 dword.
*Operands:* :ref:`v<amdgpu_synid_v>`

21
llvm/docs/AMDGPU/gfx1030_vdst_719833.rst
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@ -1,21 +0,0 @@
..
**************************************************
* *
* Automatically generated file, do not edit! *
* *
**************************************************
.. _amdgpu_synid_gfx1030_vdst_719833:
vdst
====
Instruction output: data read from a memory buffer.
If :ref:`lds<amdgpu_synid_lds>` is specified, this operand is ignored by H/W and data are stored directly into LDS.
*Size:* 1 dword by default. :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
Note that :ref:`tfe<amdgpu_synid_tfe>` and :ref:`lds<amdgpu_synid_lds>` cannot be used together.
*Operands:* :ref:`v<amdgpu_synid_v>`

4
llvm/docs/AMDGPU/gfx1030_vdst_f47754.rst → llvm/docs/AMDGPU/gfx1030_vdst_81a6ed.rst
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@ -5,13 +5,13 @@
* *
**************************************************
.. _amdgpu_synid_gfx1030_vdst_f47754:
.. _amdgpu_synid_gfx1030_vdst_81a6ed:
vdst
====
Instruction output: data read from a memory buffer.
*Size:* 4 dwords by default. :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
*Size:* 3 dwords.
*Operands:* :ref:`v<amdgpu_synid_v>`

4
llvm/docs/AMDGPU/gfx1030_vdst_a49b76.rst → llvm/docs/AMDGPU/gfx1030_vdst_d71f1c.rst
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@ -5,13 +5,13 @@
* *
**************************************************
.. _amdgpu_synid_gfx1030_vdst_a49b76:
.. _amdgpu_synid_gfx1030_vdst_d71f1c:
vdst
====
Instruction output: data read from a memory buffer.
*Size:* 3 dwords by default. :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
*Size:* 2 dwords.
*Operands:* :ref:`v<amdgpu_synid_v>`

4
llvm/docs/AMDGPU/gfx1030_vdst_d7c57e.rst → llvm/docs/AMDGPU/gfx1030_vdst_dd8a32.rst
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@ -5,13 +5,13 @@
* *
**************************************************
.. _amdgpu_synid_gfx1030_vdst_d7c57e:
.. _amdgpu_synid_gfx1030_vdst_dd8a32:
vdst
====
Instruction output: data read from a memory buffer.
*Size:* 2 dwords by default. :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
*Size:* 4 dwords.
*Operands:* :ref:`v<amdgpu_synid_v>`